JPS61212889A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image processing device, and particularly to a display device that displays text (
The present invention relates to a display device that displays text, still images, moving images, etc.

[Conventional technology]

Lask scanner cathode ray cathode ray tube (hereinafter referred to as CRT)
The function of displaying and processing information such as text, still images, and videos stored in memory (e.g., using dynamic memory or fresh memory) by using it as a display device is an important function of image processing devices. There is one. Generally, when displaying text or still images on a rask-scanning C1 (T), the information that should be displayed on the screen is edited and stored in the refresh memory, and then synchronized with the scanning timing of the CRT. A method is adopted in which the data is sequentially read and displayed.In this method, the CR
The T screen is regularly divided into a large number of small sections, each subsection corresponds to one character or one graphic element, and text or still images are expressed as a series of characters and graphic elements. It is something to do.

Figure 3 shows a central processing unit (hereinafter referred to as CPU) 51° display address register 542 and a reflex cinema memory (hereinafter referred to as video memory) in which display data is edited and stored.
52. FIG. 2 is a block diagram of a conventional display device including a display device and its peripheral circuits.

The display data is sent from the CPU 51 to the part 1 of the video memory 52.
It can be input/output by specifying /.

The display data written in the video memory 52 is read out in the order specified by the display address register 54, converted into a serial video signal 61 by the display data 1/register 534, and supplied to the CRT. In addition, the display (
Generates a deflection synchronizing signal 59.60 for horizontal and vertical deflection of the CRT5B, and also performs image multiplication.
Send it out on 8th.

Display is performed by repeating such operations in synchronization with the scanning timing of the CRT.

Recently, in addition to the display of text and still images, video display in which characters and figures are moved to arbitrary positions on the screen and displayed is required for applications such as games. FIG. 4 is a block diagram of a display device applied to such uses. For example, when displaying a moving object such as an airplane moving in the sky, this display device displays the scenery on the ground as a still image, and displays the moving object such as an airplane as a moving image. . The portion displaying still images is the portion surrounded by dotted lines in the figure, and has the same configuration and operation as the display device shown in FIG. 3 described above.

The attribute memo 1J112j of the part where the moving image is displayed and the attributes of the moving image figure, such as what kind of figure to display, and the like are stored, and can be rewritten by the CPU 10I. The character/figure generator 113 stores display data of moving image figures. During the display period, the coincidence detection circuit 115 extracts a moving image figure to be displayed based on the waste information at each scanning position in the vertical direction of the scanning line, and display data corresponding to that figure is displayed as a text. , figure generator 1
13 and stored in the buffer memory 114 so as to be displayed at the horizontal position specified by the Q attribute t'pt information. The contents of the buffer memory 114 are read out sequentially in synchronization with the scanning system, and are displayed as display data 1.
/ register 116 makes the serial video signal ]19. The serial video signal 119 is mixed with the still image video old code 111 51
20 and supplied to a CRT for display.

Display is performed by repeating the above operations.

Generally, display data in the video memory 102, etc. in such a display device is stored in a CP for re-editing characters and graphics.
U10'l In this way, from the CPU 10'l to the video memory 102 -
When a pair of memory access requests occur, switch 1
Addressing information from the CPU 10I is supplied to the video memory 102 by 06. The display data read out from the video memory 102 is taken into the CPUI 01, processed, and then stored again at a designated location. C.P.
Such a memory access request from U occurs regardless of the I display timing on the CRT, so if the CPU's memory access is given unconditional priority, if a memory access request is issued during the display period, Due to the address specification of the display address register 104, display data cannot be read out, which causes a problem.

[Problems to be Solved by the Invention] As described above, in the conventional display device described above, when the CPU accesses the video memory during the display period, the video memo 1
Since an address different from the monthly display address is supplied, the display is disturbed and normal display operation is not performed. Therefore, in the conventional display device, in response to a memory access request from the CPU, the video memory can only be released during vertical and horizontal blanking periods other than the display period that does not affect the display. For this reason, the CPU accesses the video memory for display data processing, and the access is required for a period of several tens of microseconds every 9 degrees, making operability very slow.
This has the drawback that it is not suitable as a display device where frequent display data processing is required, since the CPU's inherent ability to perform various calculations and control is reduced.

Furthermore, since still image display data and video display data must be set independently in separate video memory systems, it is possible, for example, to use part of the still image display data as video display data. I can't. In addition, when looking at the system as a whole, it is necessary to configure address and data control circuits, parallel-to-serial conversion shift l/meta, etc. separately for the still image display system and the video display system, resulting in complexity of input and output lines. , the circuit scale is quite large.

[Purpose of the invention]

The purpose of the present invention is to allow the CPU to read and write to the video memory without affecting the display at all even when the CPU accesses the video memory, and without being controlled by the display timing. , improve data bus usage efficiency, maximize display data processing speed and CPU utilization, and share as much of the hardware required for still image and video display systems as possible. The object of the present invention is to provide an inexpensive display device.

[Means for solving problems]

The display device of the present invention includes an attribute memory that stores at least video identification information and display position information, a video memory that stores video and still image display data, and edits and stores display data read from the video memory. An editing memory that generates a display signal to a display device, a display at 1 nos generation circuit that indicates a display address, and a position detection circuit that reads out the contents of the attribute memory and detects that the display position information of the video is within a predetermined range. and the third atto (
a second addressing means for addressing the video memory based on the video identification information read from the attribute memory; and a CPU for addressing the attribute memory or the video memory and inputting/outputting data. the first and second addressing means and the access means are operated exclusively in a predetermined priority order based on the output of the position detection circuit and the operation identification signal of the CPU; The present invention is characterized in that when there is an operation from the processing device, updating of the edit address in the display address generation circuit and the edit memory is suppressed.

〔Example〕

Next, embodiments of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. The video memory 1 stores display data of text, still images, and some moving images equivalent to several CRT screens. The attribute memory 19 stores video identification information indicating the type of video figure to be displayed, display position information specifying the position where it should be displayed, color information, and other attribute information necessary for display.
9- It is paid. The first editing memory 15 and the second editing memory 16 each have a capacity to store display data necessary for displaying at least one scanning line, and are used alternately for writing and reading for each scanning line. Ru. Under the control of the editing memory switching circuit 17, the output of the write address generation circuit 13 is supplied to the editing memory allocated for writing during the scanning period, and the display data read from the video memory 1 is displayed. It is directly converted into corresponding optical data, edited and stored.

Further, the output of the read address generation circuit 14 is supplied to the editing memory allocated for reading as an at 1/s, and the data read from this address is sent to the parallel-to-serial conversion shift register via the data selection circuit 18. 3
loaded into. The attribute memory 19 includes an address line 31 for specifying an address and an input/output line 33 for data.
Similarly, an address line 32 and a data input/output line 34 are connected to the video memory 1. Further, each memory is connected to a memory fill signal 6 for instructing a write operation from the CPU, and a memory read signal 7 for instructing read agglomeration.

When pledging display data and attribute information to the video memory 1 and the photomemo IJ 19, first, the At1NOS selection circuit 12t21 is switched by the memory access request signal 11, and the value of the At1NOS bus 4 of the CPU is set to the address line 31. .32, and data input/output lines 33 and 34 are selected via data buffers 27 and 30.
is connected to data bus 5'). The CPU specifies addresses for these lines to the video memory 1 and the storage memory 19, and sends data thereto. When a required number of predetermined display data is written into each memory and I' is also stored, memory access for displaying these data is started. Address selection circuit 12
The output of the displayed at1/nos generation/conversion 2 is switched so that it is in contact with the at1/sline 32 of the video memory 1. At the same time, the memory read signal 6 is activated 7%, and the display data t read from the video memory 1 is written into the edit memory, which is operating for writing during the current scanning period, by the edit memory pledge signal 226. It will be done. In the display address generation circuit, each time the display data of the video memory 1 is read, the display at1nos is updated in order to read the next display data, and the video memory 1 is continuously accessed based on the newly generated display address. Further, the edit memory write address generation circuit 13 updates the address of the display data, and writes the edit memory based on the newly created edit memory address. In this way, the still image display data is sequentially stored in the writing editing memory by repeating the reading and writing of the display data into the first editing memory. On the other hand, the output of the attribute counter 20 is switched to be connected to the address 31 in the attribute memory 19 by the address selection circuit 21 . The attribute counter 20 is reset by #l every scan, and provides an address for sequentially reading data from the attribute memory 19. The attribute memory 19 identifies the type of solid object to be displayed, and outputs moving image identification information used as address information of the video memory 1, vertical display position information (Y), horizontal display position information (X), and the like. Y is input to the subtraction circuit 23 and subtracted from the output (VC) of the vertical line counter 22 (VC-Y→Δ
). The vertical line counter 22 indicates the next position to be scanned in the vertical direction, and a value one more than the actual position of the scanning line is entered. □The content is also counted up by one. The output (ΔY) of the subtraction circuit 23 is input to a comparison circuit 24, where it is compared and detected to see if the value is within a preset range. This is to check whether there is a figure to be displayed in the contents of the attribute memory 19 at the next scanning position in the vertical direction of the scanning line. This operation control is performed by successively reading out the contents of the attribute memory 19 during one scanning period of the scanning line. When a figure to be displayed is detected by the subtraction circuit 23 and the comparison circuit 24, the position detection signal 25 is activated. Position detection signal 25 includes display address generation circuit 2 and address selection circuit 1
2°-13= Attribute counter 20 and pledged address generation circuit 13
First, the address selection circuit 12 selects the video identification information read out from the attribute memory 19 and uses it as address designation information in the video memory 1, and at the same time updates the display address of the display address generation port w12. The operation of the attribute counter 20 is also stopped.

Next, in the write address generation circuit 13, the update of the write address of the still image display data is suspended, and the horizontal display position information (X) read out from the attribute memory 19 at the same time as the video identification information is taken in. The edit memory write address is generated based on the . The display data of the moving image read from the image memory 1 according to the moving image identification information is edited and stored in the position specified by the address of the editing memory allocated for writing. When the writing of the predetermined display data of the detected moving picture figure into the editing memory is completed, the position detection signal 25 is deactivated, and the address line 32 is set by the address selection (b) path 12 to the display address 14=s generation circuit 2. is switched to be connected again to the output of Further, the update of the display address, the operation of the counter 20, and the update of the write address of the still image display data in the write address generation circuit 13 are restarted, and the still image display data processing is performed again. In this way, when a moving image figure to be displayed is detected from the attribute memory 19,
The still image display data is read from the video memory 1, and the operation side that is continuously edited and stored in the editing memory is temporarily suspended, and the moving image display data is processed first.

In this way, by repeating the reading of still image and video display data to be displayed during the next display period and writing to the editing memory, all the display data for one run is edited and stored in the same editing memory. Ru.

On the other hand, consecutive addresses are periodically supplied to the read editing memory from the read address generation circuit 14 in synchronization with the display timing, and data is read out sequentially.

The output of the readout memory is timed ft1lj# by the load clock 8 and set in the parallel-to-serial conversion shift register β. This is shifted in accordance with the shift clock 9 and becomes a serial video signal 10, which is then supplied to the CRT.

By repeating this series of operations, one scanning line is displayed. When the display for one scanning line is completed, in order to read out the contents of the paste memory for the display of the next scanning, the editing memory that was operating for writing etc. is changed to the editing memory under the control of the editing memory switching circuit 17. The memory read address is supplied to the editing memory that was operating for reading, and the editing memory write address is supplied to the editing memory, and display of the next scanning line is started. The display is maintained by repeating the above operations.

Next, an operation timing diagram will be described in the case where an access request is made from the CPU to the video memory 1 in order to perform display data processing such as graphic drawing and editing during a display operation as shown in C.

FIG. 5 is a timing diagram showing the relationship between the address of the video memory, the write address 1 of the editing memory, and the blue fill and read signals of the memory when an access request is made to the video memory 1 during the display period. be. MCm-2, M
Cm-1 is a normal display cycle, and display at1nos or moving image identification information (DADn-0, DADn) is supplied to the video memory 1. Also, the edit memory write signal 26 is activated, and the display data that has been read out is edited and stored in the edit memory. MCrn and MCHI+,
The cycle is a video memory access other than display, and the memory access request signal 11 is activated.

First, under the control of the address 8 selection circuit 12, the read address (RDA D R) from the CPU is set to the video memory 1.
given to. Display data (l(DD)) is output to the data bus 5 via the data buffer 27 in response to the memory read signal 6, and is fetched and processed by the CPU or a device that processes image information (MCn). A write address (WRADIυ) is given to the video memory 1. At the same time, the memory write signal 7 is activated and the write display data (WRD) after processing 4 is stored in the video memory (Mm+t).

l7- When the access request timing by CF'U ends, the output of the display address generation circuit 2 or the output of the attribute memory 19 (DADn-1-i) is again supplied to the video memory 1, and the display data (D port +1) is read. The data is output and stored in the writing editing memory & (MCm 10g).

In this way, during the period when the memory access request signal 11 is activated, address information from the CPU is supplied to the video memory 1 instead of the display address, and video memory access from the CPU has priority over access for display. It is done as follows. Further, under the control of the memory access request signal 11, the updating of the display address of the display address generation circuit 2 and the updating of the write address of the editing memory are stopped.

However, the memory access request signal 11 has no effect on the read system of the editing memory.

Therefore, even if a memory access request occurs, reading from the editing memory is performed continuously in synchronization with CRT scanning (display timing). In addition, it is necessary to store display data for one scanning line in the editing memory for writing.
The number of read cycles of the video memory is less than the total number of accesses that occur during one scanning period, and all remaining cycles can be used at necessary timings as access cycles for display data processing by the CPU.

〔Effect of the invention〕

As explained above, the present invention stores still image and moving image display data in the same memory, and when a request for editing or storing the moving image display data in the temporary memory occurs. By temporarily suspending the processing currently being performed on display data for still images and giving priority to video processing, the operation of detecting video shapes to be displayed from the attribute memory can be performed on still images. As a result of the display data, it is possible to perform the storage process in parallel, so that a large number of moving images can be set. Moreover, when a figure to be displayed is detected, the display data for that figure can be processed immediately, so there is no need to temporarily store and store the attribute information of the detected moving image figure until it can be processed. , the circuit configuration of the device is extremely simple. In addition, there is no need to configure control circuits that are essential for display, such as video memory and parallel-to-serial conversion shift registers, separately for still image display systems and video display systems as in conventional display devices, and the minimum necessary hardware is required. This has the effect of realizing a still image and moving image display device.

Further, according to the present invention, there is provided a device that can immediately stop access for display in response to a video memory access request from the CPU, allow the CPU to control the video memory, and has no effect on the display. realizable. Therefore, C.P.
U can control the video memory without being aware of the display state, such as during the display period or blanking period. Also,
Even if the video memory is accessed, there is almost no need to wait until the blanking period, which does not cause display disturbances, and by drastically reducing CPU waiting time, CF'U's original calculations and control processing can be performed. capacity and bus usage efficiency can be maximized. In addition, a memory with a capacity that can store display data for one scanning line is required as an editing memory, but due to the remarkable increase in memory integration and price reduction in recent years, it is relatively easy to use from an economic standpoint. realizable. Further, the address supplied to the read buffer memory may have a value that changes continuously in synchronization with the display timing, and generally such a value generates a synchronization signal necessary for timing control of C'RT. It can be obtained from the output of counters used in the section, and does not require a dedicated control circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of displaying characters and figures using a conventional display, FIG. 3 is a block diagram of a conventional still image display device, and FIG. The figure is a block diagram of a conventional moving image display device, and FIG. 5 is a diagram of operation timing in one embodiment of the present invention shown in FIG. ■...Video memory, 2...Display address generation circuit, 3...Parallel-serial conversion shift register, 4...Address bus, 5... ...Data bus, 6...Memory read signal, 7...
...Memory write signal, 8...Load clock, 9...Shift clock, 10...
...Serial video signal, 11...Memory access request signal, 12, 21...Address selection circuit, 1
3...i' key address generation circuit, 14...
...Read address generation circuit, 15', 16...
...Editing memory, 17...Editing memory switching circuit, 18...Data selection circuit, 19...
...Attribute memory, 20...Attribute counter, 2
2... Vertical line counter, 23...
Subtraction circuit, 24... Comparison circuit, 25...
・Position detection signal, 26...M8 memory write signal, 27.28, 29.30...Data buffer, 31.32...Address line, 33
．． 34...Data input/output line, 51.101
...CP'(J, 52.102...Video memory, 53,103゜116...Data register for display, 54.104...For display Address register, 55.105...Synchronization signal generator, 56,'10'6,'118...Switcher, 57,107...Video signal amplifier, 58° 1
08...CRT, 59, 1'09...
・Horizontal synchronization signal, 60, 110... Vertical synchronization signal, 61, 111° 119... Serial video signal, 112... Elliptical memory, 113...・
Character, figure generator, 114...-Buffer memory, 115... Match detection circuit, 117...
-Address register, 120...mixer.

Claims (1)

[Claims] a first storage device that stores identification information and display position information of moving images; a second storage device that stores display data of moving images and still images; and editing display data read from the second storage device; a third storage device that stores information and generates a display signal to a display device; a display address generation circuit that indicates a display address; and a display address generation circuit that reads out the contents of the first storage device so that the display position information of the moving image is within a predetermined range. a position detection circuit for detecting a certain state; a first addressing means for addressing the second storage device based on the display address of the display address generation circuit; a second addressing means for addressing the second storage device based on video identification information; and an access means for a central processing unit to address the first or second storage device and input/output data. The first and second addressing means and the access means are operated exclusively in a predetermined priority order based on the output of the position detection circuit and the operation identification signal of the central processing unit, and A display device, characterized in that when there is an operation from a processing device, updating of the edit address in the display address generation circuit and the third storage device is suppressed.