JPS61212724A - Capacitance type displacement converter - Google Patents

Abstract

PURPOSE:To eliminate error factors preventing effect of the floating capacitance in substance, by including an amplification means with an electrostatic capacitance connected between input and output terminals and a current control means with the value and direction of current controlled according to the output level thereof. CONSTITUTION:A power source for energizing a buffer gate G1 is provided with current control circuits CC1 and CC2 respectively on the high potential sice +E and on the low potential side COM while being controlled by the voltage at the output terminal of the gate G1. When the output voltage of the gate G1 is zero, the output current of the current control circuit CC1 is at its maximum and zero at the CC2 while the opposite characteristic to it is shown when the output voltage thereof is at its maximum +E. Thus, each one end of floating capacitances CCP1 and CCP2 corresponding to respective end of the current control circuits CC1 and CC2 is converted separately to power sources providing a constant voltage +E and a common potential point being zero potential and hence, there is no effect caused by any drastic variations in the voltage at the output terminal of the gate G1 to +E or zero. The floating capacitances CCP1 and CCP2 has no effect on the input terminal of the gate G1.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a capacitive displacement converter that converts physical displacement based on changes in physical quantities such as pressure and tension into electrical signals via capacitance.

<Prior Art> As a conventional displacement converter of this type, for example, a "capacitive displacement converter" (Japanese Patent Laid-Open No. 57-26711) has been proposed. This capacitive displacement converter is shown and explained in FIGS. 10 to 13.

FIG. 10 is a sectional view showing an example of a single capacitance type sensor. When P is applied, the movable electrode 4 moves and the capacitance CM between the electrode 4 and sp changes.

FIG. 11 shows the equivalent circuit of FIG. 10 in consideration of the presence of distributed capacitance. There is a distributed capacitance c8□ between the fixed electrode sp and the case P, and a distributed capacitance C between the movable electrode 4 and the case F.
B2 is intervening in each case.

FIG. 12 shows a conventional capacitive displacement converting device in which a converting circuit is constructed according to the circuit shown in FIG.

A capacitor CM is connected between the input and output terminals of the buffer gate G1, and positively feeds back the voltage at the output terminal to the input terminal. Sara K
, the output terminal of buffer gate G1 is connected to buffer gate G It is connected to the input terminal of the circuit, and the voltage at its output terminal is negatively fed back to the input terminal. CCp is a stray capacitance generated across the constant value current limiting circuit CC. A voltage of 10 B is applied to each power supply terminal of the puffer game) G and inverter G2 to energize them.

As a result of the above-described repetition K of positive feedback and negative feedback, repetitive oscillation waveforms as shown in FIGS.

If the voltage change at the input end of the buffer gate G1 is 01, the constant value discharge current of the constant value current limiting circuit CC is 1□, and the discharge time is t□, then the following equation holds true.

11tl −1, (CM E-CCp”)
(2) From equations (1) and (2), it can be seen that the distributed capacitance C81 is located between the output end of the buffer gate G1 and the common potential point, and is not related to the charging of the capacitance CM. Since the capacitance fC8□ is eliminated in the process of deriving equation (3), no problem arises.

<Problems to be Solved by the Invention> However, as shown in equation (3), due to the existence of stray capacitance CCp existing between the input and output terminals of the constant value current limiting circuit CC, when this value fluctuates, the discharge time t1 When the capacitance C- is determined from the oscillation frequency due to the fluctuation of the repetition period, an error occurs.

Means for Solving the Problems> In order to solve the above problems, the present invention has a capacitance that changes in response to a physical change to be detected, and a method that connects this capacitance between its input and output terminals. and a current control means whose current value and direction are controlled according to the output level of the amplification means, and the output current of the current control means is supplied to the input terminal of the amplification means. It is composed of

<Example> Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. The connection is the same as in FIG. 12 in that the voltage at the output terminal is positively fed back to the input terminal. However, in the embodiment shown in FIG. 1, the current control circuit connects CCI and CC2 to the high potential side terminal E and low potential side COM of the power supply that energizes the buffer gate G1, respectively.
The connection point of the circuit in which these circuits are connected in series between the power supplies is connected to the input terminal of the buffer gate G1, and the current control circuits CCV and CC2 are both connected to the voltage at the output terminal of the buffer gate G1. y) The point of control is different from the case of Fig. 12. Current control circuit CC1,
The characteristics of the output current with respect to the output voltage of the buffer gate G1 of CC2 are as shown in Fig. 2. When the output voltage of the buffer gate G is zero, the output current of the current control circuit CCI is the maximum value, and the output current of CC2 is zero, and the output current of the buffer gate G1 is zero. When the output voltage of G1 is the maximum value E, the opposite characteristic is exhibited. Since the output voltage of buffer gate G1 takes two values, zero or +E, each output current of current control circuits CCV and CC2 is the maximum current when one is zero, as shown in Figure 3 (a) and (b). Takes a value.

Therefore, the operation is similar to that shown in FIG. 12, but in the case of FIG. 1, the stray capacitances CCp1 . Since one end of CCp2 is connected to the power supply that provides a constant voltage element E and a common potential point that is zero potential, even if the voltage at the output end of the buffer gate G□ fluctuates significantly from 10B to zero, Not affected by it. Therefore, the input terminal of the buffer gate G1 is not affected by the stray capacitances ccp□ and CCp2. However, in the case of Fig. 12, one end of the stray capacitance CCp of the constant value current limiting circuit is connected to the output end of the inverter G2, and is affected by large potential fluctuations. It appeared as. Note that the distributed capacitance C81''S□ is eliminated in the same manner as in equations (1) to (3).

FIG. 4 is a circuit diagram illustrating the embodiment shown in FIG. 1 in more detail. The output terminal of the buffer gate G□ is connected to a resistor R1o and a transistor Q11. Q1
It is connected to the input end of the buffer gate G1 via □. Each transistor Q□1. Q1□C is connected to the power supply voltage 1B@ to form a current mirror circuit. Furthermore, the output terminal of buffer gate G1 is connected to resistor R2o and MO8 type FE.
It is connected to the input terminal of the buffer gate G□ via transistors Q2□ and Q2□ formed of T transistors. Each transistor Q2□, Q2° is connected to the common potential point 00M side and forms a current mirror circuit. The resistor R1o and the transistor Q11'1□ constitute the current control circuit CCV shown in Fig. 1, and the resistor R2゜ and the transistors Q2□, Q
2□ constitutes a current control circuit CC2. In this specific circuit configuration, the stray capacitance ccp1 shown in FIG.
In addition to the transistor Q11.jccp2. Stray capacitance fC8□2.C8□2 exists between the gate of Q1゜ and the input terminal of buffer gate G1, and between the gate 7 of transistor Q21''2□ and the input terminal of gate gate G, respectively. .

This is an example in which the 1-out threshold voltage v (i-0.5 volts), the resistors T Rlo and R2o are each 400 kilohms, and the voltage E is 6.5 volts.

Next, the operation of the circuit shown in FIG. 4 constructed as above will be explained using the waveform diagram shown in FIG. 6.

It is the same as the circuit shown in FIG. 12 in that oscillation is continued by alternately repeating the positive feedback action via the capacitor CM'5c and the negative feedback action via the current control circuits CCI and CC2. Therefore, the oscillation waveforms are as shown in FIGS. 6(a) and 6(b). In this case, the stray capacitance cSl shown in FIG.

, c8□2 is as follows. Figure 6 (c))K
As shown, when the voltage at the output terminal of buffer gate G1 is 10B, transistor Q□1 is turned off and its gate voltage becomes +E, but when the voltage at the output terminal of buffer gate G1 is zero, it becomes +E. Depending on the voltage, citran'''resistance Q ・Resistance R
A current flows into the output end side of the buffer gate G□ via 1o. A current with the same value as this current flows through the transistor Q1□ that constitutes the current mirror circuit, and the buffer gate G
The input end of No. 1 is busy. In this case, transistor Q11
The gate threshold voltage at V. The voltage at the gate of the transistor Q1□ decreases by an amount corresponding to the voltage 1E.

On the other hand, on the transistor 21 side, the operation is opposite to that of Q1□, and its gate voltage changes by T between V and zero. Therefore, the amount of change in the gate voltage of transistors Q1□ and Q21 is V. It is T. Also, buffer gate G
At the input terminal of No. 1, there is a voltage fluctuation via the capacitance CM.

The potential fluctuation e2 at the input end of the buffer gate G1 due to these voltage fluctuations is the sum of the voltage division ratios due to the capacitance cM, the distributed capacitance C32' stray capacitance "Cpl 'CC'2"312"S22," The discharge time t2 is 12'' when the discharge current is 12.
22-02 (C+C82+CCp1+CCp2+C81
2+C822)(5).

Here, if we calculate t2 from equations (4) and (5) with cs12=cs22=ccp for the sake of simplicity, we get t2-possible (C
,E + 2CCpVo, ) (6
)Totoru. Assuming that V = 0.5 volts and E = 6.5 volts, the term including the stray capacitance CCp as the voltage is used as the error component (
3) Compare with Eq. The error term in equation (3) is CCpE =
6.5ccp and the error term in equation (6) is 2CCpv
oT=1xC, and the error is reduced to 1/6.5.

FIG. 7 shows an example in which the current control circuits CCI and CC2 are constructed of bipolar transistors instead of MO3 type FBTs. Transistor Q1'1. Q1'2 constitutes a current mirror circuit, and transistors Q21''22 likewise constitute a current mirror circuit.

FIG. 8 shows a modified embodiment of the circuit shown in FIG.

The output terminal of buffer gate G1 is resistor R31, MO8 type F
It is connected to the input end of the buffer gate G□ via a transistor Q30 ``11''□2 formed of ET.

A connection point between transistors Q3o and Q1□ is connected to a common potential point COM through a resistor R. (3) Furthermore, a resistor R33 and a transistor Q2□ are connected in series between the power supply of voltage +E and the common potential point COM.

A current that is the sum of a fixed value current 1°2 flowing through the resistor R3□ and a current 1° flowing through the resistor R31 which changes depending on the voltage at the output terminal of the buffer gate G1 flows through the transistor Q11.

On the other hand, a constant current 1 flows through the transistor Q21 via the resistance value R33. The same current (Fig. 9 (a)) as the current (1°2+1) flowing through the transistor Q11 flows through the trunk transistor Q1°, and the same current (1°2) as the current 1°□ flowing through the transistor Q21 flows through the transistor Q2□.
FIG. 9 (rJ)) flows. A composite current 1T (m'cl+i.+1.degree.2), which is the sum of these currents, flows to the input end of the buffer gate (FIG. 9(c)). For example, w = 6.5 volts, R33 = 200 (kΩ), R3
Assuming that 1 = 182 (kΩ) and R3□ = 400 (kΩ), 1° = θ ~ 30 (IIA)・t = 30 (
IJA)・1='15 (pA) -cl
c2iT=-15ClJA
') to +15()IA). In other words, in response to the voltage change at the output terminal of buffer gate G1, the composite current IT is -
Varies between 15(1) and +15()IA). In this case, for example, if the mutual conductance of the transistor Q is 10 (mV7), then for the above-mentioned current change of 30 ()IA), 30 (IJA) x 10 (mtj)
A voltage change of =3 (mV) only occurs in the transistor Q□1. Therefore, the influence of the stray capacitances C81□ and C8°2 is negligible. When using the circuit shown in Figure 8, the transistor Q causes these various small voltage fluctuations.
This is because Q1□ and Q2□ are always in a conductive state, and in the circuit shown in FIG. 4, the output terminal of the buffer gate G1 changes during 10E tosero, and accordingly, the gate threshold voltage V.

It is different from the one that involves a change in T (= 0.5 volts).

Note that this is to prevent the resistor R3□'') current from being shunted to the resistor R31 when the output of the transistor Q3o/gate G1 in FIG. 8 is +E.

<Effects of the Invention> As specifically explained above in conjunction with the embodiments, according to the present invention, it is possible to substantially eliminate the influence of stray capacitance caused by a constant value current limiting circuit as in the prior art, and to reduce errors. Since this factor can be eliminated, a highly accurate capacitive displacement converter can be realized.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a waveform diagram showing the output current of the current control circuit in FIG. 1,
Fig. 4 is a circuit diagram that further embodies the circuit in Fig. 1, Fig. 5 is a characteristic diagram showing the characteristics of the current control circuit in Fig. 4, and Fig. 6 is a waveform diagram showing waveforms of various parts in Fig. 4. , FIG. 7 is a circuit diagram showing another embodiment of the current control circuit in FIG. 4, FIG. 8 is a circuit diagram showing another embodiment of the present invention, and FIG. 9 is a circuit diagram showing another embodiment of the current control circuit in FIG. A waveform diagram showing the waveform flowing through each part, Fig. 10 is a sectional view showing an example of a conventional single capacitance type sensor, and Fig. 11 is a waveform diagram showing an example of a conventional single capacitance type sensor.
0 is an equivalent circuit diagram, FIG. 12 is a circuit diagram showing a conventional capacitive displacement converter, and FIG. 13 is a waveform diagram showing waveforms at various parts in FIG. G1...Buffer gate, G2...Inverter, C
C... Constant value current limiting circuit, C31"S□... Distributed capacitance, CCp. CCp□, CCp2.Cs1□, C8゜2... Stray capacitance, CCI, CC2... Current control circuit, CM.・・・
capacitance. Fig. 1 Fig. 2 Fig. 3 (a) CC is sixfold - beak 1 mouth) ccZt7I (L hanawa - Fig. 4 OM Fig. 5 Fig. 4 L lunge Beaked loaf
−：==−′50(
E-Vnr) Figure 7 CDA/I Figure 8 Figure q

Claims (2)

[Claims] (1) A capacitance that changes in response to a physical change to be detected, an amplification means to which the capacitance is connected between its input and output terminals, and a current value that changes depending on the output level of the amplification means. 1. A capacitive displacement converter comprising: current control means whose direction is controlled; and an output current of said current control means is supplied to an input end of said amplification means. (2) The current control means includes a pair of current mirror circuits provided corresponding to the high potential side and the low potential side of the power supply that energizes the amplification means, and output from the output end of the amplification means. The capacitive type according to claim 1, characterized in that a current is supplied to at least one of the current mirror circuits, and a composite current transferred by the current mirror circuit is supplied to an input terminal of the amplification means. Displacement conversion device.