JPS61212060A - Schottky barrier diode - Google Patents
Schottky barrier diodeInfo
- Publication number
- JPS61212060A JPS61212060A JP60052206A JP5220685A JPS61212060A JP S61212060 A JPS61212060 A JP S61212060A JP 60052206 A JP60052206 A JP 60052206A JP 5220685 A JP5220685 A JP 5220685A JP S61212060 A JPS61212060 A JP S61212060A
- Authority
- JP
- Japan
- Prior art keywords
- diode
- layer
- schottky barrier
- epitaxial
- small area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004888 barrier function Effects 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000004065 semiconductor Substances 0.000 claims description 8
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910021339 platinum silicide Inorganic materials 0.000 abstract description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 229910052697 platinum Inorganic materials 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 2
- 238000000034 method Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000012808 vapor phase Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置用ダイオードに関し、特に大規模集
積回路（ＬＳＩ）に適した小面積かつ、大写ｔ’を提供
できるショットキバリアダイオードに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a diode for a semiconductor device, and more particularly to a Schottky barrier diode that has a small area and can provide a large image t' suitable for a large scale integrated circuit (LSI).
特開昭５３−４３４８５号において、第１図に示す回路
構造の高速バイポーラメモリセルが提案されている。こ
のメモリセルは、図示のように負荷抵抗Ｒ＋ 、Ｒｚに
並列にダイオードＤＩ 、 Ｄｔが形成され、かつ該ダ
イオードがキャパシタＣＩ＋Ｃ２の代用をすることを特
徴としている。このような構成によシ、このメモリセル
は次の点が改良されている。すなわち、１）高速のスイ
ッチングが可能で、２）動作余裕度が増大し、３）α線
によるソフトエラーが防止できる点である。JP-A-53-43485 proposes a high-speed bipolar memory cell having the circuit structure shown in FIG. This memory cell is characterized in that diodes DI and Dt are formed in parallel with load resistors R+ and Rz as shown, and these diodes serve as a substitute for capacitor CI+C2. With this configuration, this memory cell is improved in the following points. That is, 1) high-speed switching is possible, 2) operating margin is increased, and 3) soft errors due to alpha rays can be prevented.
なお、これらの３つの利点を生かすためには、キャパシ
タＣｓ、Ｃｍにはそれぞれ約５００ｆＦの静電容量が必
要とされる。従来の半導体装置においては、この静電容
ｔを得るために、上述のごとくキャパシタの代用として
ショットキバリアダイオードの静電容−１１’に見いて
いる。一方、従来の半導体装置におけるショットキバリ
アダイオードとしては主として、白金シリサイド層−シ
リコン界面を用いている。しかし、このようなダイオー
ドによって得られる静電容量は単位面積当シ最大３．４
ｆＦ／μｍ２程度に過ぎないので、上記の必要な静電容
ｉを得るためには該ダイオードの面積は約１５０μｍ”
にもなり、メモリセルの面積の約３０％を占めてしまう
。このことは、バイポーラメモリセルを高集積化するの
に重大な障害となつている。Note that in order to take advantage of these three advantages, each of the capacitors Cs and Cm is required to have a capacitance of approximately 500 fF. In conventional semiconductor devices, in order to obtain this capacitance t, the capacitance -11' of a Schottky barrier diode is used as a substitute for a capacitor as described above. On the other hand, a Schottky barrier diode in a conventional semiconductor device mainly uses a platinum silicide layer-silicon interface. However, the capacitance obtained by such a diode is up to 3.4 per unit area.
Since it is only about fF/μm2, the area of the diode must be about 150 μm in order to obtain the required capacitance i mentioned above.
It also occupies about 30% of the area of the memory cell. This is a serious obstacle to achieving high integration of bipolar memory cells.
本発明は上記従来技術の欠点に鑑みてなされたもので、
その目的は、大きな静電容量を提供できる小面積のダイ
オードを提供することにある。The present invention has been made in view of the above-mentioned drawbacks of the prior art.
The aim is to provide a small area diode that can provide a large capacitance.
上記目的を達成するために本発明は、Ｓｉ基板上に溝を
形成し、線溝の側面および底面にも白金シリサイドを形
成し、ダイオードの実効面積を減することなしに小面積
のショットキバリアダイオードを形成することを％徴と
している。In order to achieve the above object, the present invention forms a groove on a Si substrate, and also forms platinum silicide on the side and bottom surfaces of the line groove, thereby creating a small-area Schottky barrier diode without reducing the effective area of the diode. It is considered as a percent sign to form.
以下、本発明の半導体装置を、高速バイポーラメモリセ
ル形成工程に導入した際の実施例によシ詳細に説明する
。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device of the present invention will be described in detail below using an example in which it is introduced into a high-speed bipolar memory cell forming process.
第２図は、本発明の一実施例のバイポーラメモリセルの
ダイオード部の部分断面図を示す。FIG. 2 shows a partial cross-sectional view of a diode portion of a bipolar memory cell according to an embodiment of the present invention.
図において、１はＰ型Ｓｉ基板、２はダイオードの陰極
となるＮ４″埋込層、３は素子分離絶縁膜、４は適当な
ダイオード特性を得るように不純物拡散されたエピタキ
シャルＳｉ層、５は白金とエピタキシャルＳｉ層４との
反応によって形成された白金シリサイド層、６は気相化
学成長法によって形成されたバリアメタル（例えばＷ）
の層を示し、７も気相化学成長法によって形成したＡｔ
膜である。本実施例において、ダイオードの上部電極す
なわちＷとＡｔの２層膜を気相化学成長法によって形成
したのは、溝の側面にも十分な回シ込みをもつ電極を形
成して、溝の側面にも良好な特性を有するダイオードを
形成するためである。In the figure, 1 is a P-type Si substrate, 2 is an N4'' buried layer that becomes the cathode of the diode, 3 is an element isolation insulating film, 4 is an epitaxial Si layer with impurities diffused to obtain appropriate diode characteristics, and 5 is an A platinum silicide layer formed by a reaction between platinum and an epitaxial Si layer 4, and 6 a barrier metal (for example, W) formed by a vapor phase chemical growth method.
7 is also an At layer formed by vapor phase chemical growth method.
It is a membrane. In this example, the upper electrode of the diode, that is, the two-layer film of W and At, was formed by the vapor phase chemical growth method. This is to form a diode with good characteristics.
上記実施例において、ダイオードは上部電極７（陽極）
と下部′成極２の間に形成される。In the above embodiment, the diode is the upper electrode 7 (anode)
and the lower polarization 2.
第２図からも明らかなように、本発明の概念による溝型
ダイオードは、溝の側面をも良好なダイオードとして利
用できるため、小面積であるにもかかわらず、大きな容
ｔｅ有するダイオードを形成することができる。As is clear from FIG. 2, the trench diode according to the concept of the present invention can also utilize the side surfaces of the trench as a good diode, so it forms a diode with a large capacitance despite its small area. be able to.
なお、本実施例では、ダイオードとして白金シリサイド
層とエピタキシャルＳｉ層との界面を利用したが、その
他のショットキバリアダイオード例えばアルミニウムと
Ｓｉなどの界面を利用すれば、本発明の実施例に示した
構造よりもさらに簡単な構造にて、本発明の概念を実施
することも容易である。In this example, the interface between the platinum silicide layer and the epitaxial Si layer was used as the diode, but if other Schottky barrier diodes, such as the interface between aluminum and Si, are used, the structure shown in the example of the present invention can be obtained. It is also easy to implement the concept of the present invention with an even simpler structure.
上述のように、本発明によって、たとえば従来、平坦な
Ｓｉ基板上に形成されていたため、大きな面積にならざ
るを得なかったショットキバリアダイオードを溝の側面
にも形成することによって、半導体集積回路の著しい高
集積化が可能となった。As described above, the present invention allows Schottky barrier diodes, which were conventionally formed on a flat Si substrate and therefore had to take up a large area, to be formed on the side surfaces of the grooves, thereby making it possible to improve semiconductor integrated circuits. This made it possible to achieve a significantly higher level of integration.
本発明によれば、小面積であるにもかかわらず大きな容
ｔ’を有するダイオードを形成することができるため、
半導体集積回路の高集積化に著しい効果がある。According to the present invention, it is possible to form a diode having a large capacitance t' despite its small area.
This has a significant effect on increasing the degree of integration of semiconductor integrated circuits.
第１図は高速バイポーラメモリセルの等価回路図、第２
図は本発明の一実施例のメモリセルのダイオード部の部
分断面図である。Figure 1 is an equivalent circuit diagram of a high-speed bipolar memory cell, Figure 2 is an equivalent circuit diagram of a high-speed bipolar memory cell.
The figure is a partial cross-sectional view of a diode portion of a memory cell according to an embodiment of the present invention.
Claims (1)
装置において、少なくとも該溝の側面および底面にショ
ットキ接合が形成され、実効的に該ショットキ接合の面
積が増大されていることを特徴とするショットキバリア
ダイオード。1. A semiconductor device in which a groove is formed in one area on a semiconductor substrate, characterized in that a Schottky junction is formed at least on the side and bottom surfaces of the groove, effectively increasing the area of the Schottky junction. Schottky barrier diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60052206A JPS61212060A (en) | 1985-03-18 | 1985-03-18 | Schottky barrier diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60052206A JPS61212060A (en) | 1985-03-18 | 1985-03-18 | Schottky barrier diode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61212060A true JPS61212060A (en) | 1986-09-20 |
Family
ID=12908298
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60052206A Pending JPS61212060A (en) | 1985-03-18 | 1985-03-18 | Schottky barrier diode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61212060A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01192169A (en) * | 1988-01-27 | 1989-08-02 | Nec Corp | Semiconductor integrated circuit device |
| US5759871A (en) * | 1996-07-26 | 1998-06-02 | Advanced Micro Devices, Inc. | Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques |
| JP2010206012A (en) * | 2009-03-04 | 2010-09-16 | Nissan Motor Co Ltd | Semiconductor device |
| CN101901808A (en) * | 2010-06-23 | 2010-12-01 | 苏州硅能半导体科技股份有限公司 | Trench-type Schottky-barrier diode rectifier and preparation method |
-
1985
- 1985-03-18 JP JP60052206A patent/JPS61212060A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01192169A (en) * | 1988-01-27 | 1989-08-02 | Nec Corp | Semiconductor integrated circuit device |
| US5759871A (en) * | 1996-07-26 | 1998-06-02 | Advanced Micro Devices, Inc. | Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques |
| US5913106A (en) * | 1996-07-26 | 1999-06-15 | Advanced Micro Devices, Inc. | Method for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques |
| US6037607A (en) * | 1996-07-26 | 2000-03-14 | Advanced Micro Devices, Inc. | Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques |
| JP2010206012A (en) * | 2009-03-04 | 2010-09-16 | Nissan Motor Co Ltd | Semiconductor device |
| CN101901808A (en) * | 2010-06-23 | 2010-12-01 | 苏州硅能半导体科技股份有限公司 | Trench-type Schottky-barrier diode rectifier and preparation method |
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