JPS61211899A - Dynamic type ram - Google Patents

Abstract

PURPOSE:To duplicate the floating capacity value of a connected data lines and enlarge a memory capacity value of a connected data lines and enlarge a memory capacity and stabilize an operation by shortcircuiting between the data lines to which a dummy cell to be selected out is connected of the data lines corresponding to a pair of memory arrays. CONSTITUTION:A dynamic type RAM has four memory arrays MIL, MIR, M2L and M2R. The memory arrays MIL to M2R are constituted by a folding back bit line system. Respective data lines of the pair of memory arrays have substantially equal data line capacity. Between the pair of memory arrays MIL and MIR, a sense amplifier SA1 and SA 2 are controlled by timing signal generated from a timing generating circuit.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a Dairi-mink type RAM.
For example, the present invention relates to a technique effective for a dynamic RAM in which a base voltage for reading is generated by a Fleurize charge cell.

[Background technology]

I-hit memory cells in a dynamic RAM include, for example, an information storage capacitor and an insulated gate-type battery-effect I transistor (hereinafter referred to as MOS transistor) for selecting an array.
1 (referred to as ``1''), which has logic ``1''.

"0" information is stored in the form of whether or not there is a charge on the capacitor.Reading the information is done using the M for address selection.
Each time the OS is turned on, the information storage capacitor is connected to the data line or the data line, and the potential of the data line is accumulated in the capacitor t+, 1.: Charge. This is done by sensing what kind of change occurs in ′ζ depending on the amount.

In recent years, highly integrated eccentric capacity has been required for RA.
In M, each memory cell is sized small;
Also, a large number of memory cells are coupled to each data line. Correspondingly, the relationship between the capacitance Cs of the gear batter and the f$ free capacitance (data line capacitance) Co of the data line, J, that is, the ratio Cs/CO, becomes a very small value, and the data line from the memory cell to In other words, the potential change applied to the arc line in response to the charge U stored in the data signal, ``2ki 4-yapanta Cs,'' has a very small value.

In order to enable the detection of minute data signals such as
ef 1), Magazine IEEE JA'SONAL OFF SORINO F-STATE CIRCUIT-1-(I
E E E JORNAshi OF 5O
LI+)-5'rATE CIRCUITS)
VoI 5C-77, Na5 October 1972, No. 33
Pages 6-340 (Ref2), ISSC 8
4. Tigest off technical papers cts
scc84, DIGIST OF TEC) INICA
L PAPliR3) magazine, pages 276-277 (R,e
A differential sensing technique or a balanced sensing technique as shown in f 3 ) is used.

According to these techniques, two data lines or hint lines or digit lines that correspond to each other are paired;
A sense amplifier that substantially performs a differential amplification operation or a balanced amplification operation is coupled to the paired data lines (hereinafter also referred to as complementary data lines).

A data signal from a memory cell is applied to one of the pair of data lines, and a reference potential having a level intermediate between the high level and the low level of the data signal is applied to the other. The reference potential is determined by a method (Ref
l) A method of using a dummy cell (hereinafter referred to as a full-size dummy cell) having a capacitor substantially equal to the capacitor of the memory cell and having the capacitor charged in advance with half the charge of the memory cell (Ref 2), each data It is formed by a precharge method (hereinafter referred to as a half precharge method or dummy cellless method) (Ref 3) using a short circuit between lines. A minute relative level difference given between a pair of data lines based on such a reference potential is amplified by operating a sense amplifier.

The reference potential is
required to be brought to the desired level.

Here, when using a half-size dummy cell, the margin of the sensing operation is greatly influenced by the relative accuracy of the dummy cell and the capacitor of the memory cell. In general, a dummy cell is different from the memory cell except that the capacitance value of the dummy cell is half that of the memory cell capacitor in order to increase the relative accuracy between the capacitor in the dummy cell and the capacitor in the memory cell. Same manufacturing conditions,
made with the same design constants.

However, for example, in the case of dynamo-type RAM with a large storage capacity such as LM (mega) bit, the size of the information storage capacitor is further miniaturized, so 1/2 Creating dummy cells of size is very much a factor. That is, it is difficult to form a capacitor with a capacitance value that is half that of a memory cell capacitor due to limits and variations in the processing accuracy of device patterns.

Therefore, when using half-size dummy cells, it is difficult to obtain a reference potential at a desired level.

On the other hand, in the case of the method using full-size dummy cells and in the case of the half precharge method, a comparatively good level of reference can be obtained.

In other words, when full-size dummy cells are used, the capacitors of the dummy cell and memory cell can be made to have the same size, so that the relative precision of these capacitors can be made sufficiently high regardless of processing precision and variations. In the case of the dummy cell-less method, there is no dummy cell, so the relative accuracy of the capacitor does not directly matter.

However, the present inventors have found that even in a dynamic RAM of a type in which the relative accuracy of dummy cells is not a problem, such as a full-size dummy cell type, the operating margin is reduced accordingly. The inventors of the present invention have discovered that the decrease in the operating margin is caused by an undesirable change in the data line potential due to the α rays.

[Purpose of the invention]

One object of the present invention is to provide a dynamic RAM with a large storage capacity and stable operation.

Another object of the present invention is to provide a dynamic RAM whose operating margin is less reduced by α rays.

Another object of the present invention is to provide a dynamic RAM suitable for the shared sense method.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical embodiments disclosed in this application is as follows. That is,
A switch MOSFET is installed between the data lines so that the stray capacitance of the data line to which a reference potential is applied among the plurality of data lines of the memory array is twice that of the data line to which a data signal is applied. ET will be provided.

This makes it possible to form a reference potential that is less susceptible to alpha rays.

〔Example〕

FIG. 1 shows a dynamic RA according to an embodiment of the present invention.
A block diagram of M is shown. Each of the main circuit blocks in the figure is drawn in the same way in the actual geometric arrangement, and is made of a single piece of single-crystal silicon due to semiconductor integrated circuit technology, although this is not particularly limited. It is formed on a semiconductor substrate.

Although not particularly limited, this embodiment is directed to a shared sense type dynamic RAM.

As will become clear from the description below, the operations of the various circuits constituting the RAM are controlled by various timing signals generated from the timing generation circuit TG. However, in FIG. 1, signal lines that should be provided between the timing generation circuit TG and various circuits are omitted to prevent the drawing from becoming complicated.

The dynamic RAM of this embodiment has four memory arrays MIL, MIR, M2L, and M2R, although this is not particularly limited. Each of memory arrays MIL to M2R is configured with a folded bit line (data line) system, as will become clear from the explanation based on FIGS. 2A and 2B later. Therefore, each memory array includes a plurality of data lines to be paired, that is, a plurality of complementary data lines, and a plurality of dynamic memory cells whose respective data input/output terminals are coupled to the corresponding data lines. , and a plurality of sums to which selection terminals of dynamic memory cells are respectively connected. The data line is
Although not shown in FIG. 1, it extends in the lateral direction of the figure.

The word line extends in the vertical direction of the figure.

Memory arrays MIL and MIR each other, and M2L and M2
The R's are paired with each other.

According to this embodiment, the data lines of each pair of memory arrays are made to have data line capacitances that are substantially equal to each other. In order to make the data line capacitances substantially equal to each other, memory arrays MIL to MIR are configured to have the same configuration, that is, to have the same number of data lines, memory cells, and word lines, although this is not particularly limited. .

A sense amplifier SAI is provided between the pair of memory arrays MIL and MIR, which is selectively used by these memory arrays. A switch circuit 5WIL is provided between the memory array MIL and the sense amplifier SAI for selectively coupling them to each other. A switch circuit 5WIR for selectively coupling is provided.

A similar sense amplifier S A 2 and a switch circuit 5W21 are also provided between the paired memory arrays M2L and M2R.
and 5W2R are provided.

The operation of each of the switch circuits 5WIL to S W 2 R is controlled by a timing signal output from the timing generation circuit TG.

Basically, one of the two switch circuits 5WII and 5WIR corresponding to one sense amplifier, eg, SAI, is turned off at the start of memory access. As a result, a pair of memory arrays MIL and M
One of the IRs is disconnected from the sense amplifier SAI, and the other remains coupled to the sense amplifier SAI. In other words, each pair of data lines in one memory array is disconnected from sense amplifier SAI, and each pair of data lines in the other memory array is disconnected from sense amplifier SA1.
It remains connected to I. However, according to this embodiment, as will be explained in detail later with reference to FIG. 3, the timing at which one of the paired data lines in one memory array is disconnected from the sense amplifier SA1 is as follows.
made to be different from that of the other.

The operations of the sense amplifiers SAI and SA2 are controlled by timing signals output from the timing generation circuit TG. Note that the sense amplifiers SAI and SA2 as circuit blocks in FIG. 1 include a precharge circuit, a full-size dummy cell, an active restore circuit, etc., which will be explained in detail later in FIGS. 2A and 2B. I want to be understood as being there.

The illustrated RAM has an address circuit for selecting a desired memory cell from among a plurality of memory cells in each memory array and a desired dummy cell from among a plurality of dummy cells. The address circuit includes an address buffer ADB,
Row address decoders R-DCRI L-2R, column address decoders C-DCR1-2. It is composed of column switch circuits CWIL to 2R, etc.

Each circuit that makes up the address circuit operates as follows.
It is controlled by a timing signal generated from a timing generation circuit TG.

RAM to which the input terminal of address buffer ADB is connected
External row address signals and column address signals are supplied in a time-division manner to external terminals of , according to an address multiplex method.

Address buffer ADB captures an external row address signal in response to a timing signal for address signal capture control being generated from timing generation circuit TG in synchronization with the generation of row address strobe signal RAS. As a result, row address decoder R-D
A row-related internal complementary address signal to be supplied to CRI L to R-DCR2H is output from address buffer ADB. When a similar timing signal is generated in synchronization with the generation of the column address strobe signal CAS, the address buffer ADB also takes in an external column address signal in response to the column address strobe signal CAS, and receives the column address signal for the column to be supplied to the column address decoder C-DCR1. Outputs the internal complementary address signal of the system.

Row address decoder R-DCRI L or R-DC
R2R is memory array MIL to M in FIG.
2R, each output terminal being coupled to the word line of the corresponding memory array. These row address decoders R-DCRI L to R-DCR2
Each operation of R is controlled by a word line selection timing signal generated from a timing generation circuit TG, and outputs a word line selection signal and a dummy word line selection signal in synchronization with the timing signal.

Therefore, each memory array MIL, MIR, M2L and M
The 2R word line is a row address decoder R-DCRI.
L, R-DCRIR, R-DCR2L and R-DCR2
The word line selection signals formed by R are respectively supplied to select the word line selection signals. In this case, by appropriately configuring the row address decoders R-DCRIL and 1-DCRIR, one of the memory arrays MIL of the paired memory arrays MILlIl:MIR
When a word line of the memory array MIR is selected, all the word lines of the memory array MIR are made unselected, and conversely, the word lines of the memory array MIR are
When one word line of IR is selected, all word lines of memory array MAL are rendered unselected. Similarly, row address decoders R-DCR2L and R-D CR2R
The word lines of the other paired memory arrays M2L and M2R are also alternatively selected depending on the appropriate configuration.

The operation of the column address decoder C-DCR1 is controlled by the data line selection timing signal or column selection timing signal output from the timing generation circuit TG, and outputs the data line selection signal or column selection signal in synchronization with the timing signal. do. Although not particularly limited, the column address decoder C-DCR1 is arranged on the right side of the memory array as shown. An output line (not shown) of column address decoder C-DCRI, that is, a data line selection line, is extended over the memory array and coupled to column switch circuits CWIL and CWIR. The details of the column address decoder C-DCR1 are not shown because they are not directly related to the present invention, but
It consists of a plurality of unit circuits that respectively provide outputs to each data line selection line.

The column switch circuits CWIL and CW I R are provided between the common data line provided corresponding to the memory arrays MIL and MIR and the input/output terminal of the sense amplifier SAI, and also provided corresponding to the memory arrays M2L and M2R. A data line selection signal formed by a column address decoder C-1) CRI is provided between the common data line and the input/output terminal of the sense amplifier SA2, respectively, and is commonly supplied thereto. That is, the column switch circuits CWIL and CWIR receive the selection signal formed by the column address decoder C-DCRI.
The input/output terminals of the sense amplifiers SAI and SA2 are respectively coupled to a common data line (not shown) running in the vertical direction.

Here, the unit circuits constituting the column address decoder C-DCR1 have a relatively large pitch when they are formed on a semiconductor substrate according to semiconductor layered circuit technology. According to this embodiment, each of the column switch circuits CWIL, CWIR can be realized as a unit circuit constituting the column address decoder circuit C-DCR1, although not particularly limited, as will become clear later in FIG. 2B. Considering the pinch, two pairs of complementary data lines adjacent to each other are
They are configured to be coupled simultaneously to a pair of complementary common data lines, respectively. As a result, the column address decoder C
- The pitch of each unit circuit of DCR1 is made to match the pitch of a total of four data lines. In this configuration, a total of 4-bit signals, i.e., memory array M
2-bit signal of IL or MIR and 2 of M2L or M2R
Bit signals are simultaneously selected by a column selection circuit including a column address decoder C-DCR1 and column switch circuits CWIL and CWIR.

Although not particularly limited, according to this embodiment, in order to select a 1-bit signal from a total of 4-bit signals, two pairs of common data lines corresponding to memory arrays MIL and MIR and memory arrays M2L and M2R are connected. Second column switch circuits CW2L and CW2R are provided between the two pairs of common data lines corresponding to the data in and the output terminal of the data input buffer sofa DIB and the input terminal of the data output sofa DOB. These second column switch circuits CW
The operations of 2L and CW2R are controlled by selection signals formed by the second column address decoder circuit DCR2. Note that if the configuration is such that reading and writing from the memory array is performed in units of 4 bits as described above, it is not possible to change the function to access data in units of 4 bits or input/output data in nibble mode 1. This can be achieved relatively easily, mainly by changing the configurations of the second column switch circuit and the input/output circuit section.

The operation of the data cover sofa DIB is controlled by the timing signal generated from the timing start circuit '1''G, and forms a write signal corresponding to the signature signal supplied from the external terminal Din. It is connected to the second column switch circuit CW 2 L or CW 2
Supply to R. The data driver sofa DIB exhibits high power 1-beadance characteristics when it is placed in a non-operating state.

Similarly, the operation of the data output buffer OB is controlled by the timing signal generated from the timing generation circuit '1'G,
I! 8CW21. , or receive the read signal output through CW2R, amplify it, and send it to the external terminal Dout.
Send to.

A timing circuit TG for controlling information read/write operations receives a row I address strobe signal RAS, a column address strobe signal CAS, and a write enable signal WE supplied from external terminals, thereby generating various timing signals. Form.

According to this embodiment, as will become clear from the detailed description using FIGS. 2A, 2B to 4 later,
■In response to the row address signal), the switch circuit 5WI
4. It is necessary to change the operation timing of L to 5WIR. Therefore, the timing generation circuit TG is
A portion of the row-related internal complementary address signal output from the address buffer ADH is received.

The operation outline of the switch circuits 5WIL and SWIR is as follows. Note that switch circuits 5W2L and 5W corresponding to memory arrays M2L and M2R
The operation of 2R is performed by switch circuits 5WIL and SWI
is made substantially the same as R. In the following description, for convenience, one of the complementary data lines of the memory array MIL will be referred to as a first data line, and the remaining one will be referred to as a second data line.

Also, of each complementary data line of the memory array MIR,
The data line that should correspond to the first data line will be referred to as a third data line, and the remaining data lines will be referred to as fourth data lines.

The switch circuits SWIL and 5WIR are configured such that before the start of accessing the RAM, in other words, when the lower IS rest strobe signal RAS (hereinafter referred to as the ]-JAS signal) is set to the H/F level, Both are turned on. Therefore, the first data line and the third data line are connected to each other, and the second data line and the fourth data line are connected to each other by the switch circuits SWI L,
Sense amplifier SAI input/output terminals and switch circuit 5W
The data lines are connected to each other through iR. At this time, each data line is set to a precharge level.

Access to the RAM is started by lowering the RAS signal to a low level. Here, if the row-related address signal is brought into a state that selects one word line in the pair of memory arrays M11- and MIR, for example, one word line in MIL, then the memory array MI
The switch circuit 5WIL corresponding to L is maintained in the on state. In this case, the operation of the switch circuit 5WIR is as follows:
It is done as follows.

In other words, the row-related address signal is
If the memory cell coupled to the first data line of the plurality of memory cells in L is specified, the switch circuit 5WIR first selects the word line of the memory array MIL by 3rd memory array MIR
The fourth data line of the memory array MIR is controlled to be disconnected from the input/output terminal of the sense amplifier SAI, and then, after word line selection is started and the operation of the sense amplifier SAI is started, the fourth data line of the memory array MIR is switched off. The switch is controlled to disconnect the data line from the input/output terminal of the sense amplifier SAI. As a result, the third data line in the memory array MIR is disconnected from the first data line before memory cell selection is started, and the fourth data line is disconnected from the first data line before memory cell selection is started and Amplifier S
After the operation of A1 is started, it is disconnected from the second data line.

Of the plurality of full-sized dummy cells in the sense amplifier SAI, the dummy cell connected to the second data line U= is selected ′ζ W+ in synchronization with the start of word line selection.
, when full size tummy cell is selected,
The second take line is connected to the fourth data line when it is coupled to the fourth data line.
Therefore, the reference potential applied to the second data line by the full-size tummy cell is half the value of the data line capacitance. This is equivalent to the reference potential applied to the data line by the size dummy cell.

When a memory cell coupled to the second L7 fourth data line is selected, the same operation as described above is performed.

As is clear from the above, the switch circuit SW 1L,
Each of the 5WIRs requires two types of timing signals. Timing signals for these switch circuits can be obtained by the following configuration.

That is, in each memory array, a plurality of memory cells and word lines are arranged with regularity. Further, the row address decoder is usually configured to regularly decode the row address signal. That is, for example, a plurality of memory cells coupled to a first data line are respectively coupled to regularly spaced 11116th word lines, and similarly, a plurality of memory cells coupled to a second data line are each coupled to a regular discrete order of word lines. Each word line is assigned a rank corresponding to the rank determined by the combination of row address signals.

Therefore, whether one of the plurality of memory cells connected to one data line can be selected or not depends on one or two bits of the row address signal, for example, the least significant bit or the least significant bit and the upper bit. Determined by the focus. Hereinafter, such an I hint or 2-bit address signal will be referred to as a tummy address signal.

Which one of the -41 memory arrays MIL and MIR is selected is determined by the level of one hint of the row address signal, for example, the most significant one. In this case, such an address signal of lbyy+ is called an array selection address signal.

Therefore, the timing signals for switch circuits 5WIL and 5WIR are row address I-lobe signals RA
It can be generated by a logic circuit (not shown) that receives several delay signals (timing signals) formed based on S, the dummy address signal and the array selection address signal. However, since the detailed internal configuration of the circuit that forms these timing signals is not directly related to the present invention, a description thereof will be omitted. 'The dummy word line selection signal to be supplied to the dummy word line coupled to the tummy cell can be formed based on the dummy address signal and the word line selection timing signal.

According to this embodiment, the data signal level applied to the first data line by the selected memory cell is such that the first data line is previously separated from the third data line.
Becomes relatively large. The reference potential applied to the second data line becomes accurate through the use of full-size tummy cells. Undesired level changes in the second data line due to alpha radiation etc. are sufficiently reduced since the second data line has substantially twice the data line capacity. As a result, a good read operation is possible.

Figures 2A and 2)3 show the memory array/fMI
A circuit diagram of a specific embodiment of L, MIR, and sense amplifier SAI is shown.

Half of the embodiment circuit shown in the same figure is N-channel MO.

The memory array M 1 f has a plurality of complementary data lines DL.
OL, DLOL or DL 3 L, DL 31-
2. It consists of a plurality of saw 1ζ lines WLO, Wl, 2 and a plurality of Guinamick type memory cells. The memory array MIL is
As mentioned above, the folded histo I-line system is used.

Therefore, a memory cell is placed at one of the two intersections formed by one complementary data line and one word line.

The memory array IMi is a memory 7-ray M I L
The same #f configuration is used.

As shown in the figure, the memory cell MC of l-p1- has an information storage capacitor C5 and an address iM selection MOS.
F E i' (,1m, logical "1"',
An IN signal of "0" is stored in the form of whether the capacitor C8 has a charge a or no charge.

To read information, 1ψOS FET Q rn is turned on and capacitor 05 is coupled to one of the complementary data lines, and the ? This is done by sensing what changes in ζ occur in response to the 'I'Ii load stored in the capacitor C8.

Although the memory cells 81C in each of the memory 7 rays M11- and MIH are formed small as described above, many memory cells are coupled to complementary data lines arranged in parallel. Therefore, capacitor C3 and
The ratio of the data line DL to the stray capacitance Co (not shown) is amorphous and has a small value. Therefore, the change in the potential of the data line DL due to the amount of charge accumulated in the capacitor Cs becomes a very small signal.

A dummy cell DC is provided as a circuit that forms a reference potential for the sensing operation of the sense amplifier SAI that detects such a minute signal.

This dummy cell DC is composed of a switch MO3FETQd and a capacitor Cd, which are manufactured under the same manufacturing conditions and the same design constants as the memory cell MC.

The ground potential of the circuit is stored in the capacitor Cd of this dummy cell DC by the reset transistor 40SFETQd' during standby.

Hy/samp SAI is composed of a plurality of unit circuits each composed of amplifying MO5FETs QI and Q2 in a launch configuration. This sense amplifier SAI is
A timing signal (sense amplifier control signal) φpal detects the difference in minute potential changes applied to each complementary data line during addressing.

The sensing period is expanded to be determined by φpa2 (the operation will be described later). One unit circuit of sense amplifier SAI is
As shown in the figure, its input/output terminals are memory array M I
L, a pair of parallelly arranged complementary data lines D L
OL, 111. , OL +, , : respectively switch MO3FEIQ3. Q4 and a pair of complementary data lines 1-th, OR, I)LOR arranged in parallel on the memory array MIR side, respectively.
3FFCTQ19. They are coupled via Q20. As is clear from the above, the data line 1) L (l
L to I-) 1. , OR are made equal to each other in order to increase detection accuracy. A pair of input/output capacitors of the unit circuit of sense amplifier SAI have one tummy cell DC in each.
are combined.

In the above addressing, when the memory cell MC coupled to one of the pair of complementary data lines of the memory array MIL or MIR is selected, one data line of the pair of input/output nodes of the unit circuit of the sense amplifier SAI is selected. A pair of dummy word lines D are connected so that a dummy cell DC with a switch MO5FET is selected.
One of WL and DWL is selected.

The unit circuit of the sense amplifier SAI is composed of a pair of cross-connected MO3FETs Q1 and Q2 as described above, and their positive feedback action differentially amplifies minute signals appearing between complementary data lines. do. This positive feedback operation is performed by the MO3FETQ2 by the timing signal φpal.
7 is turned on. This MO5FE
TQ27 is adapted to exhibit a relatively small conductance when it is made conductive. When the operation of the sense amplifier SAI is started by the timing signal φpal, the potential difference previously applied between the complementary data lines is amplified by addressing. That is,
The higher data line potential is lowered at a slower rate, and the lower one is lowered at a faster rate. Then, M
OS FE'rQ2B is rendered conductive. MOS
I-"E TQ28 is made to have a relatively large conductance when it is conducting.
OS Fl-.

'I゛Q211(/,l) With the start of conduction, the lower data line voltage v is lowered at the speed zU.In this way, the sense amplifier SAI operates in two stages. This prevents the above-mentioned high potential from dropping significantly.In this way, the lower potential becomes cross-coupled MOS
When the voltage drops below the threshold voltage of F' ET, the positive feedback operation ends, and the drop of the higher potential is equal to the power supply voltage Vc.
c and stays at a potential lower than the above threshold voltage, and the low force potential is grounded IJ1 (O
V).

In each memory array, each arc line and each source
1. A non-negligible coupling capacitance is formed between the line and the line. As a result, the level of one line is changed, and undesirable potential fluctuations, which can be considered as essentially random, are applied to each data line.

However, in a folded bit line memory array, each word line WL crosses both complementary data lines. Therefore, the noise applied to the complementary data gauze in response to a change in the level of the word line WI is considered to be common mode noise.

The differential sense amplifier SAI has a substantially 7:- sensitivity to such common mole noise.

During the above-mentioned addressing, the stored information in the memory cell MC, which is once about to be destroyed, is recovered by taking the high level or low level potential obtained by this sensing operation. However, as mentioned above, if the high level drops more than a certain level with respect to the power supply voltage Vcc, U7, it will become a logic "0" point and become old as the reading and rewriting are repeated. malfunction occurs. Therefore, an active restore circuit AR is provided to prevent this malfunction. This active restore circuit iAR has the function of selectively boosting only high level signals to the potential of power supply voltage Vcc without having any effect on low level signals.

The active restore circuit AR is a unit circuit [J A R
It consists of O to U A R3. Unit circuit, e.g. UA
RO is connected to each data line DL as shown in FIG.
O, 1) MO3FET Q100. ulol, data line L) LO
and Boo 1 of MOSFET QI 00, and between data line DLO and MO3FET'QIOI, respectively.
Transmission boolean installed GJ 1M05FETQl 02. Ql
03, and bootstrap bolts CBI and CB2. Boots 1-wrap capacitances CBI and CB2 are:
It consists of an MO3 capacitor and essentially operates as a variable capacitance element. Transmission boo 1~10SFE'rQ102 and QIO
3 is made conductive by the tie signal φarO after the amplification operation of the sense amplifier SAI is executed until before the timing signal φarl for bootstrap shipping is generated.The timing signal φarl is set to a low level in advance. and then raised to a high level.

Precharge circuit PC is composed of unit circuits each coupled to each input/output node of sense amplifier SAI. The unit circuits constituting the precharge circuit are not particularly limited, but as shown in FIG. Consists of QPl and QP2.

The timing signal φpC for controlling the conduction of the precharge MO5FETs QP1 and QP2 is set to a high level during the non-access period of the RAM, that is, when the RAS signal is set to a high level. As a result, each complementary data line is precharged to a high level close to the level of power supply voltage Vcc. The precharge timing signal φpc is set to a low level in response to the start of RAM access. Note that the unit circuit includes an equalization MO that shorts complementary data lines together in response to a precharge timing signal φpc.
It may also include a 3FET.

In the same figure, one of the elements constituting the sense amplifier SAI
1st place circuit human output note, column switch circuit CWj
MO5I;"ETQI 9° is connected to the common complementary data line pair CDI, τ lower 1 through Q20, and the human output nodes of other unit circuits adjacent to this are
Common complementary data line CI via Q21.Q22
)2. Connected to CD2. Each of the other unit circuits is a similar MO3FE'T'Q23. (Go24 and Q25.
Q26 to each common complementary data line pair CDI,
CI)l and CL)2, connected to CI)2.

In this way, two sets of common complementary data lines CDI, CDI and CI)2. By providing CI)2, the gate 1- of the column switches MO3FETQ19 to Q22 is made common. This common gate is supplied with a data line selection signal Y1 formed by a unit circuit forming the column address decoder C-1'). As a result, as mentioned above, it is possible to lay out the unit circuit constituting the column address decoder C-DCR+ in the pinch of the data lines consisting of a total of four lines, and by aligning the pinches of both, it is possible to lay out the unit circuit that constitutes the column address decoder C-DCR+. You can make unnecessary space look good.

The switch circuit 5WIL, as shown in FIG. 2A,
Each stage of the memory array MIL arranged on the left side of the figure
It consists of switches MOSFIZ-1-03 to 1,110 provided between the input/output nodes of the sense amplifier SA1 and the input/output nodes of the sense amplifier SA1. MOS de ET Q3 to QI 0 (7), -
Force data HM I) l, I) L, D L +-
1 to 1) L J MOS installed on the L side
Cases of FET Q3, Q5, Q7 and Q9.
tLI is supplied, and the other data lines DI-OL, D
L ] Lr (Ishi I) L MO5l"1ffl provided on the 31- side TQ4., Q6.QB and Ql, 0
The game 1- is supplied with a common 4-channel timing signal SHL2 (Jj).

As shown in FIG. 2B, the switch circuit 5WIR connects the memory array M, 11<
No data ((11:, 11-OR Ishi I) 7.
A switch MO3FET is provided between each of the 3H°)L and a pair of input/output ports of the sense amplifier SAI.
It consists of Q11 and -Ql8. MO5FETQI 1-Q
MO5FIETQI numbered on the power data line DI, OR, DLIR or DLJR side of l8
I.

Ql3. Case of Ql5 and Ql7 (- is common to each other 1
1', and the timing signal SHR1 is supplied to the MO3FETQI provided on the side.2. Ql 4. Ql6
and Q1 of Ql8 are shared with each other and supplied with timing signal @SHR2. Such a switch M O
S FE 'FQ 3~Q, IO and Qll~Q1
The timing signal S1-1 is supplied to the gate of
By combining 1, 1, 5HL2 and 5HR1, 5HR2, a reference voltage V ref necessary for amplifying the read signal from the memory array selected as described below is formed.

FIG. 4 shows a timing diagram for explaining an example of the operation of the seven readout pairs of the circuit of the above embodiment.

The column address I/lobe signal RAS and the column address strobe signal CAS are shown in FIG. 4A and H, respectively.
In the standby state where the timing signals 5HLI, 5HL2 and 5HRI, 5HR2 are set to high level as shown in FIG. 4, all are set to high level as shown in FIGS. 4E and 4F. As a result, all of the switches MO3FETQ3 to Q18 are turned on.

During this time, all data lines in each memory array are set to the power supply voltage Vcc by the precharge circuit PC.

It is precharged to a high level like that. In this standby state, a word line selection timing signal (not shown) is maintained at a low rising level, and each word line of each memory array is maintained at a low non-selection level. The capacitor in each dummy cell is MO3F
Since ETQd is turned on by the timing signal ψd, it is maintained in a discharged state, that is, a recent state.

When the row address strobe signal RAS falls to the low level as shown in FIG. 4A, the RA
M's access is started. In synchronization with the start of RAM access, the precharge timing signal φpc is set to low level, and the precharge circuit PC is rendered inactive.

The 71'' address software ADB in FIG. 1 takes in an address signal supplied from an external terminal as a row address signal X1 in response to a timing signal generated from a timing ordering circuit 1''G. During the standby period of the RAM, a word line selection timing signal (not shown), which has been set to low level or low level in advance, is applied to the address buffer yA.
Set to high level after DB operation. The row address decoders R-1)CRIL to R-DCR2R are each operated when the word line selection timing signal is set to high level, and decode the row address signal X1. Due to the dirt, as shown in Figure 4C, 1
Selection signals for a real word line and a corresponding dummy word line are formed.

In this selection operation, for example, the left memory array MI
L data lines DLOL, DLIL, DL2L, etc. (hereinafter referred to as
It is called the upper data line. In addition, data lines DLOL, DL
When a memory cell MC coupled to a data line (such as IL is referred to as a lower data line) is selected, a switch circuit 5 between the memory array MIL and the sense amplifier SAI is selected.
Timing signals SHL I and 5HL2 for controlling WIL are maintained at a high level as shown in FIG. 4. At this time, before the word line and the dummy word line DWL are brought to a high level, the timing signal SHR1 is brought to a low level as shown in FIG. 4F. As a result, the right memory array M
One of the complementary data lines in IR, DLOR and DLIR
or DL3R1, that is, a switch MO5FETQI provided between the upper data line and each input/output node of the sense amplifier SAI.1. Ql 3', Ql 5 and Q
l7 etc. are turned off. In this way, one word line WL of the left memory array MIL and the dummy word line D
When WL is set to a high selection level, each data line to which a memory cell to be selected falling in the left memory array MIL is coupled is connected to the memory array MIH before selection of the memory cell starts. It is disconnected from the corresponding data line. In other words, the data line capacitance of each data line to which a memory cell to be selected is coupled is substantially reduced. As a result, a potential change, that is, a data signal, applied to each data line by each selected memory cell MC is brought to a relatively large level. On the other hand, the remaining data lines (lower data lines) among the complementary data lines in the memory array MIL are connected to the switches MO5FET4. Since Q12 is turned on, it remains coupled to the corresponding data line of the right memory array MIR. As a result, the data line stray capacitance for the dummy cell DC to be selected is set to a value that is substantially equal to the sum of the respective stray capacitances existing in the data lines of the left and right memory arrays MIL and MIR, that is, Co + C.

The capacitance value is approximately doubled, such as (2Co). Therefore, even if the capacitance values of capacitors Cs and Cd are equal, the ratio of the stray capacitances that are charge-coupled is 172, so a reference voltage V ref is formed that is halfway between the read high level and low level. .

The fact that the reference potential Vref is obtained in this way means that the ratio of the capacitance of the full-size dummy cell to the sum of the data line capacitances of the two data lines is the ratio of the capacitance value of the stray capacitance of the data line and the capacitor Cd on the half-size dummy cell side. This can be easily understood from the fact that the capacitance value and ratio are equal.

As shown in Figure 4, the timing signal φpal is set to high level after the word line and dummy word line are set to the selection level. As a result, the sense amplifier S
Amplification operations of AI and SA2 are started. The level difference given between the capacitances of each complementary data line of memory array MIL is amplified by sense amplifier SAI as shown in FIG. 4G.

Although not particularly limited, the timing signal SHR2 may be the fourth
As shown in FIG. F, when the timing signal φpal is set to high level, it is set to low level synchronously. As a result, the switch MQ connects the data line of the unselected memory array M I H to the sense amplifier SAI.
SFETQ12. Q14, Q10, QlB, etc. are turned off.

As a result, in the amplification operation of the sense amplifier SAI, the load capacitances coupled to each pair of input/output nodes of each unit circuit of the sense amplifier SAI are balanced, and when reading a high-level data signal, the reference voltage Vref can be pulled to a low level quickly, so the positive feedback amplification operation as described above can be performed at high speed.

When reading the memory cells coupled to the lower data line of the left memory array MIL, the timing signal 5H
R2 is brought to low level first, then sense amplifier SA
The timing signal SHR1 is synchronized with the operation timing of I.
is set to low level. Also, the memory array MI on the right
When R is selected and data is read from the memory array MIR, timing signals 5HRI, S
HR2 remains at high level, timing signal 5) (
L1 and 5) IL2 are respectively brought to the low level with a time difference according to their selection states, as described above. This means that the pair of memory arrays M2 located on the right side of FIG.
The same applies to the selection operation of L and M2R.

Next, the column address strobe signal CAS is
When the selection level is set to low level as shown in
The timing generation circuit TG first uses the address buffer AD.
The timing signal for B is sent to Q. by this,
Address buffer ADH takes in the address signal supplied from the external terminal as column address signal Y1,
An internal complementary address signal corresponding to the address signal is output. Next, a data line selection timing signal (not shown) is output from the timing generation circuit TO. Column address decoders C-DCR1 and DCR2 are operated by a data line selection timing signal and form a data line selection signal by decoding an internal complementary address signal. A total of four pairs of complementary data lines are selected from memory arrays MIL to M2R by a data line selection signal output from column address decoder C-DCRI,
Each is connected to a common complementary data line with a voltage < Y11. Furthermore, one pair of common complementary data lines is selected from the four pairs of common complementary data lines by a data line selection signal output from column address decoder C-DCR2.

If the line enable signal WE is set to a high read level as shown in FIG. After the signal is output from the timing generation circuit 1'G. As a result, the signal on the common complementary data line selected based on the output of the decoder C-1) CR2 is amplified and sent to the external terminal Dout.

When the write I-enable signal WE is set to a low write level, the data input circuit D I
A timing signal for operating B is generated from a timing generation circuit TG. In this case, the write data signal of the external terminal Din is transmitted to the data input circuit DIB and the column switch circuits CW2L, CW2RSCWIL, CWI.
R is supplied to the complementary data line of one of the four memory arrays via any one of switch circuits 5WIL to 5W2R.

With the above configuration, a so-called full-size cell can be used as a dummy cell. In the case of this embodiment, the full-sized dummy cell does not store the reference voltage itself, which is susceptible to fluctuations in the power supply voltage, such as a voltage formed by a voltage divider circuit, but stores the circuit's ground potential. Stored. Therefore,
A stable read reference voltage can be formed even when the power supply voltage fluctuates. Further, since a full-sized dummy cell can be used, a highly accurate reference voltage can be formed even when the processing accuracy of fine patterns is limited or when a Mizohori capacitor is used. A dynamic RAM with a large storage capacity such as 1M bits can also be realized.

In addition, in this embodiment, the complementary data lines arranged on the left and right sides of the sense amplifier SAI are short-circuited to each other, so that the RA is resistant to soft errors caused by alpha rays.
You can get M.

That is, when the precharge circuit PC is rendered inactive each time access to the RAM is started, the complementary data line is rendered floating in response.

The complementary data lines in this state are susceptible to the effects of α rays because their respective levels are substantially determined only by the charges held in their respective capacitors. 1
If one data line is irradiated with α rays, the level of that data, 'tJ ray, will be lowered by the leakage current caused by the α rays. If the level of one data line is changed, the level difference between complementary data lines will be undesirably changed accordingly. The influence of alpha rays is particularly severe when the level between complementary data lines is not sufficiently increased, such as at the beginning of a data signal sensing operation.

FIG. 5A shows the voltage waveform of the complementary data line when the reference potential is changed by alpha radiation. Data III (hereinafter referred to as read data line) to which a read data signal from one memory cell of the complementary data lines is to be applied is indicated by a solid line in FIG. 5A when memory cell selection is started. The signal is set to high level H or low level L as shown in FIG. The other data line (hereinafter referred to as a reference data line) to which a reference potential is applied among the complementary data lines is set to the reference potential Vref by selecting a dummy cell. In this case, the potential of the reference data line is lowered as indicated by the broken line in FIG. 5A due to the influence of the alpha rays. As a result, the reference potential V ref applied to the reference data line when the dummy cell is selected is lower than that in the case where there is no influence from α rays. Due to the decrease in the reference potential Vref, the low level L of the read data line and the reference potential Vre
The level difference with f is undesirably reduced. however,
According to this embodiment, the reference data line has substantially twice the data line capacitance by virtue of the fact that it is coupled to the corresponding data line of the unselected memoriar as described above. . Therefore, even if leakage current is generated by α rays, fluctuations in the reference potential V ref can be suppressed to a small level. Due to the small variation in the reference potential V ref, the decrease in the level difference between complementary data lines in reading out the level is reduced.

FIG. 5B shows a voltage waveform when the level of the data line to which high-level read data is to be applied is influenced by alpha rays.

That is, by irradiating the read data line with α rays, the charge accumulated in the capacitance CO therein is reduced. As a result, the level of the read data line changes to the solid line curve in FIG. 5B. In other words, the level of the read data line lowered in this way remains at the read high level.

Note that it is preferable that the capacitance value of the capacitor Cd constituting the dummy cell is made slightly larger than that of the capacitor Cs of the memory cell, considering the following points. In other words, when reading low level L and the level of the read data line is affected by α rays, the drop in the level of the read data line remains unchanged as the reference voltage V r
This increases the read level margin for ef. Focusing on this, the reference voltage V ref is set to be halfway between the high level H° of the read data line that is lowered by α rays and the low level L of the read data line when there is no influence from α rays. It is desirable that In other words, the dummy cell capacitor Cd
is the worst case of the level difference between complementary data lines caused by α rays in the short time from when each data line is placed in a floating state until the sense amplifier is activated. It is desirable to set a value that gives an appropriate offset to the reference voltage Vref.

Note that since the α rays are irradiated onto the semiconductor substrate substantially randomly, it is natural that the capacitors of the memory cells or the capacitors of the dummy cells can also be irradiated with the α rays. in this case,
Since the number of dummy cells is small, the probability that the capacitor will be irradiated with alpha rays is negligible. On the other hand, since the capacitance value of the capacitor of a memory cell is extremely small, when it is irradiated with alpha rays, much of the stored charge is reduced. In this case, a circuit countermeasure is possible, for example, by employing a known error correction structure using a parity bit and an error correction circuit.

FIG. 6 shows a circuit diagram showing another embodiment of the present invention.

In this embodiment circuit, instead of the shared sense amplifier method described above, a switch MO3FET is provided between corresponding data lines of two memory arrays ML and MR, each of which is provided with a sense amplifier SA. In addition, in Fig. 6,
The precharge circuit is not shown because it is not directly related to the main points described below.

To explain the memory array ML arranged on the left side of the figure, a pair of complementary data lines DL and D are arranged in parallel.
L is directly coupled to the input/output node of a sense amplifier SA configured by MO5FETs QI and Q2 similar to those in the above embodiment. Moreover, this complementary data line D1. ．． The DL is provided with an active restore circuit AR. Such complementary data 1jlD+7. The structure of the memory cell MC coupled to DL is the same as that of the memory cell MC shown in FIGS. 2A and 2B, so its explanation will be omitted.

MO3FET that puts the above sense amplifier SA into operation state
Q27. The gate of Q10 is supplied with timing signals φ1, Pl, and φLP2, which are generated in the same manner as described above when this memory array ML is brought into the selected state. Each data line of memory array ML and common data line CD end, CDI
Switches MO5FETQ30 to Q33, each of which constitutes a column switch circuit CWL, are provided between them. This causes the selection signal Y1. generated by the column address decoder. ．． A pair of complementary data lines corresponding to I and YLn are coupled to common complementary data lines CDI and CDI.

The memory array i'MR on the right side of FIG. 6 has data lines in one-to-one correspondence with each data line of the memory array ML.

This memory array MR is the memory array ML on the left side above.
Sense amplifier SA and column switch circuit CW similar to
R is provided. Operation timing signals of Hince amplifier SA φRPI and φI? P2 is generated when this memory array MR is brought into a selected state.

The full-size dummy cell DC is the memory array ML,! :
! It is provided only on one of the mutually corresponding data lines of IJR. Although not particularly limited, in each memory array, dummy cells are provided only on one of the complementary data lines. That is, as shown in the figure, in response to the fact that the upper data line DL of the complementary data lines DL and DL of the left memory array ML is provided with the dummy cell DC,
A dummy cell DC is provided in the lower data VMDL of the right memory array MR. Since these dummy cells are similar to those shown in FIG. 2 above, detailed explanation thereof will be omitted.

Switches MO3FETQ34 to Q are connected between the corresponding data lines of the left and right memory arrays ML and MR, respectively.
37 are provided. Switch MO3FETQ34 provided between each upper data line DL of memory arrays ML and MR
．． Gates such as Q36 are shared and receive timing signal φ
1 is supplied. In addition, a switch MO3FETQ35. is provided between the lower data lines DL. The gate of Q37 is shared and supplied with timing signal φ2.

The circuit of this embodiment uses timing signals φ1. φ2, φLPI, φ
LP2,φl? P1. 2 as the timing of φRP2 is appropriately changed as will become clear from the following explanation, and row address decoders (not shown) corresponding to each of memory arrays ML and MR are appropriately changed. Two configurations are possible.

In the first configuration, left memory array ML and right memory array MR are selectively selected.

That is, a row address decoder (not shown) that should correspond to the two memory arrays ML and MH is configured to select one of the plurality of word lines of the two memory arrays ML and MR based on the row address signal. be done. The common data lines CI)1 and CI)l and the common data lines C1) and CI)2 are selected by a second column switch circuit (not shown) similar to the previous embodiment.

The operation of the circuit in this first configuration is similar to the circuit of the embodiment shown in Figures 2A and 2B.

However, each memory array ML and MF? The sense amplifier SA and active squirrel (
- The child circuit A is different in that only the one corresponding to the selected memory array is activated.

In other words, for example, the memory area on the left i Ivi L
When the memory cell coupled to the upper data line 1) I of the memory array M L is selected, the timing signal φ1 is activated as shown in FIG. switch to low level) JO3
FETQ34. Q36 etc. are turned off first.

As a result, when a memory cell coupled to the upper data line DL of the left memory array ML is selected, the data line DL is separated from the corresponding upper data line of the right memory array MR. . , 2, the dummy word line DWL is set to a high selection level in response to the selection of the memory cell coupled to the upper data line. In response, the dummy cell coupled to the lower data line of the right memory array MR is selected. The timing signal φ2 is still kept at a high level even if the dummy cell is selected as shown in the seventh diagram. As a result, the lower data line DL of the left and right memory arrays ML, MR,
DL are brought to the same reference voltage Vref by full-sized dummy cells, since they remain coupled together as in the previous embodiment. timing signal φ
2 is an input (
The signal ψLPi is set to a low level as shown in FIG. 7 in synchronization with the timing at which it is set to a high level as shown in FIG. 7C. This allows Suin (-M
O5FE'T'Q35. Q37 etc. are turned off, and the amount of data in the left and right memory arrays is separated.

The sense amplifiers SA of the left memory array M L are operated all at once according to the above-mentioned miniaturization signal φLPI and the subsequent generated φ1.P2, and the read signal from the selected memory cell is amplified. At an appropriate timing after amplifier SA is operated, data line selection signals YLI to Y L rr are generated to select a pair of complementary data lines in memory array ML.

According to the second configuration, two memory arrays ML and MR
are simultaneously selected by appropriately configuring a row address decoder (not shown). Memory array M
Each word line of L is in one-to-one correspondence with each word line of memory array iMR.

The mutually corresponding word lines of memory arrays ML and MR are coupled back to the memory cells that are coupled to the mutually corresponding data lines of the respective memory arrays ML and MR. Timing signals φLPI, φLP2, φPR1, and φPR2 for controlling the operations of the sense amplifiers coupled to memory arrays ML and MR, respectively, are made the same, unlike the first configuration described above. As will be clear from the following explanation, the timing signals φ1 and φ2 for controlling the switch circuits (Q34 to Q37) provided between the memory arrays ML and MR are different from those in the first configuration. changed to .

The operation of the circuit having the second configuration is as follows.

The timing signals φ1 and φ2 are the RAS signal as shown in FIG. 8A.
If it is set to a high level as shown in Figure 8, it is set to a high level as shown in the 8th diagram. As a result, the switch circuit is turned on, and the data lines corresponding to each of memory arrays ML and MR are short-circuited to each other.

At this time, each data line is set to a bridge level equal to the voltage Vcc of the five circuits.

Access to the RAM is started by setting the RA S IFJ number to 1 value.

M O3F E T coupled to the data line to be used as the read data line of the timing signals φl and φ2
The timing signal for controlling the word line is set to ``] before the word line selection starts.For example, the upper data line DL of each complementary data line of the memory arrays ML and MR is If it is considered as a reading data line,
Timing signal φ17! l<Low like the 8th plan [Novel number Kosamaru. This electrically isolates the upper data lines of memory arrays ML and MR from each other.

After one of the timing signals φ1 or φ2 is set to low level, one word I' line corresponding to each other in memory arrays ML and MR is selected. In synchronization with the word line selection, one of the tammy word lines DWI and DWl.
is selected. As a result, data signals from the memory cells are applied to each read and data line of memory arrays ML and MR, and a reference potential is applied to each reference data line.

After the dummy word line is selected, the timing signal for controlling the sense amplifier is used as the timing signal for controlling the MOS FET coupled to the reference data line among the timing signals φl and φ2. It is set to low level until it is generated. Thereby, the reference data lines of memory arrays ML and MR are electrically isolated from each other.

After that, the timing signals φLPI, ψRPI, φL
P2, and φl? By generating P2 as shown in FIG. 8C, sense amplifier SA coupled to each of memory arrays ML and MR is operated.

After the operation of the sense amplifier SA, a data line selection signal is generated from a column address decoder (not shown), and one complementary data line of each of the memory arrays ML and MR is connected to the common data lines CD1, CI)1, CD2 and C, respectively.
It is coupled to D2.

In this embodiment, since the sense amplifier SA and the data line are closely connected, the high-speed operation of the sense amplifier SA (
u4i: Every plan is worth it.

In this embodiment as well, full-size dummy cells can be used (to form the read reference voltage). Also, the data line f! ! Since the number of visitors is temporarily large, from 8.S, it is possible to strengthen the resistance to soft errors caused by alpha rays as described above.

FIG. 9 is a circuit diagram of a dynamic RAM according to another embodiment.

Following this practical hfh example, one memory array M-AR
Complementary data lines DLO and DLO in Y are connected to adjacent complementary data lines 1) 1.1. Timing signals φ1.DL1 and DL1, respectively. φ2 controls the speed control 'L MO3FE''Qi] 0 to Q113
is provided. Although not particularly limited, MOS F
The wiring 5HLO for connecting E'rQ 110 and Qllll in series is also crossed by the data lines DLO and Dl, 1 in order to better balance the capacitance between the data lines. Similarly, the wiring S HLO also intersects with DLO and DLI.

In addition, MO3FE'l'Q110, Qllll, Ql12
and Q113 are connected in series with each other and turned on and off at the same time, so each of them is one MOS
It may be replaced with FET. Each full-size dummy line has a data line DLO.

It is connected to π7. MO3F'ETQ114 to Qllll forming a column switch circuit are provided between each data line and the common data lines CD and CD. Note that in FIG. 9, the active restore circuit and precharge circuit to be coupled to each of the complementary data lines are omitted to avoid complicating the drawing.

The circuit operation of this embodiment is made almost the same as that of the embodiment of FIG. 6 above.

That is, one of the timing signals φI and φ2 is set to low level before the start of word line selection (in advance), and the other one is set to low level after the start of word line selection and before the start of the operation of the sense amplifier SA. The two MOSFETs connected in series between the two data lines to be read data lines are set to low level.
is turned off before the start of word line selection, and the two series-connected MOS F E'r provided between the two data lines to be used as reference data lines have a reference potential formed by a dummy cell. is then turned off.

The fluctuation of the reference potential due to α rays is caused by the two reference data lines being
Since they are short-circuited to each other until just before the sense amplifier SA starts operating, it becomes small.

FIG. 10 is a circuit diagram of a dynamic RAM according to yet another embodiment.

The RAM of this embodiment uses a half precharge method and does not have dummy cells.

Like the embodiment shown in FIG. 6, the RAM of this embodiment has a switch circuit SW consisting of MO3FETQ34°Q35 between the data lines corresponding to each of memory arrays ML and MR.

A sense amplifier SA, a precharge circuit PC, and a memory cell (not shown) are coupled to complementary data lines DL and DL of memory arrays ML and MR, respectively.

Each data line is also coupled to a column switch circuit as shown in FIG.

The precharge circuit PC is connected to the complementary data lines 1. as shown. ．． N-channel MO3 installed between DL
It is composed of FETQ12B.

Sense amplifier SA consists of N-channel MO3FETQI20, Q121, which constitutes a CMOS latch circuit.
, and P channel MO3FE'l'Q122, Q12
Contains 3. The sense amplifier SA further includes a MO3FETQ
N-channel MO3F for power switch provided between the common source of 120 and Q121 and the ground point of the circuit
ETQ124゜Q125 and MO3 P-channel MO for the power switch connected between the common source of FETQI 22 and Q123 and the circuit power supply voltage Vcc
S FETQ126. Including Q127. MOS F E
TQ124 and Q126 are turned on and off at the same time by timing signals φpaLφpal having mutually opposite phases, and similarly, MO3FETs QI 25 and Q127 are turned on and off by timing signals φpa2. It is turned on and off simultaneously by φpa2.

According to this embodiment, the precharge levels of complementary data lines DL and DL of memory arrays ML and MR are set as follows.

That is, when the RAM is changed from an access state to a non-access state, each word line (not shown) in memory arrays ML and MR is set to a low non-selection level, and the power switch MO3FBTQ is set to a low non-select level.
The timing signals φpa1, φpa2, and φpaLφpa are set to turn off I24 to Q127.
2 are set to low level and high level, respectively. Further, the precharge timing signal φpc is set to high level.

By setting the timing signal φpc to a high level, the precharge circuit PC is activated. The precharge circuit PC is connected to the complementary data line DL to which it is coupled.
and DL to redistribute their mutual charges. As a result, complementary data lines DL and DL, which had been set to a high level equal to one power supply voltage Vcc and a low level equal to -ground potential, respectively, according to the previous amplification operation of the sense amplifier SA.
is brought to a precharge level equal to VVcc/2. This precharge level of complementary data lines DL and DL is regarded as a reference potential in the case of reading data signals from memory cells.

The operation of the circuit of this embodiment is substantially the same as that of the embodiment of FIG. 6, except for the difference in precharge level. Therefore, a description of the circuit operation after the precharge operation will be omitted.

〔effect〕

(Of the 11 pairs of corresponding data lines of the memory array,
By short-circuiting the data line to which the dummy cell to be selected is coupled, its stray capacitance value can be made twice the stray capacitance value of the data line to which the memory cell to be selected is coupled. This provides the effect that a full-sized dummy cell can form a reference voltage at an intermediate level between the read high level and low level of the data line.

(2) Since the circuit ground potential is stored in advance in the full-sized dummy cell, it is possible to form a read reference voltage that is stable even with fluctuations in the power supply voltage.

(3) Since full-sized dummy cells can be used due to the above (]), it is possible to obtain the effect that the operating margin of the circuit can be increased even when the processing precision of fine patterns is limited or the Mizohori capacitor is adopted. This allows dynamic type R with large storage capacity such as IM Pi I.
AM will also become possible.

(4) By short-circuiting the data line and holding the precharge level, the stray capacitance value can be increased. This makes it possible to reduce the drop in the level of the data line due to α rays, thereby achieving the effect that the software 1-error resistance can be strengthened.

(5) Assuming the worst case of the reference voltage being affected by alpha rays, by providing an offset on the low level side, it is possible to secure a level margin against a drop on the high level side, which works in conjunction with the effect of (4) above. The effect is that the resistance to soft errors can be further strengthened.

(6) Due to the synergistic effects of +11 to 5) above, miniaturization of memory cells and dummy cells can be realized.
It is possible to achieve the effect of reducing the size of the amplifier of the dynamic RAM or increasing the storage capacity.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. Dynamic RAM
The specific configuration of the memory array and the configuration of its peripheral circuits can take various embodiments. For example, the read reference voltage may be formed not only by using a full-sized dummy cell as described above but also by a full-sized dummy cell that is precharged to a voltage that is half the power supply voltage. That is, in this case, a full-size dummy cell is coupled to each data line in one memory array. Also, every other data line DL, DL... (DL
, DI-...) are provided with switches MO5FET as in the embodiment of FIG. 9, respectively. Data lines to which a reference potential is applied by each full-size dummy cell are short-circuited until the sense amplifier starts operating. In this case, the precharge level of each data line after each data line is set to a floating state until the word line and dummy word line are selected, and the sense amplifier starts operating after the dummy word line is selected. The reference potential LJ applied to each reference data line up to LJ is held by the stray capacitance increased by the interconnection of the data lines. As a result, the resistance to soft errors can be enhanced in the same manner as described above. Note that when such half-precharged full-size dummy cells are used, every other data line among the complementary data lines that are simultaneously shorted to each other by the switch circuit does not necessarily constitute a set. It doesn't have to be done. The number of alternate data lines that are simultaneously shorted together can be set appropriately.

The half-precharge dummy cell in this case can also be changed to a half-size dummy cell.

The embodiment of FIG. 9 can be changed to a dummy cell-less system like the embodiment of FIG. 10. In this case, the sense amplifier and precharge circuit (not shown) in FIG. 9 are changed to those in FIG. 10, for example, and the dummy cells are omitted. In this case, the timing signal φ1. The number of data lines that are short-circuited to each other according to φ2 does not have to be two. The precharge level of each data line may not be Vcc/2. Instead of simply shorting the complementary data lines together, the precharge circuit may be configured to couple each data line to a suitable potential source, such as a voltage divider circuit.

[Application field]

The present invention can be widely used in memories such as dynamic RAMs that utilize read reference voltages.

Dynamic RAM does not necessarily mean an 1111il independent device. For example, RAM
may be a RAM formed on one semiconductor substrate together with various circuits constituting a microcomputer system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the main part of a dynamic RAM according to the present invention, FIGS. 2A and 2B are circuit diagrams showing a specific embodiment of the memory array, sense amplifier, etc. Figure 3 shows the second
A specific circuit diagram of block UARO in Figure A, Figure 4 is a timing diagram showing an example of its operation, and Figure 5A is a timing diagram showing an example of its operation.
6 and 5B are waveform diagrams showing an example of a read operation of a memory cell, FIG. 6 is a circuit diagram showing another embodiment of the present invention, and FIGS. The operation waveform diagram of the embodiment, FIGS. 9 and 10 are circuit diagrams of other embodiments, respectively.

Claims (1)

[Claims] 1. A plurality of data lines to which a plurality of memory cells each consisting of an address selection MOSFET and an information storage capacitor are coupled, and data to which a reference potential is applied when reading data from the memory cell. a switch M that couples the line to an unselected data line to increase its effective parasitic capacitance value;
A dynamic type R characterized by including an OSFET.
A.M. 2. The dynamic RAM according to claim 1, wherein the switch MOSFET selectively couples data lines of memory arrays arranged on the left and right sides of the sense amplifier. 3. The read reference potential is formed by a dummy cell consisting of an address selection MOSFET and an information storage capacitor, which are formed under almost the same design conditions as the memory cell, and the data line to which the selected dummy cell is connected. Dynamic type according to claim 1 or 2, characterized in that the switch MOSFET is turned on and the switch MOSFET is turned off at the timing when the sense amplifier becomes operational. RAM. 4. The reference voltage is set to have an offset on the low level side with respect to an intermediate potential between a read high level and a low level. Dynamic RAM described
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