JPS61210390A - Pattern generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a pattern generation device, and more particularly, to a pattern generation device suitable for downsizing data storage devices and increasing pattern generation speed.

[Background of the invention]

When manufacturing semiconductor devices such as ICs and LSIs, a pattern is drawn on a mask or reticle, and the pattern is printed onto a wafer using this as a master plate. The apparatus for inspecting a pattern drawn on the mask or reticle includes a pattern generator for generating a design data pattern stored in a memory of the pattern generator and for comparing it with the pattern. It has become.

As a conventional design data pattern generator, for example, "Graphic Pattern Generation Method" 16th 8LCE Academic Lecture Proceedings N
As described in No. 2706, a method has been developed that generates a rectangular pattern based on data on vertex coordinates and side inclinations.

Patterns other than rectangles are decomposed into rectangles, the coordinates of each vertex and the slope of the sides are given, and the generated rectangular patterns are synthesized to obtain the desired pattern.

However, as IC/LSI circuit patterns become finer, the number of rectangular patterns tends to increase. Especially IM, 4
In a VLSI for M-bit memory, the number of these is enormous, and in order to store and store this rectangular data, a large number of storage devices such as magnetic tapes and magnetic disks are required.

In addition, when generating design patterns at high speed while reading a large amount of rectangular data from the storage device in synchronization with pattern inspection, the large amount of data causes a long data reading time, which is an obstacle to speeding up the process. It is becoming.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a design data pattern generation device that reduces the number of design data required to generate a design pattern, reduces the size of a data storage device, and increases the speed of pattern generation.

[Summary of the invention]

In order to achieve the above object, the present invention provides memory IC, LS
Focusing on the fact that most of the circuit patterns of I are composed of figures in which several kinds of basic figures are regularly arranged, based on the binarized data of the basic figures and the design data representing this arrangement rule, It is characterized by automatically generating design patterns.

Therefore, in the pattern generator of the present invention, two basic figures
An image memory that stores value image data, two buffer memories that store a design pattern corresponding to one scanning line of a linear image sensor, and a portion of the image memory that is read out sequentially in fixed pixel (byte) units to store continuous data. 2
A barrel shift circuit is provided that creates one byte of data by applying a certain shift to the byte of data.
Based on the array data of the basic figure and the coordinate measurement values detected from the scanning position of the linear image sensor, a part of the image memory is sequentially read out in byte positions, and after a knot operation is performed, it is sequentially written to a predetermined address on one buffer memory. . Then, while switching the buffer memory to be written to every line scan of the linear image sensor that performs pattern detection, in parallel with writing data to one buffer memory, data created during the previous scanning period is read from the other buffer memory. However, it is configured to convert into serial data in synchronization with the scanning of the linear image sensor and output a design pattern signal.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 9.

FIG. 2 shows the overall configuration of a reticle pattern inspection apparatus to which the present invention is applied. 2, the pattern of a test reticle 37 mounted on an XY scanning stage 38 is detected by an imager 34 through an objective lens 39. Further, this image signal is processed by a binarization circuit 35 to obtain a binary image signal 41.

On the other hand, the inspection data storage device 31 stores design data that has been converted into a format suitable for inspection based on the design information used when manufacturing the test reticle. A pattern generator 32 generates a design pattern signal 40 corresponding to the reticle 37 under test. This design pattern signal 40 corresponds to the binary image signal 41 that detected the reticle under test, and the synchronization between the two is based on the coordinate signal 42 of the XY stage 38. Controlled by no one. The design pattern signal 40 and the binary image signal 41 obtained by detecting the reticle under test 37 are checked by a comparator 33 for matches and mismatches, and areas where there is mismatch are determined as defects.

FIG. 3 shows an example of a pattern on a test reticle. In particular, in a reticle for memory IC and LSI, as shown in the figure, the pattern in the 7: part is a specific pattern such as basic figures 45 and 46. It consists of a repeating pattern of figures.

Detect such a lenacle pattern with an imager, and 2 (
As shown in the example of FIG. 5, the vL-converted image signal is YA=Q +X7z0 corresponding to the detection scan of the imager.
, 1 , 2 , ... n , YL= 1 :X1=
0.1, 2. . . . Binarized data in the order of n is obtained.

The present invention generates a corresponding design pattern signal in synchronization with this binary data, and as shown in FIG. Repetition interval xp”yp, number of repetitions M
-N and the design data representing the array head coordinates xn*ya of the basic figure 47, a design pattern signal is automatically generated.

A specific example of the configuration of the design pattern generator according to the present invention is shown in FIG. In the figure, each of the buffer memories 3 and 4 is for storing a design pattern for one scanning line created from design data. A pattern that precedes the signal coordinate YL by one line is created and stored based on the binary data of the basic figures stored in the image memory 2 and the design data indicating the arrangement of the basic figures input to the computer 1.

At the same time, from the other buffer memory, the binary design pattern created and stored during the previous scanning time is transferred to the output binary data of the imager @binarization circuit (Fig. 2). The signals are read out synchronously and sequentially, and generated while being converted into a bit string by the shift register 7. In this way, a design pattern is created that is one scanning line ahead of the scanning line of the image pickup device, and the design pattern is simultaneously output in real time.As the line scanning progresses, the switching circuits 5, 6...
17, patterns are generated while sequentially switching between the pattern creation buffer memory and the output buffer memory.

The design pattern is created by xp*Yp, which represents the repetition interval in each of the X and Y directions of the basic figure input to the computer 1.
X'f is stored in one image memory 2 based on the number of repetitions M and N in each direction, xB and VB data that designates the starting position coordinates to start repeated development, and YQ that indicates the Y coordinate of the scanning line of the image pickup device. A part of the basic image data thus created is read out and repeatedly written onto the pattern creation buffer memory 3 or 4.

This will be explained using an example of pattern creation of scanning line (yL+t) shown in Figure @6. Here, the image data to be read from the ITII image memory is Ypt=(yL+1)-(yn+(h-1) at the Y direction address.
)・yp) The data at the row address YM is shown as yp). However, here, it is assumed that the following conditions are satisfied: YL≧YM≧Q (YL is the bit length of the basic image data in the Y direction) R=1.2...N.

This image data is stored on the buffer memory as shown in FIG.
1.2. . . .M) A pattern is created by sequentially and repeatedly storing data starting from each address position indicated by .

However, if this image data is read and written bit by bit, it will take a long time to create a pattern, which is disadvantageous in generating patterns at high speed. For this reason, in the present invention, the predetermined number of bits is one byte, and one byte is read and written one byte at a time.

Then, as shown in FIG. 8, Y
After specifying the row address with M, read the column address in the X direction in the order of XM = 0111...
From the position indicated by the byte e address XBUF = XB /N (where N is the data bit length of 1 byte) on the buffer memory, the IN next address is incremented by 1 at byte coordinates. In addition, XBUF' is an integer d and a positive fraction Xs
(Xy-r).

Xaur=I with the data read in steps 1 and 2 as is.

■+1. . . . Instead, data shifted by the bit amount of each Xs is created and stored. The reason for shifting in this manner is that it is not possible to specify the valley bit position using only the byte-level address XBUF.

Furthermore, in the same way as above, XM = Q, 1,
... byte data on the buffer memory while performing the /ft operation of the byte number) (Buy=(XB+J-11Xp)/N (however,
j=1.2. . . . (M-1)) and the subsequent addresses to create a design pattern for the scanning line (YA+1).

Next, this hardware configuration will be explained. Row in Figure 1
Address pointer 14, column address pointer 15
is for latching and instructing read byte addresses YM and XM of both image memories 2 described above based on instructions from the computer 1. The latch 9 holds 1 byte of data read from the image memory 2. On the other hand, the launch 10 is configured to latch the previous byte of data held by the latch 9.

As a result, the register 11 can be inputted to the barrel shifter 12 by inputting 2 consecutive bytes of read data.
It is possible to output a complete shift operation result for one byte to be written to the buffer memory, including bit data carried forward from one adjacent byte of data based on the shift amount x3 specified by.

After holding this result in the latch 13, the buffer address pointer 16 on the buffer memory (3 in the illustrated example)
The address coordinates XBUFK shown by are sequentially stored and a pattern is created.

As shown in FIG. 9, a plurality of sets of design pattern generators 52, 53, and 54 are prepared, and a figure type code is given to the basic figure stored in each set, and the figure type code is also specified in the design data 50. If this method is used, the design pattern generators are operated in parallel while the data distributor 51 is used to supply design data to the corresponding design pattern generator, and the output signal is
By combining the R and circuit 55, it is also possible to generate a figure pattern consisting of repetitions of a plurality of basic figures as shown in the example of Figure 8g3.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the number of design data required to generate a design pattern, and the data storage device can be downsized.
A designed pattern generation device capable of speeding up pattern generation can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a pattern generator according to the present invention, and FIG.
The figure shows the overall w4 configuration of a reticle pattern inspection apparatus to which the present invention is applied, FIG. 3 is an explanatory diagram of an example of a circuit pattern on the reticle, FIG. 4 is an explanatory diagram of a pattern description format, and FIG. 6 is a design pattern generation diagram. # An explanatory diagram of the calculation operation of the device, Fig. 7 is an explanatory diagram of the operating principle of the pattern generator, Fig. 8 is an explanatory diagram of the operation of the actual design pattern generator, and Fig. 9 is an explanatory diagram of the basic figure pattern expansion device of multiple types. FIG. 1... Calculator 2... Image memory 3.4
...Buffer memory time...Switching circuit 7...Shift register 8...Controller 9...Latch circuit A10
...Latch circuit B 11...Register 12.
...Barrel shifter 13...Latch circuit 14...
・Row address pointer 15...Column address pointer 16...Buffer address pointer 17...Switching circuit

Claims (1)

[Scope of Claims] 1. An image memory storing a basic figure pattern, and reading out the basic figure pattern from the image memory in units of bytes based on the array data of the basic figure, and fixing the data to two consecutive bytes. a barrel shift circuit that generates one byte of data by applying a shift of 1. A pattern generating device, characterized in that said data is alternately output as serial data to generate a repeating pattern of said basic graphic pattern. 2. Hold 1 byte of data read from the image memory in the first latch circuit, then transfer the data in the first latch circuit to the second latch circuit, and transfer the next 1 byte of data. The data is read from the image memory and held in the first latch circuit, and each data held in the first and second latch circuits is taken into the barrel shift circuit and combined, and the barrel shift circuit 2. The pattern generating device according to claim 1, wherein the pattern generating device shifts a byte of data by a shift amount designated by a register and outputs a complete 1-byte of data.