JPS61208844A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61208844A JPS61208844A JP5129085A JP5129085A JPS61208844A JP S61208844 A JPS61208844 A JP S61208844A JP 5129085 A JP5129085 A JP 5129085A JP 5129085 A JP5129085 A JP 5129085A JP S61208844 A JPS61208844 A JP S61208844A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resist
- region
- semiconductor substrate
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
この発明は、特に集積回路における素子分離に最適な半
導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention particularly relates to a method of manufacturing a semiconductor device that is optimal for element isolation in integrated circuits.
（ロ）従来技術
一般に、ＣＭＯ３構造の集積回路においてはフィールド
領域が反転するのを防ぐために選択酸化技術あるいは、
反転防止用高濃度領域の形成を用いて素子分離を行って
いる。(b) Prior art In general, in CMO3 structure integrated circuits, selective oxidation technology or
Element isolation is performed by forming a high concentration region for preventing inversion.
しかしながら、前記選択酸化技術においては、横方向へ
の酸化膜成長が比較的大きくなり集積度を高めていく場
合に不利である。However, in the selective oxidation technique, the oxide film grows relatively large in the lateral direction, which is disadvantageous when increasing the degree of integration.
また、プロセスそのものも比較的複雑であり、ひいては
活性領域への欠陥を誘起しやすいという問題を生じる。Furthermore, the process itself is relatively complicated, which results in the problem of easily inducing defects in the active region.
（ハ）目的
この発明は上記事情に鑑みてなされたもので、比較的簡
便な工程でもって素子を高密度にレイアウトすることの
できる半導体装置の製造方法を提供することを目的とし
ている。(c) Purpose This invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device in which elements can be laid out at a high density through relatively simple steps.
（ニ）構成
この発明に係る半導体装置の製造方法の特徴とする処は
、半導体基板の主表面に所望パターンの絶縁分離層を形
成する工程と、前記半導体基板をエピタキシャル成長さ
せることにより、前記絶縁分離層のない部分にエピタキ
シャル層を形成する工程とを具備したことにある。(D) Structure The method for manufacturing a semiconductor device according to the present invention is characterized by a step of forming an insulating separation layer of a desired pattern on the main surface of a semiconductor substrate, and a step of epitaxially growing the semiconductor substrate. The present invention also includes a step of forming an epitaxial layer in a portion where no layer exists.
（ホ）実施例
第１図はこの発明に係る半導体装置の製造方法の一実施
例を示す断面説明図である。なお、この実施例ではＣＭ
Ｏ３構造の集積回路における素子分離を行う場合を例に
とって説明する。(E) Embodiment FIG. 1 is an explanatory cross-sectional view showing an embodiment of the method for manufacturing a semiconductor device according to the present invention. In addition, in this example, CM
A case will be explained taking as an example a case where element isolation is performed in an integrated circuit having an O3 structure.
■ Ｎ型のシリコンからなる半導体基板１０の表面のＰ
チャネルのトランジスタを形成すべき部分にＰ十拡散領
域２０を形成する。次に、ＳｉＯ２からなる絶縁分離層
３０を半導体基板１０の表面に堆積させる。その後、前
記Ｐ十拡散領域２０と新たに形成すべきＮチャネルのト
ランジスタ領域とをそれぞれ分離するようなパターンの
レジスト４０を絶縁分離層３０の上に被着させる（第１
図（ａ）参照）。■ P on the surface of the semiconductor substrate 10 made of N-type silicon
A P diffusion region 20 is formed in a portion where a channel transistor is to be formed. Next, an insulating separation layer 30 made of SiO2 is deposited on the surface of the semiconductor substrate 10. Thereafter, a resist 40 having a pattern that separates the P diffusion region 20 from the newly formed N-channel transistor region is deposited on the insulating separation layer 30 (first
(See figure (a)).
■ 前記レジスト４０をマスクとして絶縁分離層３０を
エツチングする。その後、前記残余のレジスト４０を除
去する（第１図（ｂ）参照）。(2) Etching the insulating separation layer 30 using the resist 40 as a mask. Thereafter, the remaining resist 40 is removed (see FIG. 1(b)).
■ この半導体基板１０をエピタキシャル成長させるこ
とによりエピタキシャル層５０を形成する。なお、絶縁
分離Ｆｆ３０のない部分のみがエピタキシャル成長され
る一方、Ｐ十拡散領域２０も拡散される。(2) An epitaxial layer 50 is formed by epitaxially growing this semiconductor substrate 10. Note that while only the portion without the insulation isolation Ff30 is epitaxially grown, the P+ diffusion region 20 is also diffused.
このとき、エピタキシャル層５０が絶縁分離Ｗ１３０よ
りも厚くなるから、前記絶縁分離層３０とエピタキシャ
ル層５０とを表面ポリッシュしてそれぞれ同一高さにせ
しめる（第１図（Ｃ）参照）。At this time, since the epitaxial layer 50 becomes thicker than the insulation isolation layer W130, the surfaces of the insulation isolation layer 30 and the epitaxial layer 50 are polished so that they have the same height (see FIG. 1C).
■ Ｐ十拡散領域２０のあるエピタキシャル層５０以外
の部分にレジスト６０を被着する（第１図（ｄ）参照）
。このレジスト６０をマスクとしてＰ型不純物（例えば
ボロン）をイオン注入し、しかる後、アニールすること
によりＰウェル領域５０′を形成する（第１図（Ｐａｌ
参照）。■ Depositing a resist 60 on a portion other than the epitaxial layer 50 where the P1 diffusion region 20 is located (see FIG. 1(d)).
. A P-type impurity (for example, boron) is ion-implanted using this resist 60 as a mask, and then annealed to form a P-well region 50' (see FIG.
reference).
以下通常のＣＭＯ３構造の集積回路を形成する工程を行
う。The following steps are performed to form an integrated circuit having a normal CMO3 structure.
なお、上記実施例において、絶縁分離１３０は多結晶の
ものであればよく、例えばポリシリコン等でも好ましい
。In the above embodiment, the insulation isolation 130 may be made of polycrystalline material, and preferably polysilicon or the like, for example.
また、上記実施例ではＣＭＯ３構造の集積回路の場合を
例にとって説明したが、この発明はこれに限定されず、
バイポーラ構造の集積回路等の素子分離にも用いられる
ことは勿論である。Furthermore, although the above embodiments have been explained using an example of an integrated circuit having a CMO3 structure, the present invention is not limited to this.
Of course, it can also be used for element isolation of bipolar integrated circuits and the like.
（へ）効果
この発明は上記詳説したように、まず、半導体基板の主
表面に所望形状の絶縁分離層を形成し、その後、前記各
絶縁分離層間にエピタキシャル層を成長させているから
、従来用いられる選択酸化技術と比較して簡便な工程と
なり、しかも素子を高密度にレイアウトすることができ
る。(f) Effects As explained in detail above, this invention first forms an insulating separation layer of a desired shape on the main surface of a semiconductor substrate, and then grows an epitaxial layer between each of the insulating separation layers. This method is a simpler process than the selective oxidation technique used in the conventional method, and allows devices to be laid out at a high density.
また、上記実施例においては、本発明の効果と別異の効
果を得ることができる。即ち、ＣＭＯＳ形成時において
、各素子が絶縁分離層でもって完全に電気絶縁されてい
るから、チャンネルス）７パーを形成する必要がなくな
る。更に、Ｐウェル層の濃度が深さ方向に高くなるプロ
ファイルとなるから、ラッチアップにも強い構造にでき
る。Further, in the above embodiment, effects different from those of the present invention can be obtained. That is, when forming a CMOS, each element is completely electrically insulated by an insulating separation layer, so there is no need to form a channel. Furthermore, since the concentration of the P-well layer has a profile that increases in the depth direction, a structure that is resistant to latch-up can be achieved.
第１図はこの発明に係る半導体装置の製造方法の一実施
例を示す断面説明図である。
１０・・・半導体基板、３０・・・絶縁分離層、５０・
・・エピタキシャル層。FIG. 1 is an explanatory cross-sectional view showing an embodiment of the method for manufacturing a semiconductor device according to the present invention. DESCRIPTION OF SYMBOLS 10... Semiconductor substrate, 30... Insulating separation layer, 50...
...Epitaxial layer.
Claims (1)
を形成する工程と、 前記半導体基板をエピタキシャル成長させることにより
、前記絶縁分離層のない部分にエピタキシャル層を形成
する工程とを具備したことを特徴とする半導体装置の製
造方法。(1) The method comprises a step of forming an insulating separation layer in a desired pattern on the main surface of a semiconductor substrate, and a step of forming an epitaxial layer in a portion where there is no insulating separation layer by epitaxially growing the semiconductor substrate. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5129085A JPS61208844A (en) | 1985-03-13 | 1985-03-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5129085A JPS61208844A (en) | 1985-03-13 | 1985-03-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61208844A true JPS61208844A (en) | 1986-09-17 |
Family
ID=12882790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5129085A Pending JPS61208844A (en) | 1985-03-13 | 1985-03-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61208844A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59129439A (en) * | 1983-01-14 | 1984-07-25 | Nec Corp | Manufacture of substrate for semiconductor device |
| JPS6015975A (en) * | 1984-06-21 | 1985-01-26 | ア−ルシ−エ− コ−ポレ−ション | Method of producing mosfet |
-
1985
- 1985-03-13 JP JP5129085A patent/JPS61208844A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59129439A (en) * | 1983-01-14 | 1984-07-25 | Nec Corp | Manufacture of substrate for semiconductor device |
| JPS6015975A (en) * | 1984-06-21 | 1985-01-26 | ア−ルシ−エ− コ−ポレ−ション | Method of producing mosfet |
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