JPS61206249A - Laminated semiconductor integrated circuit device - Google Patents

Laminated semiconductor integrated circuit device

Info

Publication number
JPS61206249A
JPS61206249A JP4652085A JP4652085A JPS61206249A JP S61206249 A JPS61206249 A JP S61206249A JP 4652085 A JP4652085 A JP 4652085A JP 4652085 A JP4652085 A JP 4652085A JP S61206249 A JPS61206249 A JP S61206249A
Authority
JP
Japan
Prior art keywords
holes
chip
chips
wirings
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4652085A
Other languages
Japanese (ja)
Inventor
Chihei Miura
三浦　地平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4652085A priority Critical patent/JPS61206249A/en
Publication of JPS61206249A publication Critical patent/JPS61206249A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To enable effective wirings, to reduce a wiring region and to scale down the size of a laminated semiconductor integrated circuit device finally by arranging through-holes on a chip surface in a latticed manner and gradually narrowing spaces between adjacent through-holes toward a central section from the peripheral section of a chip. CONSTITUTION:A plurality of chips 1, 2 are superposed, through-holes 6 are formed to silicon substrates 5 for each chip, and chips are wired 7, thus enabling the wiring of a three-dimensional element and wirings among the elements. The number of the through-holes in the substrates is limited more than that of through-holes shaped to an insulating film due to multilayer wirings in active layers in the chips at that time. The distribution of the degree of congestion of wirings of the central section of the chip is made higher than the peripheral section of the chip, the through-holes in the substrate are disposed on the chip in consideration of the distribution of the degree of congestion of wirings, and bypasses until wirings among the chips reach to the through-holes in the substrates on the chips are reduced. The through-holes in the substrates are arranged on chip surfaces 13 in a latticed manner, and spaces between adjacent through-holes 14 are gradually narrowed toward the central sections from the peripheral sections of the chips.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、積層半導体集積回路装置、特に、並列度が高
く、ランダムな論理構造を有する大規模な論理回路に好
適な積層半導体集積回路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a stacked semiconductor integrated circuit device, and particularly to a stacked semiconductor integrated circuit device suitable for a large-scale logic circuit with a high degree of parallelism and a random logic structure. It is something.

〔発明の背景〕[Background of the invention]

最近、積層半導体集積回路装置の実現性、応用の研究が
始められている。現在までに提案されている装置は、上
記文献に記載のように、並列プロセッサ向きの規則的な
構造を有しており、基板に形成されるスルーホールの間
隔は固定である。しかし、もし現在の大型計算機のＣＰ
Ｕ部のようなランダムな論理回路を１つの積層半導体集
積回路装置で実現する場合には、素子の配置、素子間の
配線は上記の規則的な構造を持たない。従って、上記ス
ルーホールの間隔も、配線の効率化を計るためには、隣
接した半導体集積回路装置間の配線の混雑度に応じて可
変とする必要がある。この点については今まで配慮され
ていなかった。Recently, research has begun on the feasibility and application of stacked semiconductor integrated circuit devices. As described in the above-mentioned document, the devices proposed to date have a regular structure suitable for parallel processors, and the intervals between through holes formed in the substrate are fixed. However, if the current large computer's CP
When a random logic circuit like the U section is realized in one stacked semiconductor integrated circuit device, the arrangement of elements and the wiring between elements do not have the above-mentioned regular structure. Therefore, in order to improve wiring efficiency, the spacing between the through holes needs to be made variable depending on the degree of wiring congestion between adjacent semiconductor integrated circuit devices. This point has not been considered until now.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、積層半導体集積回路装置において、隣
接した半導体集積回路装置間の配線のために基板に形成
するスルーホールの間隔を場所に応じて可変とすること
により、効率的な配線を可能とし、配線領域を削減し、
最終的には積層半導体集積回路装置の寸法を縮小化する
ことを目的としている。An object of the present invention is to enable efficient wiring in a stacked semiconductor integrated circuit device by varying the spacing between through holes formed in a substrate for wiring between adjacent semiconductor integrated circuit devices depending on the location. and reduce the wiring area,
The ultimate objective is to reduce the size of a stacked semiconductor integrated circuit device.

〔発明の概要〕[Summary of the invention]

ランダムな論理構造を有する論理回路を半導体集積回路
で実現した時の特徴は、チップ周辺部からチップ中心部
へ向かうほど、配線の混雑度が高いことである。上記論
理回路を積層半導体集積回路で実現した場合、隣接した
チップ間の配線混雑度は、やはり、チップ周辺部からチ
ップ中心部に向かうほど高くなる。従って、隣接したチ
ップ間を通過するために形成する基板スルーホールは。When a logic circuit having a random logic structure is realized using a semiconductor integrated circuit, a characteristic feature is that the degree of wiring congestion increases from the periphery of the chip toward the center of the chip. When the above logic circuit is realized by a stacked semiconductor integrated circuit, the degree of wiring congestion between adjacent chips also increases from the periphery of the chip toward the center of the chip. Therefore, substrate through holes are formed to pass between adjacent chips.

チップ間配線の迂回を少なくし、配線領域を削減するた
めには、チップ周辺部よりもチップ中心部に多く存在す
ることが望ましい。この点に注目し、本発明では、積層
半導体集積回路において、上記スルーホールをチップ面
上で格子状に配列させ。In order to reduce detours of inter-chip wiring and reduce the wiring area, it is desirable that more wiring be present at the center of the chip than at the periphery of the chip. Focusing on this point, in the present invention, in a laminated semiconductor integrated circuit, the through holes are arranged in a grid pattern on the chip surface.

かつ、隣接した上記スルーホールの間隔を、上記チップ
周辺部から中心部に向かうほど狭まくする。Further, the distance between the adjacent through holes is narrowed from the periphery of the chip toward the center of the chip.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を第１図より説明する。 An embodiment of the present invention will be described below with reference to FIG.

第１図は、現在、実現性の検討が行なわれている積層半
導体集積回路の断面図である。複数個のチップを積み重
ね、各チップのシリコン基板にスルーホールを形成し、
チップ間配線を行なうことにより、３次元的な素子の配
線、素子間の配線を可能とするものである。ここで、基
板スルーホールの数は、チップ能動層内の多層配線を行
なうため絶縁膜に形成するスルーホールよりも数が限定
される。現状では１０００程度と考えられている。その
ため、基板スルーホールをチップ間配線のためにいかに
効率的にチップ上に配置するかが課題となる。第２図は
、ランダムな論理構造を有する論理回路で典型的なチッ
プ間配線の混雑度（単位面積当りの通過配線本数）分布
の予想図を示す。配線混雑度分布はチップ周辺部よりチ
ップ中心部の方が高くなっている。基板スルーホールの
チップ上の配置は上記配線混雑度分布を考慮して行ない
。FIG. 1 is a cross-sectional view of a stacked semiconductor integrated circuit whose feasibility is currently being studied. Stack multiple chips, form a through hole in the silicon substrate of each chip,
By performing inter-chip wiring, it is possible to perform three-dimensional wiring of elements and wiring between elements. Here, the number of substrate through-holes is more limited than the number of through-holes formed in the insulating film in order to perform multilayer wiring within the chip active layer. Currently, the number is thought to be around 1,000. Therefore, the challenge is how to efficiently arrange substrate through holes on chips for interchip wiring. FIG. 2 shows a predicted diagram of the distribution of typical inter-chip interconnect congestion (number of passing interconnects per unit area) in a logic circuit having a random logic structure. The wiring congestion level distribution is higher at the center of the chip than at the periphery of the chip. The arrangement of substrate through-holes on the chip is done in consideration of the above wiring congestion degree distribution.

チップ間配線がチップ上で基板スルーホールに到達する
までの迂回を少なくする必要がある。It is necessary to reduce the number of detours the interchip wiring takes on the chip to reach the substrate through holes.

この点を考慮して、本発明では・チップ上での基板スル
ーホールの配置を第３図のようにする。すなわち、基板
スルーホールをチップ面上に格子状に並べ、かつ隣接し
たスルーホールの間隔を、上記チップ周辺部から中心部
に向かうほど狭まくする。In consideration of this point, in the present invention, the substrate through-holes are arranged on the chip as shown in FIG. That is, the substrate through-holes are arranged in a grid pattern on the chip surface, and the distance between adjacent through-holes is narrowed from the periphery of the chip toward the center.

〔発明の効果〕〔Effect of the invention〕

本発明の効果は、積層半導体集積回路の寸法を縮小化す
ることにより、上記回路の製造コストを低減することに
ある。すなわち、チップ間配線の基板スルーホールに到
達するまでの迂回配線を少なくし、配ＩＩｇ領域を削減
する。An effect of the present invention is to reduce the manufacturing cost of the laminated semiconductor integrated circuit by reducing the size of the laminated semiconductor integrated circuit. That is, the number of detours of the interchip wiring to reach the substrate through hole is reduced, and the wiring area IIg is reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は積層半導体集積回路の断面図、第２図は積層半
導体集積回路内の隣接した２チップ間配線の混雑度分布
を示す図、第３図は積層半導体集積回路内の各チップ面
上における基板スルーホールの配置図である。 １．２・・・チップ、３・・・チップ間配線接続層、４
・・・チップ内能動層、５・・・シリコン基板、６・・
・基板スルーホール、７・・・チップ間配線、８・・・
チップ面。 ９・・・チップ面Ｙ軸、１ｏ・・・チップ面Ｙ軸上のチ
ップ間配線の混雑度、１１・・・チップ面Ｘ軸、１２・
・・チップ面Ｘ軸上のチップ間配線の混雑度、１３・・
・チップ面、１４・・・基板スルーホール。Fig. 1 is a cross-sectional view of a stacked semiconductor integrated circuit, Fig. 2 is a diagram showing the congestion degree distribution of wiring between two adjacent chips in the stacked semiconductor integrated circuit, and Fig. 3 is a diagram showing the distribution of the congestion degree of wiring between two adjacent chips in the stacked semiconductor integrated circuit. FIG. 1.2... Chip, 3... Inter-chip wiring connection layer, 4
...In-chip active layer, 5...Silicon substrate, 6...
・Board through hole, 7... Inter-chip wiring, 8...
Chip side. 9...Chip surface Y-axis, 1o...Congestion degree of inter-chip wiring on chip surface Y-axis, 11...Chip surface X-axis, 12.
・Congestion degree of inter-chip wiring on the chip surface X axis, 13...
・Chip surface, 14... Board through hole.

Claims (1)

【特許請求の範囲】[Claims] 　複数の半導体集積回路装置を積み重ね、隣接した上記
半導体集積回路装置間の配線を、上記半導体集積回路装
置の基板にスルーホールを形成して行なう積層半導体集
積回路装置において、上記スルーホールをチップ面上で
格子状に配列させ、かつ、隣接した上記スルーホールの
間隔を、上記チップの周辺部から中心部に向かうほど狭
まくしたことを特徴とする積層半導体集積回路装置。In a stacked semiconductor integrated circuit device in which a plurality of semiconductor integrated circuit devices are stacked and wiring between adjacent semiconductor integrated circuit devices is formed by forming through holes in the substrate of the semiconductor integrated circuit devices, the through holes are formed on the chip surface. A laminated semiconductor integrated circuit device characterized in that the through holes are arranged in a lattice pattern, and the interval between the adjacent through holes becomes narrower from the periphery toward the center of the chip.
JP4652085A 1985-03-11 1985-03-11 Laminated semiconductor integrated circuit device Pending JPS61206249A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4652085A JPS61206249A (en) 1985-03-11 1985-03-11 Laminated semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4652085A JPS61206249A (en) 1985-03-11 1985-03-11 Laminated semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS61206249A true JPS61206249A (en) 1986-09-12

Family

ID=12749548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4652085A Pending JPS61206249A (en) 1985-03-11 1985-03-11 Laminated semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS61206249A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003001597A2 (en) * 2001-06-21 2003-01-03 Giesecke & Devrient Gmbh Vertically contacted stacked chips

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003001597A2 (en) * 2001-06-21 2003-01-03 Giesecke & Devrient Gmbh Vertically contacted stacked chips
WO2003001597A3 (en) * 2001-06-21 2003-12-18 Giesecke & Devrient Gmbh Vertically contacted stacked chips

Similar Documents

Publication Publication Date Title
US7649249B2 (en) Semiconductor device, stacked structure, and manufacturing method
KR0160211B1 (en) Method for forming a monolithic electronic module by dicing wafer sacks
US6489688B1 (en) Area efficient bond pad placement
JP3422675B2 (en) Electronic integrated circuit package
TWI652788B (en) Chip package structure and chip package structure array
JPH09162279A (en) Semiconductor integrated circuit device and manufacture thereof
JP2003124377A (en) Interconnection method for semiconductor chip carrier and line
JP2018505558A (en) Semiconductor structure
TWI540653B (en) Methods and arrangements relating to semiconductor packages including multi-memory dies
TWI285422B (en) Chip structure and stacked chip package structure
US8283765B2 (en) Semiconductor chip and stacked semiconductor package having the same
KR20010104320A (en) Vertically integrated semiconductor system
US5552596A (en) Three-dimensional radiation detection device and process for the production of said device having elementary reading circuits hybridized by welding microbeads
CN114664669A (en) Semiconductor package and method of manufacturing the same
EP0417345B1 (en) Design method for VLSI chips arranged on a carrier and module thus designed
US7067352B1 (en) Vertical integrated package apparatus and method
JPS61206249A (en) Laminated semiconductor integrated circuit device
US9824954B2 (en) Semiconductor package comprising stacked integrated circuit chips having connection terminals and through electrodes symmetrically arranged
JPH0544829B2 (en)
KR100329952B1 (en) Semiconductor integrated circuit and wiring method thereof
JPS62194640A (en) Semiconductor integrated circuit using bump mounting
US20110108995A1 (en) Spiral staircase shaped stacked semiconductor package and method for manufacturing the same
JP2007242864A (en) Semiconductor device
JP7272587B2 (en) semiconductor equipment
KR101035597B1 (en) Structure of a bonding pad in semiconductor device