JPS61206059A - System for detecting and processing interface trouble - Google Patents

Abstract

PURPOSE:To analyze in detail the trouble and to shorten the interface trouble cause pursuing time by providing the a signal change detecting circuit, a memory circuit, etc., and storing the condition of the interface signal for a constant time. CONSTITUTION:Input output control signals X1-X3 and Y1-Y3 are selected at a selecting circuit 2-2, and inputted to a signal change detecting circuit 2-3. At the circuit 3, the change of the polarity of the selected signal is detected, and a starting trigger signal is given to a timing generating circuit 2-5 and a timer circuit 2-4. At the circuit 2-5, a trigger signal from the circuit 2-3 is received, and to a memory circuit 2-6, the timing necessary to store the condition of '1' and '0' of the signals X1-X3 and Y1-Y3 is supplied. Thus, the dialog of the interface in a certain time belt is stored to the circuit 2-6, and when the interface trouble is informed, the contents of the 2-6 can be read watched. Consequently, the trouble can be analyzed in detail and the pursuing time of the interface trouble cause can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a fault detection throughput formula for an input/output interface between a channel and an input/output device in a data processing device.

BACKGROUND OF THE INVENTION Conventionally, failure detection of an input/output interface between a channel and an input/output control device in this type of data center equipment is based on the expected state of a certain signal line on the input/output interface. Depending on whether or not there is a failure, if the condition indicates a state other than the expected value, it is determined that a failure has occurred and failure processing is executed. In addition, in order to monitor whether the interface dialog (signal exchange) between the channel and the input/output device is performed normally, a timer for monitoring the status of the input interface control signal is provided to avoid deadlock on the interface. That's what I do.

Problems to be Solved by the Invention However, in the conventional failure detection processing method for input/output interfaces, when a failure is detected, the status of the signal line of the input/output interface is not recorded at all, or the status of the signal line is not recorded. Due to timer O'timeout, etc., even if an interface failure is detected, only the final state of the interface signal line is memorized. Therefore, there is no intermediate dialogue information of the interface, and as a result, it takes time to find the cause of the two failures, and the failure occurs. The disadvantage is that it takes a lot of time to process.

Original F! A was made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology.Therefore, an object of the present invention is to set the interface control signal monitoring timer by assuming the previous interface dialog in advance. An interface control signal line is selected, and the state of the signal line is memorized at regular intervals from the moment the signal line changes, and when the predetermined time is reached, the memorization is stopped and the monitoring timer times out. An object of the present invention is to provide a new interface failure detection processing method that makes it possible to accurately know the interface dialog by finding stored information when a failure occurs.

Means for Solving Problems In order to achieve the above object, a means for monitoring the state of an input signal and notifying an abnormal state as an interface failure detection processing means between a channel and an input/output control device, and an interface. The control signal is configured to include means for freely selecting a control signal, means for detecting a change in the state of the selected control signal, and means for capturing the change in state and sequentially storing the states of the input/output interface signals. Ru.

Principle and operation of the invention The present invention stores the previous state of the signal line on the interface at fixed time intervals at the time when an interface failure is detected, and analyzes the interface failure from this stored status information. do.

Embodiments of the Invention Next, a preferred embodiment of the present invention, applied to the channel side, will be described in detail with reference to the drawings.

FIG. 1 is a system configuration diagram of the present invention. FIG. 2 is a block diagram showing an embodiment of the interface failure detection processing method according to the present invention.

FIG. 1, which shows the system configuration of the present invention, shows the relationship between channel l-1 consisting of an interface circuit and channel Ia structure and input/output control devices 1iE1-2 to l-N consisting of an interface circuit and input/output control mechanism. Indicates the connection status depending on the input/output interface.

FIG. 2, which shows one embodiment of the present invention, is a detailed diagram of the input/output interface shown in FIG. Although only the control signals Yl-Ya are illustrated, in reality, all input/output control mechanisms are targeted.

In FIG. 2, reference number 2-1 is an input/output interface signal driver/receiver circuit.

The input/output control signals Xi, X3, yl, y3 are supplied to the selection circuit 2.
For example, one signal xl is selected at -2 and input to the signal change detection circuit 2-3. Signal change detection circuit 2-3
Then, a change in the polarity of the corresponding signal XI is detected and a start trigger signal is given to the timing generation circuit 2-5 and the timer circuit 2-4. The timing generation circuit 2-5 receives the trigger signal from the signal change detection circuit 2-3 and outputs "1'" of the input/output control signals X1 to x3 and Y1 to Y3 to the storage circuit 2-6 at fixed time intervals. ” continues to supply the timing necessary to memorize the state.

The timer circuit 2-4 receives the trigger signal from the signal change detection circuit 2-3 and continues counting until the maximum time T that can be stored. The relationship between the storage capacity M of the storage circuit 2-6, time, and T is set to 70 to satisfy M)T/l.

Also, the signal state monitoring circuit 2-8 on the interface works on a signal Yl different from the signal selected by the selection circuit 2-2, but if there is no change in the state of the signal for longer than the state monitoring time, a timeout occurs. , generates a timeout signal and notifies it as an interface failure.

The timeout signal from the timer circuit 2-4 when the maximum memorable time T has passed and the timeout signal from the signal status monitoring circuit 2-8 are ORed in circuit 2-7, whichever occurs first. When the timeout signal is given to the timing generation circuit 2-5, the timing generation circuit 2
-5 stops supplying timing to the memory circuit 2-6 and stops storing the state of the input/output control signal.

As described above, the interface dialog from time A to time C shown in FIG. By reading and viewing the contents of the , you can know the dialogs of the interface in progress.

FIGS. 3 and 4 show an example of a dialog time chart of an interface related to the embodiment of the present invention.

FIG. 3 shows a normal dialog time chart, and FIG. 4 shows a dialog time chart in an abnormal situation.

In FIGS. 3 and 4, Xl-store indicates an output control signal from the channel, and Yl-Y3 indicates an input control signal from the input/output control device.

Referring to FIG. 3, the dialog of the interface will be explained.

When the Xl signal becomes 1 on, the Yl signal becomes 1 on, and the Yl signal status monitoring timer operates. at the same time,
When the Y2 signal becomes 1 on, the Xl signal becomes 1 off, X
The l signal becomes 1 on". When the me signal becomes 1 on", Y
When the Y2 signal becomes 1 off, the Xl signal becomes 1 off. When the Xl signal becomes 1 off, the Y3 signal becomes 1 on, and the Y3 signal becomes 1 on. Then, X3 (When the i signal becomes 1 on, and the X3 signal becomes 1 on, the Yl signal and Y3 signal become 1 off, and Yl
The signal monitoring timer is reset. Y3 signal is 1 off”
Then, the X3 signal becomes 1 off, and the interface dialog ends.

Fourth! In iJ, it is the same as in Figure 3 until point B in the figure, and the dialog stops because the Y3 signal does not turn 1 on after point B, and a timeout failure is detected depending on the status monitoring timer of Yl. Sanru.

However, regarding the status of the signal lines x1 to X3 and Yl-Y3 at time D, the only information we can get is that the Yl signal is 1 on and all others are 1 off, and it is not possible to determine whether the dialog in progress was normal. do not have.

Effects of the Invention As explained above, the present invention has a configuration in which the interface signal lines can be stored for each song at a certain time, so that the interface signal between the channel and the input/output control device at the time of failure can be stored. Dialogs can be known accurately, failures can be analyzed in detail, and the time required to find the cause of an interface failure can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing details of the main parts of the present invention, and FIGS. 3 and 4 are dialog time charts of an explanatory interface. 1-1... Channel, l-2 to l-N... Input/output control device, 2-1... Driver/receiver circuit, 2-2
...Selection circuit, 2-3...φ signal change detection circuit, 2-
4... Timer circuit, 2-5... Timing generation circuit, 2-6... Memory circuit, 2-7... IO circuit, 2-
8...Signal status monitoring circuit, Xl-X3-...Output control signal, Yl-Y3...Input control signal Patent applicant: NEC Co., Ltd., patent attorney Yutabe Kumagai Figure 111

Claims (1)

[Claims] In an input/output interface between a channel and an input/output control device, means for monitoring the state of an input signal and notifying an abnormal state, means for selecting an interface control signal, and a change in state of the selected control signal. 1. An interface fault detection processing method comprising: means for detecting a change in the state; and means for sequentially storing the state of an input/output interface control signal by capturing a change in the state.