JPS6120430A - Multifunction fuzzy logical circuit - Google Patents

Abstract

PURPOSE:To obtain a multifunction fuzzy logical circuit which is used as the base of a system suitable for handling a fuzzy logic, by providing plural different fuzzy logical circuits which use at least one of output currents of the first, the second and the third inputting circuits and an output current of a multi-output limit difference circuit, as at least one of input currents, respectively. CONSTITUTION:An input current and an output current of a fuzzy logical circuit 10 are denoted as Ii and Io, respectively. A shows an input/output state that the input current Ii flows in toward the circuit 10, and the output current Io flows out of the circuit 10. They are called as a suction input and a discharge output. The source S of two FETs 11, 12 is grounded. Also, their gates G are connected to each other, and also these gates G are connected to the drain D of one FET 11. When the discharge input current Ii is applied to the drain D of one FET 11, the discharge output current Io which becomes Ii=Io is obtained from the drain D of the other FET12.

Description

[Detailed description of the invention] Background of the invention This invention relates to multifunctional fuzzy logic circuits.

Fuzzy logic is a logic that deals with fuzziness, or "ambiguity." Ambiguity surrounds human thoughts and actions. Therefore, if such ambiguity can be quantified or theorized, it should be possible to apply it to the design of social systems such as traffic control, emergency, and applied medical systems, as well as robots created to imitate humans. In 1965, △
Since the concept of fuzzy sets was proposed by Zadeh, research on fuzzy logic has been conducted as a means of dealing with "ambiguity" from this perspective. However, the current situation is that much of this research is directed toward application to software systems using digital computers. Digital measurement m performs calculations based on binary logic consisting of O and 1, and although the calculation processing is extremely strict, it is necessary to add an A/D conversion circuit to the input of analog quantities. For this reason, when attempting to process a huge amount of information, there is a problem in that it takes a long time to see the final result. Furthermore, programs for applying fuzzy logic must be extremely complex, and complex processing requires a large digital computer, which is not economical.

In the first place, fuzzy logic is a logic that handles continuous values (0, 1) in the interval from O to 1, so it has the aspect that it is not compatible with digital computers based on binary logic. Furthermore, since fuzzy logic deals with wide and ambiguous quantities, calculations performed by digital computers do not require any degree of rigor. Therefore, it is desired to realize circuits and systems suitable for handling fuzzy logic.

SUMMARY OF THE INVENTION The present invention aims to provide a multifunctional fuzzy logic circuit as the basis for a system suitable for handling fuzzy logic.

The multifunctional fuzzy logic circuit according to the present invention generates at least one current having the same value and direction as the input current, and at least one current having the same value and opposite direction as the input current, and has one output. A current mirror, a multi-output current mirror, or a combination thereof.
first and second input circuits provided respectively for different types of input current; one output current mirror or multi-output current mirror of one of the first and second input circuits; Output current of one output current mirror of one input circuit or one of multiple output current mirrors
A wired OR that calculates the difference between one output current and one output current of the other input circuit, and this wired OR
a multi-output limit difference circuit consisting of a multi-output current mirror with input currents as input;
and a plurality of different fuzzy logic circuits each having at least one of its input currents the output currents of the first, second and third input circuits and the output current of the multi-output limit difference circuit. It is characterized by having the following.

a one-output current mirror or a multi-output current mirror of either the other of the first and second input circuits; an output current of a one-output current mirror of the other input circuit or one of the multi-output current mirrors; Another multi-output limit difference circuit is provided, which consists of a wired OR that calculates the difference between the output current and one output current of one input circuit, and a multi-output current mirror that receives the output current of this wired OR as input. It is preferable.

Here, the same value includes values that are close enough to not cause a practical problem. When the input circuit is configured with FETs, a current almost equal to the input current can be obtained,
Even if the transistor is a bipolar transistor, no practical problem will arise if the current amplification factor β is very large.

The basic operations of fuzzy logic include marginal difference, logical product, marginal use, marginal product, logical sum, logical product, absolute difference, implication, and equality. When the current mode is adopted as the operating mode and the limit difference circuit is configured with a current mirror, a wired OR, and a diode, the circuit that performs operations other than the limit difference among the basic operations described above will have one or more limit differences. This can be achieved using a difference circuit and wired OR. That is, the plurality of different fuzzy logic circuits described above can be constructed by a limit difference circuit and a wired OR. Moreover, the diode in the limit difference circuit can be replaced with a current mirror.

In this invention, since a multi-output limit difference circuit is provided, a plurality of limit difference calculation output currents can be obtained from this circuit. Therefore, it becomes possible to use not only the limit difference circuit but also a part of several other fuzzy logic circuits with this multi-output limit difference circuit. Moreover, since the diode in this circuit is replaced by a multi-output current mirror, no diode is required. Since the circuit configuration can be simplified in this way, multifunctional fuzzy logic circuits can be
It is advantageous when produced by C.

Furthermore, in this invention, since input circuits for generating input currents in two different directions are provided for two types of input currents, input currents in the directions required by a plurality of different fuzzy logic circuits can be generated from these fuzzy logic circuits. It becomes possible to apply it to a logic circuit.

Further, in the present invention, since an input circuit for a current having a value of 1 is provided in fuzzy logic, a fuzzy logic circuit using a value of 1 can also be included.

MOS FE single output or multi-output current mirror
When configured with T, it is possible to always keep the Mira constant at 1, allowing accurate fuzzy logic operations and speeding up the operations.

Description of Embodiments 1) Current input/output mode in fuzzy logic circuit In the present invention, the fuzzy logic circuit operates in current mode. Therefore, the current input/output format will be briefly explained. In FIG. 1, the input current of the fuzzy logic circuit (10) is represented by li, and the output m current is represented by IO. (A) shows an input/output configuration in which the input current [i flows into the circuit (10) and the output current IO flows out from the circuit (10). These are called suction input and discharge output. In (B), the input current li is the circuit (10
), and the output current ■0 flows into the circuit (10). Similarly, (C) is the suction input and suction output, and (D
) indicate the discharge input and discharge output, respectively. When connecting fuzzy logic circuits in multiple stages (cascade), it is preferable to adopt the configuration shown in Figure 1 (A> or (B). Figure 1 is an example of one manual operation and one output.
Even in multi-input and multi-output circuits, the input/output form of current remains the same.

2) Basic operations of fuzzy logic A fuzzy set X is characterized by a membership function μX. The membership function represents the degree to which the variable belongs to the fuzzy set X, and this degree is a continuous value in the interval from O to 1 (0, 1).
is expressed by Therefore, it can be said that the membership function converts the variable into (0, 1). The fuzzy set Y is also characterized by the membership function μy.6 Fuzzy logic expresses ambiguity in the form of a fuzzy set, and uses this to
It is an extension of ordinary logic to handle ambiguity. The basic operations of fuzzy logic include marginal difference, logical product, marginal use, marginal product, logical sum, logical product, absolute difference, implication, and equality. As will become clear later, these nine basic operations can be expressed by marginal differences and arithmetic sums. This means that the minimum units of basic operations in fuzzy logic are the marginal difference and the arithmetic sum.

One of the advantages of circuits operating in current mode is that the arithmetic sum (
(arithmetic difference) can also be realized with wired OR.

Below, a circuit for performing the above-mentioned nine types of basic operations will be described first, and then embodiments of the present invention will be described. The circuit that executes fuzzy logic basic operations is basically a P-channel MO8 type FET (field effect transistor) (P-
MOSFET), and adopts a current input/output configuration with source input and sink output.

However, fuzzy logic circuits use not only P-MOSFETs but also N-channel MO8 type FETs (N-MOSFETs).
FET>, it can also be realized by a complementary MO8 (C-MOS) FET.

3) Limit difference circuit The limit difference for the fuzzy sets X and Y is defined by their membership functions μ× and μy as follows.

XθYoμX87 3 μ×θμy = OV (μX − μy) ... (1) Here, θ is the limit difference, ■ is the logical sum (Wa difference) respectively. Since negative values are not used in fuzzy logic, when (μX−μy) becomes a negative value in equation (1), the limit difference becomes O due to the logical sum V. That is, Equation (1) specifically expresses the following relationship.

...(2) A limit difference circuit is shown in Fig. 2. The limit difference circuit is P
-Current mirror (1) composed of MOS FETs
, wire FOR, diode (2), two current sources (
3) (4) and one output terminal (5). Current mirror (1) is equivalent to a current mirror consisting of two P-MOS FETs. In Figure 4, (A> is the second
The current mirror (1) in the figure, (B) is the two P-M
Current mirrors consisting of OS FETs (11) and (12) are shown, respectively.

In FIG. 4(B), two FETs (11) (12)
The source (S) of is grounded. Further, these gates (G) are connected to each other, and these gates (G) are connected to the drain (D) of one FET (11). When a source input current 1i is applied to the drain (D) of one FET (11), a source output current IO becomes 1i-1o from the drain (D) of the other FET (11).
is obtained. This is because the gate voltage (gate/source voltage) is applied so that the drain current of FET (11) is equal to li, and this gate voltage is
This is because the drain current of FET (12) also becomes equal to li due to the effect on ET (12>).
Structure of T(11) (12) and 3i −8i 0
The condition is that the physical properties of the two interfaces are equal. No current flows through the short circuit between the gate (G) and the drain (D) of one FET (11).

If the structures of the two FETs and the physical properties of the Si-8i 02 interface are the same, the input current is 1 regardless of the magnitude of the input current.
The ability to obtain an output current io equal to 1 is a major feature of current mirrors using FETs. In a current mirror using a bipolar element, for example an ordinary junction transistor, 1i=I only when the current amplification factor β is very large.
O holds true. When the input current ■i is small, the current amplification factor β also becomes small, so the above equation no longer holds true. The current mirror shown in FIG. 4(B) will be expressed by the symbol "A>" in FIG. 4 below.

Returning to Figure 2, the input drain (
It will be clear from the above explanation that if a current source (4) with a discharge current H is connected to the gate), a discharge current of the same value 1y will be obtained in the output train. This output drain has rIi of discharge current
The i source (3) is connected to the output terminal (5) via a diode (2) whose direction is opposite to the direction in which the current mirror discharges. Since the current source (3) draws a current with a value of ■×, Iz −l only when lx>ly
The output current of x −fy is transferred from the terminal (5) to the diode (2
> will be sucked in through. When lx≦ly, the output current of IV-IX is about to be discharged, but
Since it is blocked by the diode (2), the terminal (5)
The output current flowing through becomes zero.

The above relationships can be summarized as follows.

...(3) Membership functions μX and μy are respectively input current ix
, Iy and the limit difference μ) 17 are made to correspond to the output current Iz, the equation (3) expresses exactly the same relationship as the equation (2). It will be understood that the circuit shown in FIG. 2 is a basic calculation circuit for limit differences.

FIG. 3 shows the relationship between the other input current lx and the output current ■z when one of the input currents It/ is used as a parameter. Here, both the person and the output current are normalized so that the maximum value is 1.

FIG. 5 shows an example of the structure of an IC (integrated circuit) when the limit difference circuit shown in FIG. 2 is realized by an IC (integrated circuit). (Δ) is a planar pattern diagram, (B) is a sectional view taken along line bb, and (C) is a sectional view taken along line C-C, all of which are shown schematically. Also, the substrate (
2nd gate) is omitted. This circuit can be fabricated on an n-type substrate (30) by a normal P-MO8 manufacturing process.

The A/(conductor) pattern (61) which becomes the source in the current mirror (1) is in ohmic contact with the n-region (41). The AI pattern (62) that becomes the drain on the input side is p-region F! IC (42) is connected. The AI pattern (63) that becomes the train on the output side is also in the n area (43
)It is connected to the.

The two FETs are manufactured to have the same channel width, channel length, and gate oxide film thickness. Polycrystalline Si (B-doped, p-type) (5
0) is provided via a 5tOz insulating film (51). This polycrystalline 3i (50) is connected to the Δl pattern (62), but the AI pattern (63) is St 02
(51). n area (44)
and the n-region (45) constitute a diode (2).

A/N area (45) where pattern (63) is on the cathode side
) Stretched out to the top, this n territory t1! (45). AI pattern (6) connected to output terminal (5)
4) is connected to the n area (44).

FIG. 6 shows a limit difference circuit made up of N-MOS FETs. It has a current input/output format of sink input and source output.

Two drains are also provided, one connected to the gate and the other connected to the output side.

Source is grounded. The diode (2) is of course opposite in orientation to that shown in FIG. It goes without saying that the calculation of equation (3) can be achieved in such a circuit as well.

In FIG. 6, the current sources are replaced by input terminals (3) and (4), but the same approach is adopted for the sake of simplicity in the various circuits described below.

4) Logical Complement For the fuzzy set Y, the logical complement is defined as follows using its membership function μy, and can be expressed using the marginal difference.

Y-Iy 31-μy -1eμ■ ... (4
) Comparing equation (1) or equation (2) with equation (4), it will be seen that the logical product is defined as μx−i at the limit difference.

Therefore, as shown in FIG. 7, the AND circuit may be set to Ix=1 in FIG. 2. That is, as the input current source (3), one that generates an input current of 1 1 li (maximum value) may be used.

In this case, the diode (2) can be omitted since the current flowing out from the output drain (equal to fy) cannot be greater than the input current 1 at the terminal (3). FIG. 8 shows the relationship between the input current 1y used in the AND operation and the output current lz.

5) For the limit fuzzy sets X and Y, the limit is defined by their membership functions μX and μy as follows.

X■Y ratioμx8y =μ×■μy 31△(μ×10μy) River (5) Here, ■ is for limit, △ is logical product (n+in) (
(choose the smaller one) and shi represent arithmetic sums, respectively. In fuzzy logic, values exceeding 1 are not used, so if (μ×+μy) exceeds 1, the limit value becomes 1 due to the logical product Δ.

That is, Equation (5) specifically expresses the following relationship.

... (6) The limit value of equation (5) can be expressed as the following equation.

1△(μχ1μy) -1θ (1θ (μ×10 μy)) ...(7) Equation (7) can be proven as follows.

1θ (1e (μX 10 μy)) 31θ (1θ (x + y)) -OV (1-(1θ(x + y) ) ) -OV
(1-(OV(1-x-y)))-OV(
(1-0)Δ (1-(1-X-1))) -OV (1Δ(x + y)) -1Δ(x + y) 31Δ(μX 10μy) ...(8) No. (7)
As can be seen from the formula, the limit value can be obtained by one arithmetic sum operation and two limit difference operations. This shows that the marginal sum circuit can be realized by one wired OR and two marginal difference circuits.

FIG. 9 shows a marginal sum circuit. Input terminals (3) (4
) is the arithmetic sum of the source input currents Ix and Iy 1a = 1x+
ry is calculated by wired OR, and this current 1a
becomes the input to the first stage limit difference circuit. Another input terminal (6) of this limit difference circuit is supplied with a source input current having a value of 1. Therefore, the sink output current Ib of the first stage limit difference circuit is given by the following equation.

... (9) This output side 1b becomes the input of the second stage limit difference circuit.

This limit difference circuit consists of a current mirror (21) and a diode (
22), and an input current having a value of 1 is applied to the other input terminal. The sink output current ■Z of the output terminal (25) of the second stage limit difference circuit is given by the following equation.

(10) Equation <10) corresponds to Equation (6), and it can be understood that the marginal sum calculation is executed by the circuit shown in FIG. The circuit shown in FIG. 9 can also be easily integrated into an IC by applying the IC pattern shown in the fifth factor to two stages.

The current flowing out from the output drains of current mirrors (1) and (21) (equal to la and lb, respectively) can never be larger than the input current 1 of terminal <6 (23), respectively. It is possible to omit the diodes (2) (22). This is convenient for converting the circuit into an IC.

6) Marginal score For fuzzy sets X, Y, the marginal score is defined by their membership functions μX, μy as follows,
and can be expressed using a marginal difference.

X■Y9μ8゜7 30V (μχ10μy−1) −(μ × −to μy) θ 1
... (11) Here ■ represents the marginal score. According to the definition of marginal score in formula (11), marginal score is:
This means subtracting 1 from the arithmetic sum of the membership functions μ× and μy, and selecting the larger of this subtraction result and 00. Specifically, this shows the following relationship.

...(12) On the other hand, Equation (11) shows that the calculation of the marginal score is performed by an arithmetic sum and a marginal difference. The marginal product circuit is the 10th
As shown in the figure. In this figure, the current mirror (1)
A source input current having a value of 1 is supplied to the gate side input terminal (6) of the circuit. Further, the sum of two input currents 1x and 1y is calculated by a wired OR circuit, and this sum current is input to the output side drain of the current mirror (1). Therefore, the output current 1z of this circuit is given by the following equation.

...(13) Since the equation (13) corresponds to the equation (12), the first
It is clear that the marginal result is calculated by the circuit shown in FIG. The marginal product circuit of FIG. 10 can be easily integrated into an IC by providing another A/pattern (65) connected to the A/pattern (63) in FIG. 5(A).

7) Disjunction For fuzzy sets X and Y, disjunction is defined by their membership functions μX and μy as follows.

XUY4hμ9. J.

3μ×Vμy...(14) Logical sum V
means selecting the larger of μX and μy, so Equation (14) can be rewritten as follows.

...(15) Equation (14) can be transformed as follows.

μxVμV-(μXθμy)+μy −(μyθμ×) 10μ× ...(16) Equation (16) is proven as follows.

(μXθμy) 10μy3(X (9') +Y-[O
V (x − y), ) ]+y= (
y + O) V (y + (x - y
))=y×3μyVμX (17) From equation (16), it can be seen that the logical sum operation can be realized by a limit difference circuit and a wired OR. FIG. 11 shows an OR circuit.

In this figure, the output current 1a of the limit difference circuit is given by the following equation.

(18) Current Iy is supplied to the input terminal (6), and currents Ia and Iy are added by wired OR. The final output current iz is given by z-la + ly, so Iz is as follows.

(19) It can be seen that a logical sum operation is performed by making the equation (19) correspond to the equation (15).

The IC circuit for the OR circuit is a Δl pattern (64) connected to the A/pattern (64) in FIG. 5(A).
6) should be added.

Note that, as shown in FIG. 11, the OR circuit requires two current sources for one input current (Iy in FIG. 11). In addition, in Fig. 11, the input current)
It goes without saying that the same result can be obtained by exchanging and [1.

8) Conjunction For fuzzy sets X, Y, the conjunction is defined by their membership functions μ×, μy as follows.

X/'IYψμX/Iy 3 μ× to μy ... (20) Logical product △
means selecting the smaller of μX and μy, so equation (20) can be rewritten as follows.

...(21) Equation (20) can be transformed as follows.

μX1ly −μ×θ(μ×θμy)−μye(μ
yθμ×) (22) Equation (22) is proven as follows.

μ×θ(μ×θμy)3×θ(Xθy)=OV [x
−(x θy)]=OV [x−[OV (
x −y ) ] ] = OV [(x −
0) △ (x − (x − Y) ) ]=
OV (x Δy ) −X Δy 3 μ× μy ...(23rd (2
From equation 2), it can be seen that the logical product operation can be realized by two marginal difference circuits. FIG. 12 shows an AND circuit. In this figure, the output current ■a of the first stage limit difference circuit is given by the following equation.

...(24) This current [a becomes one input current of the second stage limit difference circuit, and the other input current (lx is given as the terminal (23). Therefore, this second stage The output current 1z of the limit difference circuit is calculated using the following formula % Formula % By making formula (25) correspond to formula 21),
It will be understood that a logical AND operation is performed.

Since it is impossible for current to flow into the gate of the current mirror (21) in the subsequent limit difference circuit, the diode (2) can be omitted.

FIG. 13 shows a structure when the AND circuit of FIG. 12 is integrated into an IC. In Figure 12, diode (2)
This diode is omitted in FIG. 13 because it can be omitted. Also, in the first stage limit difference circuit (
Regarding the IC pattern of the current mirror (1), please refer to the fifth
The same reference numerals as the corresponding parts in Figure (A) are given. The cross section along the line bb and the cross section along the line C-C are shown in Figure 5 (
B) Same as shown in (C). and,
The dd-line cross section is a part of the cross-sectional view shown in FIG. 5(B) (
This is the same as FIG. 17(B), which will be described later. The first stage current mirror is connected to the second stage current mirror by a Δl pattern (63). From the correspondence with FIG. 5, it can be easily understood that the IC pattern shown in FIG. 13 constitutes the circuit shown in FIG. 12.

The IC pattern of the marginal sum circuit in FIG. 9 is realized by adding the A/pattern (67) connected to the AI pattern (62) in FIG. 13.

9) Absolute Difference For fuzzy sets X, Y, the absolute difference is defined by their membership functions μX, μy as follows.

IX-Yleμ屹71 31μ×−μy1 ...(26) Equation (26) can be transformed as follows.

μm, -χ1 - (μXθμy) + (μyθμ×)...
・(27) Equation (27) is proven as follows.

(μ×θμy) Ten (μyθμ×) Three (×θy) + (yθX) −(xθy)+[0V(y−x)] −[(Xθy)+O]V[(x θy>+(y −y
, )] - [[0V(x-y)]10]V [[OV (x-y)] + (y-x)
] = [(0+0) V (0+x −y )
] V[(y −x +O) V (x −y +y
-X )]-0V(x-y)V(y-X)VO-(X-V)V(Y-x)three(
μX-μy)V(μy-μ×)...(28)th (21st
) shows that the calculation of the absolute difference can be realized by two marginal difference circuits and one wired OR. FIG. 14 shows an absolute difference circuit. In this figure, the output current 1a of one limit difference circuit including a current mirror (1) and a diode (2) is given by the following equation.

...(29) In the other limit difference circuit including the current mirror (21) and the diode (22), its input currents 1× and Iy are exchanged with the input current of the one limit difference circuit. Therefore, the output current 1b is given by the following equation.

(30) Since the output current 7 of the absolute difference circuit is the arithmetic sum of the output currents 1a and lb, it is as follows.

IZ=Ia+[b... (31) By making equation (31) correspond to equation <26>,
It will be understood that an absolute difference operation is being performed.

FIG. 15 shows a structure in which the absolute difference circuit of FIG. 14 is integrated into an IC. Since the two diodes (2) and (22) cannot be omitted, the IC circuit of FIG.
Two limit difference IC circuits shown in FIG. 5 are arranged side by side, and the A/pattern (64) connected to the anode of the diode (2>(22)) is connected to each other to lead one output. The bb line cross section and the C-C line cross section are the same as those shown in FIG. 5, (B) and (C), respectively.

10) Implications For fuzzy sets X, Y, implication is defined by their membership functions μX, μy as follows.

X-+Y*ttx,.

31Δ(1−μ×10μy) (32) μX represents the degree of belonging to the set X, and (1−μX) represents the degree of not belonging to the set X. Also, the smaller of the logical products Δ is selected. Considering the above, implication represents the arithmetic sum of the degree of not belonging to set X and the degree of belonging to set Y, and if this arithmetic sum is greater than 1, the result is set to 1. It means. Equation (32) can be expressed more clearly as follows.

1Δ(1−μ×10μ■) (33) Furthermore, equation (32) can be transformed as follows.

1 Δ ku 1- μX 10 μy )-1θ(μ×e
μy) ... (34) Equation (34) is proven as follows.

Ie(μ×eμy)31θ(x ey )−OV [1
-(X eV) ] -OV [1-[OV (x - y) ]] CoOV
[(1-0)△(1-(x-y))]-OV [1
△(1-x 10y)] = 1△(1-x+y) 31△(1-μ×10μy) - (35)th (
From equation 34), it can be seen that the implication operation can be realized by two limit difference circuits. FIG. 16 shows the implication circuit. In this figure, the output current of the first stage limit difference circuit 1
a is given by the following equation.

(36) This current 1a becomes one input current of the second-stage limit difference circuit, and a current with a value of 1 is given as the other input Ti current (terminal (23)). Therefore, the output current IZ of this second stage limit difference circuit is given by the following equation.

...(37) By making equation (37) correspond to equation (33),
It will be understood that an operation of implication is being performed.

In FIG. 16, the diode (2) can be omitted for the same reason as in the AND circuit (FIG. 12). In addition, the current (equal to Ia) flowing out from the output side drain of the second stage current mirror (21) flows from the terminal (23
Since the input current of ) cannot be greater than 1, the diode (22〉) can also be omitted. Therefore, when converting the implication circuit of Fig. 16 into an IC, the input current of Fig. 17 ( As shown in △), diode (2) (
22) is not necessary.

The cross section taken along the line bb in FIG. 17 (A>) is shown in the same figure (B). The cross section taken along the line C-C is the same as that shown in FIG. 5 (C).

11) For peer fuzzy sets X, Y, equality is defined by their membership functions μX, μy as follows.

X→Y clause μX white − 3μ to μa □ ...(38) Since it is expressed by the smaller of xλ→y, using the above definition of implication (Equation 33), it can also be expressed as follows.

...(39) Equation (39) can be modified as follows.

μX Cy −1θ (μ× θμy) + (μy θμx
))...(40) Equation (40) is proven as follows.

XgY 3 (X-Y) △ (Y-X) 1x-yl -1-1x-yl -1-1XθV) + (Vθ×)) -1θ ((x ey ) + (yθX))... (4
1) From equation (40), it can be seen that equal calculation can be realized by three marginal difference circuits and one wired OR. FIG. 18 shows an equivalent circuit. Current mirror (1)
A first limit difference circuit including a current mirror (21) and a second limit difference circuit including a current mirror (21) are connected in parallel. These two marginal difference circuits connected in parallel are the above-mentioned absolute difference circuits. Therefore, the output current 1c can be expressed as follows by referring to equation (31).

...(42) The limit difference circuit of the third formula is composed of a current mirror (31) and a diode (32), the input current of one of which is the above output current 1c, and the input tube yt of the other one is a value of 1. The current is Therefore, the output current 1z of this third limit difference circuit is given by the following equation.

(43) It will be seen that an equivalent operation is performed by making the equation (43) correspond to the equation (39).

In equation (43), in the case of 1x-Iy, (lx-
1y )-(Iy-IX)=O, so Iz-1
It is. That is, when the two input currents Ix and Iy are equal, the output current Ix takes a value of 1, and in other cases, lz≠1. Therefore, if we focus only on whether the output current 7 is 1 or not, the equivalent circuit can be considered to be a matching circuit.

As can be seen from equation (42), the current 1c represents the difference between ■× and IV. If Ix=ry, it is IC-0. Also, in the current mirror (31), the short circuit (3
If 4) is left open, this element becomes just one FET.
becomes. This FET is turned off only in case of IC-0. If the FET is off, a source current with a value of 1 is given to the input terminal 33), so Iz=1. F
When ET is on, IC+O), input terminal (33)
Since the source input current of flows from the FET, Iz
-0. It will be understood that the circuit of FIG. 18 becomes a binary output coincidence circuit when the short circuit (34) is opened.

Also, the current (equal to IC) flowing out from the output side drain of the current mirror (31) is the input current 1 of the terminal (33).
Since it cannot be larger than the diode (
32) can be omitted.

FIG. 19 shows a planar pattern when the circuit of FIG. 18 is integrated into an IC. In the equivalent circuit, although the diode (32) can be omitted as described above, the diodes (2) and (22) cannot be omitted. For this purpose, two limit difference circuits consisting of a current mirror and a diode and another current mirror are provided on the IC substrate. The bb line cross section and the C-C line cross section are the same as those shown in FIGS. 5(B) and 5(C).

12) Current distribution circuit In the limit sum circuit (Figure 9), two current sources with a value of 1 are required. Similarly, in the OR circuit (Fig. 11), the AND circuit (Fig. 12), the absolute difference circuit (Fig. 14), and the equal circuit (Fig. 18), the current source of the input current Ix or Iy is Two are required. In this way, when currents of the same value and in the same direction are required, a current distribution circuit may be used. A current distribution circuit can be easily created by extending the current mirror concept. That is, the current mirror shown in FIG.
As can be seen from the IC in the figure, two drains, a common source, and a common gate are provided on the substrate, and one drain is connected to the gate. If three or more trains are installed on the board and one of them is connected to the gate (multi-output current mirror), it will pass a current equal to the gate current (input drain current) to the other two or more drains. can be obtained at the same time from Such a multi-output current mirror can be expressed as shown in FIG. Second
Figure 0 shows an example of 4 outputs.

Figure 21 shows an example in which the current distribution circuit is applied to an OR circuit (Figure 11). In the OR circuit, two terminals (4) +15 and (6) are connected to 1i current Iy (discharge input). You have to input a small number of terminals (7).
3), the source input current Iy is converted into a sink input current IV by a current mirror (72). By using a multi-output commercial mirror (71) which inputs this sinking input current 1y, two outputting input currents 1y are generated. Multi-output current mirror (71) is N-MOS
It is composed of FETs.

13) Multi-output circuit A multi-output current mirror can also be applied when it is necessary to obtain a large number of outputs with the same value. FIG. 22 shows the current mirror (72) and the multi-output current mirror (72) described above.
71) (however, the number of output terminals is different) is applied to a limit difference circuit (Fig. 2). Four sink output currents I Z from one sink output current 1z
You can see that /J< is obtained. Current mirror <
11> and (72) generates a plurality of output currents having the same value and direction as the input current, and is therefore essentially a current distribution circuit.

However, a circuit that creates multiple output currents in the same direction as the input current is called a current distribution circuit, and a circuit that creates multiple output currents in the opposite direction to the input current is called a multi-output circuit (multi-output ° commercial mirror). So it is difficult to distinguish between these.

14) Multi-output limit difference circuit By further expanding the multi-output circuit, it is possible to construct a multi-output limit difference circuit as shown in FIG. One input side of a wired OR is connected to each output drain of a multi-output current mirror (80) (for simplicity, four outputs are assumed). The other input side of this wired OR is connected to the panono ends (91) to (94), respectively, and the output side is connected to the diode (
81) to (84> respectively to output terminals (101)
~(104). Input terminal (91) ~ (
The input currents of the terminals (94) are respectively IX+ to l x t, and the output currents of the output terminals (101) to (104) are respectively IZ+ to IZ+124. Then, the following output current is obtained corresponding to equation (3).

However, n −1 to 4 (44) The circuit shown in FIG. 23 achieves four types of limit difference calculations at once. This shows that when one membership function μy is constant and the other membership function μ×n is a variable, it is possible to perform the calculation of μxnθy for many values μxn at once, and the calculation This means that the speed can be increased and temporal scanning of μxn can be omitted.

In addition, IX+ = IX2-IX3 ``IX'< =I×
If so, the circuit of FIG. 23 becomes equivalent to the circuit of FIG. 22.

FIG. 24 shows a problem caused when the multi-output limit difference circuit of FIG. 23 is integrated into an IC.

(A) is a planar pattern, and (B), (C), and (D) are cross-sectional views taken along the bb line, CC line, and dd line of (Δ), respectively. A comb-shaped n region (110) is formed on the n-type substrate (30) when viewed from above.
The source of the multi-output current mirror (80) is created by the ohmic contact of the A/pattern (146) to Five other n regions (111) to (115) are formed so as to face each other with a certain interval between them. The width and length of the channels formed between them are set equal.
Polycrystal 5i (5
0) is provided. An A/pattern (145) serving as an input side drain is connected to this polycrystalline Si (50). A/Pattern (145) ICn area (
115) is in ohmic contact.

The diodes (81) to (84) each have an n-region (1
21) to (124) and zero areas (131) to (134). Above A/pattern (141)~
(144) are connected to n regions (131) to (134), respectively. AI patterns (151) to (154) connected to output terminals (101) to (104), respectively
is connected to n areas (121) to (124).

Figure 25 shows the multi-output limit difference circuit as an OR circuit (first
Figure 1) shows an example of its application.

Figure 11 shows a current mirror (1) and a diode (2).
) is replaced with a multi-output limit difference circuit shown in FIG.

Further, an input terminal (6) for supplying input current Iy is connected to the anode side of each of the diodes (81) to (84). The four input terminals (6> and (4)) can be supplied with equal values of input current IV using the °1 current distribution circuit (FIG. 20) as described above.

From each output terminal (161) to (164), the (19th)
By referring to the formula, it is easy to understand that the logical sum output given by the following formula can be obtained.

1z-1xnVIY However, ×-1 to 4...(45) The multi-output limit difference circuit uses diodes (81) to (84
) (Fig. 23) can be omitted.

15) IC circuit with limit difference circuit as a basic element As described above, the basic arithmetic circuit of fuzzy logic can be constructed by a combination of limit difference circuit and wired OR.

Therefore, by creating a logic array of limit difference circuits on the substrate in advance, it becomes possible to realize any fuzzy logic operation circuit by designing only the A/wiring pattern.

As shown in FIG. 26, an IC is prepared in which a large number of basic circuits (180) are provided on a substrate (170). On the upper surface of this IC, an insulating protective film with contact holes formed at appropriate locations is formed, and an A/il film (171), which is a conductor, is further deposited on the negative side of the insulating protective film. Instead of the insulating protective film and the A/thin film with the contact/small holes, only the insulating protective film may be formed all over the top surface of the IC. The basic circuit (180) is in principle the basic element of the limit difference circuit (ie, the limit difference circuit minus its connections). As mentioned above, the diode in front of the current mirror can be omitted, so the basic circuit (18
0), the basic element of a current mirror (a current mirror minus the wiring) may be used, or these two types of basic elements may be employed.

For example, a manufacturer manufactures such an IC semi-finished product and provides it to a user. A user creates a wiring pattern that will yield a desired fuzzy logic circuit by subjecting an IC semi-finished product to a small number of steps, about 1 to 3 steps. This allows the user to easily configure a desired fuzzy logic circuit or system.

As shown in FIG. 27, one substrate (170)
It is more preferable to provide not only the basic circuit (1ao) but also a current distribution circuit and a multi-output circuit <183) <186) on the top.

FIG. 28 shows an example of a fuzzy logic circuit connected using an IC semi-finished product provided with a current distribution circuit and a multi-output circuit as shown in FIG. 27. Input terminal (201
) (202) and (203) are given input currents 1y, lx and currents with a value of 1, respectively. substrate(
170) A multi-output circuit (185) formed above generates a number of currents 1y with a value equal to the input current y. Similarly, multi-output circuits (184) (18
3), currents each having a value equal to I× and 1 are created. A power supply voltage +v9° is applied to the terminal (204) and applied to each of the multi-output circuits (183) to (185).

A large number of limit difference circuits (18) formed on a substrate (170).
0> (181) is appropriately connected, a fuzzy logic circuit is constructed which has a certain function (this example does not have any particular meaning). The output currents of the multi-output circuits (183) to (185) are input to this fuzzy logic circuit. The output device 21iE10 of this fuzzy logic circuit appears at an output terminal (205) (not a specific terminal for wire bonding or the like, but a hypothetical one on the A/pattern for convenience).

Since this output current IO is a source output, a current mirror of the limit difference circuit (182) is used to convert it to a sink output. The diodes of the limit difference circuit (182) have no effect. The cathode side of this diode is open. Limit difference circuit (182
) is sent to a multi-output circuit (186), which provides a number of output currents 0 with the same value. This output current IO is
06) to the outside.

The multi-output circuits (183) to (18G) are P-MOS, and the limit difference circuits (180) to (182) are N-MOS.
Each is composed of: In this way, it is possible to provide many types of circuits on one board (170), or it is possible to separate them at the chain line M and provide a multi-output circuit on one board and a limit difference circuit on the other board. Of course, it is also possible to write it down.

FIG. 29 shows the part surrounded by the broken line in FIG. 28, that is, the [C structure pattern] of the multi-output circuit (183) and the limit difference circuit (181). This IC is fabricated using a polysilicon gate self-alignment P-MO8IIJ fabrication process. The substrate (170) is n-type. The multi-output circuit (183) has almost the same structure as the multi-output current mirror (symbol (80) in FIG. 24 (Δ)). However, one output side drain is made of polycrystalline Si.
The difference is that it is composed of two-layer wiring of (211) and Δl pattern (212).

The other output side drain is connected to the limit difference circuit <181> by an AI pattern (213).

A limit difference circuit (181) is provided within the n-region (220). This n area (220) is A/pattern (21
4) is grounded. n area (221) is connected to n area (220) by A/pattern (215),
It constitutes the source of the current mirror (191). other n
One of the areas (223> is A/pattern (213)
(drain), and the other (222) is connected to polycrystalline Si (230) which becomes the gate, and is also connected to the input A/pattern (216) (train). The diode (192) is composed of a 0 region and a p-type polycrystal 3i (225).

The polycrystalline 3i (225) is connected to the A/pattern (213), and the n-region (224) is connected to the output A/pattern (217).

16) Multi-Functional Fuzzy Logic Circuit Figure 30 shows a multi-functional fuzzy logic circuit formed on one substrate. This circuit is also fabricated using polysilicon gate self-alignment P-MO8 fabrication. It can be created through a process.

This circuit has 12 fuzzy logic functions.

That is, the marginal differences μxey and μyeX, the logical product μ
X and μV, marginal sum μ, marginal product meΩy μ,. 2. Disjunctive sum μ, conjunctive product μ, absolute difference in nχμ1x−yl, implication μX−,, and μ7. r1 as well as the equivalent μXd7. In FIG. 30, for the sake of clarity, the symbol μ for the membership function is directly used to represent the current instead of the symbol for the current I.

The input terminals (241) (2
42) Given in (243). In addition, above 1
The fuzzy logic operation results of 2 are output to the output terminals (25
1) to (262) are output as discharge output currents.

The current μX input from the terminal (241) is input to the N-MOS multi-output circuit (current mirror) (244),
From this circuit (244), six currents μ× of the same value and opposite direction are obtained. One of the output currents of this multi-output circuit (244) further becomes a source input to a P-MOS multi-output circuit (245), and this circuit (245)
), two currents μX having the same direction and the same value as the current input to the terminal (241) are obtained. In this way, the multi-output circuits (244) (245) output two currents μX in the same direction and the same value as the current input to the terminal (241), and five currents μX in the opposite direction and the same value. can get.

Similarly, multi-output circuit (246> (247)
As a result, one current μy having the same direction and the same value as the current input to the input terminal (242) and four current μy having the same value and opposite direction are obtained.

The current with a value of 1 given to the input terminal (243) is N-M
The direction is reversed by the O8 current mirror (248) and P
- Input to MOS multi-output circuit (249). This circuit (249) provides eight currents having the same direction and the same value 1 as the current input to the terminal (243).

Multi-output circuit <247> and wired OR (28
1) and the multi-output current mirror (271) constitute a 7" output limit difference circuit that calculates μ〆97k. In this multi-output limit difference circuit, the same value is calculated from the multi-output current mirror (271). Five currents μ70. representing the calculation results are output (discharge output). That is,
Focusing on the current input and output to the wired OR (281), if μ×>μy, a current of (μ×−μy) flows from the gate (drain connected to the gate) of the multi-output current mirror (271). It flows into the wired OR (281). When μx=lB, the current flowing from the gate of the current mirror (271) to the wired OR<281) is naturally zero. If μ×〈μy, then (μy−μ
×) current tries to flow from the wired OR (281) to the multi-output current mirror (271), but the current mirror (271) acts as a diode for the current in this direction, so in the end, the wired OR (281) ) flows into the current mirror (271). Therefore, the calculation of the marginal difference shown in equation (2) is configured. The multi-output current mirror (271) performs the dual functions of a diode and a multi-output circuit (corresponds to the diode (2) and multi-output circuit (71) in Figure 22, however, the one corresponding to the current mirror (72) is (Not present in Figure 30). One of the output currents of the multi-output current mirror (271) represents the limit difference μyrey and is sent to the output terminal (253) as a −=l ffi current. Other output currents are used for other fuzzy logic operations.

In the same way, a multi-output circuit (245), a wired OR<282> and a multi-output current mirror (272)
) constitutes a multi-output limit difference circuit that calculates limit differences μ and eo. Multi-output current mirror (27
2), five discharge output currents μyG,o are obtained, one of which is sent to the output terminal (252), and the others are used for other calculations.

Logical product μ, 4. From equation (22), μxe(μXθμy
)-μ×θμX6y.

Since the limit difference μ8°7 can be obtained from the multi-output current mirror (271), the AND operation can be performed by calculating the limit difference between μX and μxey. This operation is accomplished by a multi-output current mirror (271), a wired OR (283), and a current mirror (273) (acting like a diode). The current mirror (273) reverses the direction of the current representing the result of this calculation and sends it to the output terminal (251).

As can be seen from equation (11), the critical product μ8° is (
μX+μy) θ1. (Ilx 10μy) is calculated by wired OR<288). (μχ
The limit difference between 10μy) and 1 is the current 7 (250>
The current mirror (250) acts as a diode and reverses the direction of the output current to connect the output current to the terminal (250).
54).

Absolute difference μ1x−y− and limit difference μ, xey and μ29X
(see equation (27)), so these limit difference circuits and the soi 1 hood OR (2
85), and the calculation result is realized by the terminal (25
5) is output.

The logical product μy (can be expressed as a limit difference (1θμy), see equation (4)), and a diode is not required in this limit difference circuit. The multi-output circuit (246) and the wired OR (286) can realize an arithmetic circuit with a limit difference (1θμy), and the output current of the AND product μ7 is connected to the terminal (2
56).

Similarly, the output current of the logical product μY (output terminal (261)) is connected to the multi-output circuit (244) and the wired OR (292).
) is obtained from a limit difference circuit consisting of

The implication μ is equivalent to the limit difference (1θ μye Limit difference (1θll, ox)
The limit difference circuit that calculates the value is realized by a current mirror (276) and a wired OR (287), and its output appears at the output terminal (257). Since an N-MO8 current mirror (276) is used, the direction of the current is reversed from the circuit shown in FIG.

Similarly, the implication μ (output terminal (259)) is calculated by .

Toward equality? / can be calculated by [1θ(μ, ., 10μ, θx)] (see equation 4 (1)).Wired OR
(293) calculates (μXeχ0μχ0^). A limit difference circuit that calculates the limit difference between 1 and (uxey 1μ, θs) is constituted by a current mirror (277) and a wire A7 to a wire OR (289). In this limit difference circuit (also the diode can be omitted), the computation output of this equal appears at the output terminal (258).

The output terminal (2G(1)) is (μ, θ7
×07 10μ×) can be calculated (see equation (16))
, the OR circuit is realized by a limit difference circuit of μyfE17 and a wired OR (291).

The limit μX5)7 is expressed as follows from equations (6) and (7).

... (6) -1θ (1θ (μχ + μy)) ... (7) (μx 10μy) is calculated by wired OR (295), and this current is applied to the gate of N-MO8 current mirror (279). This is the source input to the drain (connected to the drain). One output side of the multi-output circuit (249>) is connected to this gate (wired OR (296)).
, 1 is input. Therefore, a current expressed by the following equation flows into the drain of the current mirror (279).

(No discharge current flows through the drain)...(46
) By the wired OR (294), the current mirror (27
9) drain output ffi'a (Equation (46)) is subtracted from the current having a value of 1, and this subtracted current appears at the output terminal (262) as a discharge output. Therefore, the current appearing at the output terminal (262) is given by the following equation.

...(47) Equation (47) represents the limit value.

The multifunctional fuzzy logic circuit shown in Fig. 30 is provided with many multi-output circuits (current mirrors) as described above, and utilizes the diode action of the (multi) current mirrors, so 12 The number of elements (for example, the number of drains) is reduced compared to when fuzzy logic circuits are individually created.

In Figure 30, the multi-output current mirror (250)
Both (249) are of the P-MOS type, but the number of drains is different.

If a large number of multi-output current mirrors having different numbers of trains are manufactured on the same substrate, the design becomes complicated, so it is preferable to keep the number of drains the same. By doing this, it is possible to uniformly manufacture elements in the IC board manufacturing process, and it is only necessary to consider the connection between each element when designing the wiring pattern, so the design of the IC board manufacturing process can be improved. This makes it possible to simplify the process.

FIG. 31 shows another embodiment of the multifunctional fuzzy logic circuit. This circuit has F in the circuit shown in FIG.
The EI current mirror is replaced with a bipolar junction transistor current mirror and the FET multi-output current mirror is replaced with a bipolar junction transistor multi-output current mirror. The PFi-flow mirror and the multi-output current mirror using these transistors are constituted by multi-collector transistors having two or more collectors. As described above, in a current mirror using a bipolar element, the function as a current mirror is achieved only when the current amplification factor β is extremely large.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the current input/output form, Figure 2 is a circuit diagram showing a limit difference circuit, Figure 3 is a graph showing its input/output characteristics, and Figure 4 is a circuit diagram of two equivalent current mirrors. , Figure 5 shows the structure of the limit difference circuit when it is integrated into an IC, where (A) is a planar pattern diagram, (B) is a cross-sectional diagram taken along line bb in (A), and (C) is a cross-sectional diagram taken along line bb of (A). is a cross-sectional view taken along line C-C of (A>), Figure 6 is a circuit diagram showing a limit difference circuit constructed of N-MOS FETs, Figure 7 is a circuit diagram showing an AND circuit, and Figure 8 is Graph showing its input/output characteristics, Figure 9 is a circuit diagram showing a marginal sum circuit, Figure 10 is a circuit diagram showing a marginal product circuit, Figure 11 is a circuit diagram without an OR circuit, and Figure 12 is a logic diagram. A circuit diagram showing the product circuit, Fig. 13 is a planar pattern diagram of the IC, Fig. 14 is a circuit diagram of the absolute difference circuit, Fig. 15 is a planar pattern diagram of the IC, and Fig. 16 is a circuit diagram of the implication circuit. Figure 17 shows the IC pattern, (A>
is a planar pattern diagram, (B) is a sectional view taken along line bb of (A), Figure 18 is a circuit diagram of the equivalent circuit, and Figure 19 is its I
C plane pattern diagram, Fig. 20 shows a multi-output current mirror, J circuit diagram, Fig. 21 shows a circuit diagram showing an OR circuit using a current distribution circuit, and Fig. 22 shows a limit difference circuit using a current distribution circuit. Figure 23 is a circuit diagram showing a multi-output limit difference circuit, Figure 24 shows its ICIM construction, (A) is a plan pattern diagram, (B), (C), and (D) are respectively (B-, b-line of A> is a cross-sectional view, C-C line is a cross-sectional view, dd line is a cross-sectional view, Figure 25 is a circuit showing an OR circuit using a multi-output limit difference circuit. 26 shows a fuzzy logic IC, (A> is a schematic layout configuration diagram seen from a plane, (B) is a schematic layout configuration diagram taken along the bb line of (A>), and FIG. 27 is another Fuzzy theory JIN
28 is a circuit diagram showing an example of a fuzzy logic circuit, and FIG. 29 is a part of the IC.
(A) is a partially cutaway plane pattern diagram, (B) and (C) are (A>'s b - b li
30 is a circuit diagram of a multifunctional fuzzy logic circuit according to an embodiment of the present invention, and FIG. 31 is a circuit diagram showing another example of a multifunctional fuzzy logic circuit. . (241) to (243)...input terminals, (244) to
(247) (249)...Multi output circuit (input circuit), (248)...Current mirror (input circuit), (
251) to (262)...output terminals, (271) to (
273)...multi-output current mirror, < 250)
(276) to (279)...Current mirror, (28
1) to (296)...wired OR. 4 people other than the above No. 5j Me 1 Fig. 6 Funeral 71 Fig. S xy Fig. 9 Fig. 12 Fig. 13...15141) 118N 1.・, 25i*+ jA; 261”j Fig. 27

Claims (3)

[Claims] (1) At least one of the same value and direction as the input current
It generates two currents and at least one current with the same value and opposite direction as the input current, and is configured with a single-output current mirror, a multi-output current mirror, or a combination thereof, and is configured to generate two currents with respect to two types of input currents. a single output current mirror or a multi-output current mirror of one of the input circuits of the first and second input circuits; one output current mirror of one of the input circuits of the first and second input circuits; A wired OR that calculates the difference between the output current of an output current mirror or one output current of a multi-output current mirror and one output current of the other input circuit, and a multi-output current mirror that takes the output current of this wired OR as input. a multi-output limit difference circuit comprising: a third input circuit for producing at least one current of the same value and desired direction from an input current of one value; and outputs of the first, second and third input circuits; A multifunctional fuzzy logic circuit comprising: a plurality of different fuzzy logic circuits each having at least one of its input currents as at least one of the current and the output current of the multi-output limit difference circuit. (2) A single-output current mirror or a multi-output current mirror of the other input circuit of the first and second input circuits; an output current of a single-output current mirror or a multi-output current mirror of the other input circuit; Another multi-output limit difference circuit consists of a wired OR that calculates the difference between one output current of the circuit and one output current of one input circuit, and a multi-output current mirror that takes the output current of this wired OR as input. A multifunctional fuzzy logic circuit according to claim 1, wherein the multifunctional fuzzy logic circuit is provided. (3) The multifunctional fuzzy logic circuit according to claim (1), which is formed into an IC on one substrate.