JPS6120429A - Multifunction fuzzy logical circuit - Google Patents

Abstract

PURPOSE:To obtain a multifunction fuzzy logical circuit which is used as the base of a system suitable for handling a fuzzy logic, by providing plural different fuzzy logical circuits which use at least one of output currents of the first and the second inputting circuits and an output current of a multi-output limit difference circuit, as at least one of input currents, respectively. CONSTITUTION:An input current and an output current of a fuzzy logical circuit 10 are denoted as Ii and Io, respectively. A limit difference circuit consists of a current mirror 1 constituted of a p-MOSFET, a wired OR, a diode 2, two current sources 3, 4, and one output terminal 5. The power source mirror 1 is equivalent to a current mirror consisting of two p-MOSFETs. The source S of two FETs 11, 12 is grounded. Also, their gates G are connected to each other, and also these gates G are connected to the drain D of one FET11. When the discharge input current Ii is applied to the drain D of one FET11, the discharge output current Io which becomes Ii=Io is obtained from the drain D of the other FET 12.

Description

[Detailed description of the invention] backbone of invention This invention relates to multifunctional fuzzy logic circuits.

Fuzzy logic is a logic that deals with fuzziness, or "ambiguity." Ambiguity surrounds human thoughts and actions. Therefore, if such ambiguity can be quantified or theorized, it should be possible to apply it to the design of social systems such as traffic control, emergency, and applied medical systems, as well as robots created to imitate humans. In 1965,
Ever since the concept of fuzzy sets was proposed by A. Zadeh, research on fuzzy logic has been conducted as a means of dealing with "ambiguity" from this perspective. However, at present, much of this research is directed toward application to software systems using digital computers. Digital computers perform calculations based on binary logic consisting of O and 1, and although the calculation processing is rigorous and rigorous, it is necessary to add an A/D converter circuit to input analog quantities. Therefore, when a huge amount of information is processed, there is a problem that it takes a long time to obtain the final result. Furthermore, programs for applying fuzzy logic must be extremely complex, and complex processing requires a large digital computer, which is not economical.

In the first place, fuzzy logic is a logic r that handles continuous values (0, 1) in the interval from 0 to 1, so it has the aspect that it is not compatible with digital computers based on binary logic. Furthermore, since fuzzy logic deals with wide and ambiguous quantities, calculations performed by digital computers do not require any degree of rigor. Therefore, it is desired to realize circuits and systems suitable for handling fuzzy logic.

SUMMARY OF THE INVENTION The present invention aims to provide a multifunctional fuzzy logic circuit as the basis for a system suitable for handling fuzzy logic.

The multifunctional fuzzy logic circuit according to the present invention generates at least one current having the same value and direction as the input current, and at least one current having the same value and opposite direction as the input current, and has one output. Consisting of a current mirror, a multi-output current mirror, or a combination of these,
First and second input circuits respectively provided for two types of input currents, one output current mirror or multi-output current mirror of one of the input circuits, one output current mirror of one of the input circuits; A multi-output limit consisting of a wired OR1 that calculates the difference between the output current or the output current of one of the multi-output current mirrors and the output current of one of the other input circuits, and a multi-output current mirror whose input is the output current of this wired OR. a difference circuit, and a plurality of different fuzzy logic circuits each having at least one input current of at least one of the output currents of the first and second input circuits and the output current of the multi-output limit difference circuit. It is characterized by

One output current mirror or multi-output current mirror of either other input circuit, one output current of one output current mirror or one output current of a multi-output current mirror of either other input circuit and one output of one input circuit A wired OR that calculates the difference between the current and this wired O
Preferably, another multi-output limit difference circuit is provided, consisting of a multi-output current mirror whose input is the output current of R.

Here, the same value includes values that are close enough to not cause a practical problem. If the input circuit is configured with FET, a current almost equal to the input current can be obtained, and even with bipolar transistors, the current amplification factor β
If the value is very large, there will be no practical problem.

The basic operations of fuzzy logic include marginal difference, logical complement, marginal use, marginal product, logical sum, logical product, absolute difference, implication, and equality. When the current mode is adopted as the operation mode and the limit difference circuit is configured with a current mirror, a wired OR, and a diode, the circuit that executes the calculations outside the limit difference section among the above basic calculations has one or more circuits. This can be achieved using a limit difference circuit and wired OR. That is, the plurality of different fuzzy logic circuits described above can be constructed by a limit difference circuit and a wired OR. Moreover, the diode in the limit difference circuit can be replaced with a current mirror.

In this invention, since a multi-output limit difference circuit is provided, a plurality of limit difference calculation output currents can be obtained from this circuit. Therefore, it becomes possible to use not only the limit difference circuit but also a part of several other fuzzy logic circuits with this multi-output limit difference circuit. Moreover, since the diode in this circuit is replaced by a multi-output current mirror, no diode is required. Since the circuit configuration can be simplified in this way, multifunctional fuzzy logic circuits can be integrated into ICs.
This is advantageous when manufacturing by.

Furthermore, in this invention, since the input circuits for generating input currents in two different directions are set for two types of input currents, input currents in the directions required by a plurality of different fuzzy logic circuits can be generated from these input currents. can be applied to fuzzy logic circuits.

MOS FE single output or multi-output current mirror
When configured with T, it is possible to always keep the Mira constant at 1, allowing accurate fuzzy logic operations and speeding up the operations.

Description of Embodiments 1) Current input/output mode in fuzzy logic circuit In the present invention, the fuzzy logic circuit operates in current mode. Therefore, the current input/output format will be briefly explained. In Fig. 1, the input current of the fuzzy logic circuit (10) is represented by (i), and the output current is represented by IO. (A> means that the input current 1i flows toward the circuit (10) and the output It shows the input/output form in which the current IO flows out from the circuit (10). These are named sink input and source output. (B) shows that the input current 11 flows out from the circuit (10).
), and the output current 1o flows into the circuit (10). Similarly, (C) is the suction input and suction output, and (D
) indicate the discharge input and discharge output, respectively. When connecting fuzzy logic circuits in multiple stages (cascade), it is preferable to adopt the configuration shown in FIG. 1 (A) or (B). Figure 1 is an example of one person and one output.
Even in multi-input and multi-output circuits, the input/output form of current remains the same.

2) Basic operations of fuzzy logic A fuzzy set X is characterized by a membership function μ×. The membership function represents the degree to which the variable belongs to the fuzzy set X, and this degree is a continuous value in the interval from 0 to 1 (0, 1).
is expressed by Therefore, it can be said that the membership function converts the variable into (0, 1). The fuzzy set Y is similarly characterized by a membership function μy.

Fuzzy logic expresses ambiguity in the form of fuzzy sets, and uses this to extend normal logic so that it can handle ambiguity. The basic operations of fuzzy logic include marginal difference, logical product, marginal sum, marginal product, logical sum, logical product, absolute difference, implication, and equality. As will become clear later, these nine basic operations can be expressed by marginal differences and arithmetic sums. This means that the minimum units of basic operations in fuzzy logic are the marginal difference and the arithmetic sum.

One of the advantages of circuits operating in current mode is that the arithmetic sum <
(vii technique difference) can be realized with wired OR.

Below, a circuit for performing the above-mentioned nine types of basic dances will be described first, and then embodiments of the present invention will be described. The circuit that executes fuzzy logic basic operations is basically a P-channel MO8 type FET (field effect transistor) (P-
MOSFET>, and adopts a current input/output configuration with source input and sink output.

However, fuzzy logic circuits are not limited to P-MOSFETs, but also N-channel V-channel MO3 type FETs (N-MOSFETs).
FET>, it can also be realized by a complementary MO3 (C-MOS) FET.

3) Limit difference circuit For fuzzy sets X, Y, the limit difference is defined by their membership functions μ×, μy as follows.

xeyφuμxen3μ×θμy = OV <μX −μy) ... (
1) Here, θ is the marginal difference, and ■ is the logical sum (WaX) (
(select the larger one) and - represent the arithmetic difference (n-arithmetic difference), respectively. Since negative values are not used in fuzzy logic, when (μX−μy) becomes a negative value in equation (1), the limit difference becomes O due to the logical sum V. Specifically, Equation (1) expresses the following relationship.

...(2) A limit difference circuit is shown in Fig. 2. The limit difference circuit is P
-Current mirror (1) composed of MOS FETs
, wired OR, diode (2), two current sources (
3) (4) and one output terminal (5). Current mirror (1) is equivalent to a current mirror consisting of two P-MOS FETs. In Figure 4, (A) is the second
The current mirror (1) in the figure, (B) is the two P-M
Current mirrors consisting of OS FETs (11) and (12) are shown, respectively.

In FIG. 4(B), two FE-r(11)(12
) source (S) is grounded. Also, these gates (G) are connected to each other, and these gates (G)
is connected to the drain (D) of one FET (11). When a source input current 1i is applied to the drain (D) of one FET (11), a source output current I from the drain (D) of the other FET (11) becomes [1-1o.
O is obtained. This is because the gate voltage (voltage between Go 1 and So 2) is applied so that the drain m current of FET (FEllll) is equal to 11, and this gate voltage also acts on the other FET (12), causing the FET This is because the drain current in (12) also becomes equal to li. However, the structure of two FETs (11) (12) and st - st
o□The condition is that the interface physical properties are the same. Gate (G
) and the drain (D) of one FET (11).

If the structures of the two FETs and the physical properties of the 3i - 8i 02 interface are the same, the input current is 1 regardless of the magnitude of the input current.
The ability to obtain an output current IO equal to 1 is a major feature of current mirrors using FETs. In a current mirror using a bipolar element, for example a normal junction transistor, li −
■0 is established. When the input current 1i is small, the current amplification factor β also becomes small, so the above equation does not hold.

The current mirror shown in FIG. 4(B) will be expressed by the symbol "A>" in FIG. 4 below.

Returning to Figure 2, the input drain (
It will be clear from the above explanation that if a current source (4) with a discharge current IV is connected to the gate), a discharge current of filly equal to this will be obtained in its output train. This output drain is connected to a current source (3) with a discharge angle of 1× and an output terminal (5) via a diode (2) whose direction is opposite to the discharge direction of the current mirror. Since a current in the range of 1x is drawn by the current source (3), Iz-1x only when 1x>Iy
-[y output current will be sunk from terminal (5) through diode (2). When IX≦[y, an output current of Iy-1x is about to be discharged, but it is blocked by the diode (2), so the output ll current flowing to the terminal (5) becomes zero.

The above relationships can be summarized as follows.

...(3) Input membership functions μ× and μy respectively 11*I
If x, 1y and the limit difference μX97 are made to correspond to the output current Iz, then equation (3) expresses exactly the same relationship as equation (2). It will be understood that the circuit shown in FIG. 2 is a basic calculation circuit for limit differences.

FIG. 3 shows the relationship between the other input current lx and the output meter 11 when one of the input currents 1y is used as a parameter. Here, both the person and the output current are normalized so that the maximum value is 1.

FIG. 5 shows an example of the structure of an IC (integrated circuit) in which the limit difference circuit shown in FIG. 2 is implemented by an IC (integrated circuit). (A> is a plan pattern diagram, (B) is a cross-sectional view taken along line bb, and (C) is a cross-sectional view taken along line C-C. All are shown schematically. (second gate) is omitted.This circuit is based on an n-type substrate (
30) above can be fabricated by a conventional 1)-MOS manufacturing process.

The AI (conductor) pattern (61) which becomes the source passing through the current mirror (1) is in ohmic contact with the n-region (41). The A/pattern (62) which becomes the drain on the input side is connected to the n region (42). The A/pattern (63) serving as a train on the output side is also connected to the p region 14 (43).

The channels [1], channel lengths, and gate oxide film thicknesses of the two FETs are manufactured to be equal to each other. n
Polycrystalline Si (B-doped, p-type) that will serve as the gate is placed between regions (41), (42), and (43).
(50) is connected through the SiO2 insulating film (51). This polycrystalline 3i (50) is A/pattern (6
2>, but A/pattern (63) is connected to S
It is insulated via i 02 (51). A diode (2) is configured by the n region (44) and the n region (45).

A/N area (45) where pattern (63) is on the cathode side
) Stretched out to the top, this n territory 11! (45) is connected. The AI pattern black 4) connected to the output terminal (5) is connected to the pfl area (44).

FIG. 6 shows a limit difference circuit made up of N-MOS FETs. It has a current input/output configuration with a suction input horn and a discharge output.

Two drains are also provided, one connected to the gate and the other connected to the output side.

Source is grounded. As a matter of course, the direction of the diode (2) is opposite to that shown in FIG. 2. It goes without saying that the operation of equation (3) can also be achieved in such a circuit.

In FIG. 6, the current sources are replaced by input terminals (3) and (4), but the same approach is adopted for the sake of simplicity in the various circuits described below.

4> Logical Complement For the fuzzy set Y, the logical complement is defined as follows using its membership function μy, and can be expressed using the marginal difference.

Y-μ■ 31-μy = 1θμy ... (4) No. (1)
If we compare the equation or equation (2) with this equation (4), we get
It will be seen that the logical complement is with μx =1 at the marginal difference.

Therefore, as shown in FIG. 7, the logic auxiliary circuit may be set to f×-1 in FIG. 2. That is, as the input current source (3), one that generates an input current having a value of 1 (maximum value) may be used.

In this case, the current flowing out from the output side drain (equal to Iy) is thicker than the input current 1 at terminal (3) (this cannot happen, so it is possible to omit diode (2). Fig. 8 shows the relationship between the input current 1y and the output tube flow IZ in the logical complementary operation.

5) For the limit fuzzy sets X and Y, the limit is defined by their membership functions μX and μy as follows.

X■YμxGy -μ×■μy 31△ (μX 10μy) ... (5) Here, ■ is for limit, △ is logical product (min) (select the smaller one), and 10 is arithmetic Each represents the sum. In fuzzy logic, values exceeding 1 are not used, so (μ×10μy
) exceeds 1, the limit value becomes 1 due to the logical product △.

That is, Equation (5) specifically expresses the following relationship.

... (6) The limit value of equation (5) can be expressed as the following equation.

1△(μχ1μy) -1θ (1θ(μχ+μy)) ...(7) Equation (7) can be proven as follows.

1θ (1θ (μχ 10 μy)) 3 1θ (1θ (×→−y)
)=OV(1-(1θ(x+y)))=OV(1
-(OV(1-x-y)))=OV((1-0)△(1-(1-x-y))) =OV(1△(x y)) =1△(X +V ) 31△(μχ1μy) ...(8) No. (7)
As can be seen from the equation, the limit value can be obtained by performing one arithmetic sum mm and two limit difference calculations. This shows that the marginal sum circuit can be realized by one wired OR and two marginal difference circuits.

FIG. 9 shows a marginal sum circuit. Input terminals (3) (4
) is the arithmetic sum of the source input currents Ix and Iy 1a-1x+
]V is calculated by wired OR, and this current 1a
becomes the input to the first stage limit difference circuit. The other input terminal (6) of this limit difference circuit is supplied with a 111 input current having a value of 1. Therefore, the sink output current 1b of the first stage limit difference circuit is given by the following equation.

(9) This output current 1b becomes an input to the second stage limit difference circuit. This limit difference circuit consists of a current mirror (21) and a diode (22), and the other input terminal is supplied with an input current having a value of 1. The sink output current 1z of the output terminal (25) of the second stage limit difference circuit is given by the following equation.

...(10) It will be understood that equation (10) corresponds to equation (6), and the limit calculation is executed by the circuit shown in FIG. The circuit shown in FIG. 9 can also be easily integrated into an IC by providing the IC pattern shown in FIG. 5 in two stages.

Although the current flowing out of the output drains of current mirrors (1) and (21) (equal to la and lb, respectively) cannot be greater than the input current 1 of terminal (6) <23>, respectively, Diode (2>(22)
can be omitted. This means that the circuit's IC
It is convenient for development.

6) Marginal product For fuzzy sets X, Y, the marginal product is defined by their membership functions μ×, μy as follows,
and can be expressed using a marginal difference.

X○Y@μ, Machi 30 (μ×+μy−1) ・−(μχ1μy) θ1 (11) Here, 0 represents the marginal product. According to the definition of the marginal product in equation (11), the marginal product is the membership function μX and μ
This means subtracting 1 from the arithmetic sum with y and selecting the larger of this subtraction result and O. Specifically, this shows the following relationship.

...(12) On the other hand, Equation (11) shows that the calculation of the marginal product is performed by an arithmetic sum and a marginal difference. The marginal product circuit is the 10th
As shown in the figure. In this figure, the current mirror (1)
A source input current having a value of 1 is supplied to the gate side input terminal (6) of the circuit. ζ, the two input currents [X
The sum of Iy and Iy is calculated by a wired OR circuit, and this sum current becomes the input point of the output side drain of the current mirror (1). Therefore, the output current [2 of this circuit is given by the following equation.

...(13) Since equation (13) corresponds to equation (12), the first
It is clear that the marginal product is calculated by the circuit shown in FIG. The marginal product circuit of FIG. 10 can be easily integrated into an IC by providing another A/pattern (65) connected to the A/pattern (63) in FIG. 5 (A>).

7) Disjunction For fuzzy sets X and Y, disjunction is defined by their membership functions μX and μy as follows.

XUYsuμxuy 3μ×Vμy ... (14) Logical sum ■
means selecting the larger of μX and μy, so equation (14) can be rewritten as follows.

...(15) Equation (14) can be transformed as follows.

μ×vμV=(μ×θμy)+μy −(μyθμ×) 10μ× ...(16) Equation (16) is proven as follows.

(μ×θμy) 10μy3(XθY)−1−[OV (x
−y ) > 1 +y−(y +0) V (y
10(x-y)y Vx 3μyVμ× (17) From equation (16), it can be seen that the logical sum operation can be realized by the marginal difference circuit and the wired OR. FIG. 11 shows an OR circuit.

In this figure, the output current 1a of the limit difference circuit is given by the following equation.

...(18) Current 1y is supplied to input terminal (6), and current 1a is generated by wired OR! '/ is added. and,
Since the final output current Iz is given by l7-1a+ly, 12 is as follows.

(19) It can be seen that a logical sum operation is performed by making the equation (19) correspond to the equation (15).

The IC circuit for the OR circuit is an AI pattern (64) connected to an AI pattern (64) in FIG.
6) should be added.

As shown in FIG. 11, the OR circuit requires two current sources for one input current (Iy in FIG. 11). In addition, in FIG. 11, the input current jx
It goes without saying that the same result can be obtained even if and I′y are exchanged.

8) Conjunction For fuzzy sets X, Y, the conjunction is defined by their membership functions μ×, μy as follows.

X/'IY Nakaμ. χ 3 μ × △ μy ... (20) Logical product △
means selecting the smaller of μX and μy, so equation (20) can be rewritten as follows.

...(21) Equation (20) can be transformed as follows.

μX/17 = μXθ (μ×θμy) − μV θ
(μy e μ×) ... Ku 22) No. (22)
The formula is proven as follows.

μxe(μ×θμy)3Xθ(×θy)=OV [x
−(xθy)] =OV rx −[0V(x −1/ ) ] ] = O
V ((x-0)△(X-(X-Y))]=OV (x
Ay ) =x Ay 3 μ× to μy (23) From equation (22), it can be seen that the logical product operation can be realized by two marginal difference circuits. FIG. 12 shows an AND circuit. Considering this factor, the output current 1a of the first stage limit difference circuit is given by the following equation.

...(24) This current 1a becomes the -h input current of the second stage limit difference circuit, and the other input current (IX is given as the terminal (23). Therefore, The output current 1z of this second-stage limit difference circuit is calculated by the following formula % Formula % By making formula (25) correspond to formula (21),
It will be understood that a logical AND operation is performed.

Since it is impossible for current to flow into the gate of the current mirror (21) of the connected limit difference circuit, the diode (2) can be omitted.

FIG. 13 shows a structure when the AND circuit of FIG. 12 is converted into an IC. In Figure 12, diode (2)
This diode is omitted in FIG. 13 because it can be omitted. Further, regarding the IG pattern of the current mirror 1) in the first stage limit difference circuit, the same reference numerals as the corresponding ones in FIG. 5 (Δ) are given. The cross section along the line bb and the cross section along the line C-C are shown in Figure 5(B) (
These are the same as those shown in C). And d-d
The line cross-section is a part of the cross-sectional view shown in FIG. 5(B) (the same as FIG. 17(B), which will be described later).The first stage current mirror is connected to the second stage current by the Al pattern (63). Connected to the mirror.From the correspondence with Fig. 5, I shown in Fig. 13
It can be easily understood that the C pattern constitutes the circuit shown in FIG.

The IC pattern of the marginal sum circuit in FIG. 9 is realized by adding the A/pattern (67) connected to the A/pattern (62) in FIG. 13.

9) Absolute Difference For fuzzy sets X, Y, the absolute difference is defined by their membership functions μ×, μy as follows.

IX-YI@μ1x-yJ 31μ×−μy1 ...(26) Equation (26) can be transformed as follows.

μmx−n1 − (μ× θμy ) + (μ
y θμ× )...(27) Equation (21) is proven as follows.

(μxeμy)+ (μyeμX)3(×θV)+
(Vθ×) −(×θy) + [OV (y −
x ) ]-[(xθy)+O]V[(xθy)
10 (y - x )] = [[0V (x - y)] + O] V [[OV (x - y)] + (y
−x ) ]= [(0+O) V (0+x
-y )] V[(Y-X +O) V (X-■
+'/-X) ]-OV (x-y)
V (y −x ) VO= (x −
y ) V (y −x )3(μ×−μy
)(μy−μ×)...(28) From equation (27), the calculation of the absolute difference requires two limit difference circuits and one wired OR.
It turns out that this can be achieved by FIG. 14 shows an absolute difference circuit. In this figure, the output current (a
is given by the following equation.

...(29) In the other limit difference circuit including the current mirror (21) and the diode (22), its input currents X and IV are exchanged with the input current of the above one limit difference circuit. Therefore, the output current 1b is given by the following equation.

...30) Since the output current 1z of the absolute difference circuit is the arithmetic sum of the output currents [a and lb], it is as follows.

(Z −1a 10 lb... (31) By making equation (31) correspond to equation (26),
It will be understood that an absolute difference operation is being performed.

FIG. 15 shows a structure in which the absolute difference circuit of FIG. 14 is integrated into an IC. Since the two diodes (2) and (22) cannot be omitted, the IC circuit of FIG.
Two limit difference IC circuits shown in FIG. 5 are arranged side by side, and the A/pattern (64) connected to the anode of the diode (2>(22)) is connected to each other to lead one output. The bb line cross section and the C-C line cross section are the same as those shown in FIGS. 5(B) and 5(C), respectively.

10) Implications For fuzzy sets X, Y, implication is defined by their membership functions μx9μy as follows.

X → Y now -ty 31△(1-μ×10μy) ... (32) While μX represents the degree of belonging to set x, (1-μ×) means that It represents the degree to which one does not belong. Also, the smaller of the logical products Δ is selected. Considering the above, implication represents the arithmetic sum of the degree to which the set It means that. Equation (32) can be expressed more clearly as follows.

1Δ(1−μχ10μy) 33) Well, IC, equation (32) can be transformed as follows.

1Δ(1-μX→μy) = 1θ(μ×θμy) ...(34)th (3rd
4) Equation is proven as follows.

1θ (μXθμy〉31θ(Xθy) = OV N-(x ey ) ] = OV [1-[OV (X - y) ] ] = OV
[(1-0)△(1-(X-V))]=ov ci△
(1-x-←y)] -1△(1-x+y) 31Δ〈1-μ×10μy) ・・・(35)th (
From equation 34), it can be seen that the implication operation can be realized by two limit difference circuits. FIG. 16 shows the implication circuit. In this figure, the output current of the first stage limit difference circuit 1
a is given by the following equation.

(36 N) This current 1a becomes one input current of the second-stage limit difference circuit, and a current with a value of 1 is given as the other input current (terminal (23)). The output current Il of the second stage limit difference circuit is given by the following equation.

...(31) By making equation (37) correspond to equation (33),
It will be understood that an operation of implication is being performed.

In FIG. 16, the diode (2) can be omitted for the same reason as in the AND circuit (FIG. 12). Also, the current 11a flowing out from the output drain of the second stage current mirror (21) is equal to the current 11a flowing out from the output side drain of the second stage current mirror (21).
) can never be greater than 1, so the diode (22) can also be omitted. Therefore, when implementing the implication circuit of FIG. 16 into an IC, as shown in FIG. 17 (A>), the diode (2) (
22) is not necessary.

Figure 17 (A>) shows the b-blIgi plane in the same figure (B
) is shown. The cross section taken along the line CC is the same as that shown in FIG. 5(C).

11) For peer fuzzy sets X, Y, equality is defined by their membership functions μ×, μy as follows.

X#Y@μ engineering's 3μX-97Aμy-tx...(3
8) Equality thus has two implications μx, 7. μ1-px
Therefore, by using the above definition of implication (Equation 33), it can also be expressed as follows.

...(39) Equation (39) can be transformed as follows.

μX shear 1θ ((μ× θμy ) + (μy θμ×)
)... (40) Equation (40) is proven as follows.

X→Y ← Three (X-Y) △ (Y-X) Three (xθy) V (yθx) 1x-yl -1-lx-yl -1-((Xθy) + (yθx)) = 10 ((xθ′/)+(YθX)) (41) From equation (40), it can be seen that the equal operation can be realized by three limit difference circuits and one wired OR. 1st
Figure 8 shows an equivalent circuit. A first limit difference circuit including a current mirror (1) and a second limit difference circuit including a current mirror (21) are connected in parallel. These two marginal difference circuits connected in parallel are the above-mentioned absolute difference circuits.

Therefore, the output current 1c can be expressed as follows by referring to equation (31).

...(42) The limit difference circuit of the third formula is composed of a current mirror (31) and a diode (32), the input current of one of which is the above output current 1c, and the input current of the other with a value of 1. It is an electric current.

Therefore, the output current lz of this third limit difference circuit is given by the following equation.

...(43) It will be seen that an equivalent operation is performed by making the equation (43) correspond to the equation (39).

In equation (43), in the case of 1x-Iy, (lx-
1y )-(Iv-1x)-0, so Iz-1
It is. That is, when the two input currents lx and IV are equal, the output current lx takes a value of 1, and in other cases, l≠1. Therefore, if we focus only on whether the output current 7 is 1 or not, the equivalent circuit can be considered to be a matching circuit.

As can be seen from equation 42), 1C represents the difference between)X and ry. In the case of 1x-ry, rc = o. Also, in the current mirror (31), the short circuit (3
When 4) is open, this element becomes just one F E
It becomes T. This FET is turned off only when Ic-0. If the FET is off, l7=1 because a source current with a value of 1 is given to the input terminal (33). When the FET is on (Ic≠0), the input terminal (3
The discharge input ttt flow in 3) flows from the FET, so it becomes rz-o. The circuit of FIG. 18 has a short circuit (34
), 211! It will be understood that this is an output matching circuit.

Also, since the current 'i4 (equal to IC) flowing out from the output side drain of the current mirror (31) cannot be larger than the input current 1 of the terminal (33), the diode (32) is omitted. Is possible.

FIG. 19 shows a planar pattern when the circuit of FIG. 18 is integrated into an IC. In the equivalent circuit, the diode (32) can be omitted as described above, but the diode (2>(22)) cannot be omitted. Therefore, on the LC board, there is a Two limit difference circuits and another current mirror are installed.The bb line cross section and the C-C line cross section are as follows.
This is the same as shown in FIGS. 5(B) and 5(C).

12) Current distribution circuit In the limit sum circuit (Figure 9), two current sources with a value of 1 are required. Similarly, in the OR circuit (Fig. 11), the AND circuit (Fig. 12), the absolute difference circuit (Fig. 14), and the equal circuit (Fig. 18), the current source of the input current ■× or Iy is Two are required. In this way, when currents of the same value and in the same direction are required, a current distribution circuit may be used. A current distribution circuit can be easily created by extending the current mirror concept. That is, the current mirror shown in FIG.
As can be seen from the IC in the figure, two drains, a common source j3 and a common gate are arranged on the substrate, and one train is connected to the gate. If three or more drains are connected to the gate (multi-output current mirror) on the substrate, a current equal to the gate current (input drain current) will be transferred to the other two or more drains. Such a multi-output current mirror can be expressed as shown in Fig. 20. Fig. 20 shows an example of four outputs.

FIG. 21 shows an example in which the current distribution circuit is applied to the OR circuit (FIG. 11). In the OR circuit, a current IV (source input) must be input to the two terminals (4) and (6), and a voltage V must be pulled. Therefore, the source input current IV of the terminal (73) is converted into the sink input current 1y by the current mirror (72). Furthermore, a multi-output current mirror (71) which inputs this sinking input current 1y
is used to generate two source input currents 1y. Multi-output current mirror (11) is N-MOS FE
It is composed of T.

13) Multi-output circuit A multi-output current mirror can also be applied when it is necessary to obtain a large number of outputs with the same value. FIG. 22 shows the current mirror (72) and the multi-output current mirror (72) described above.
71) (however, the number of output terminals is different) is applied to a limit difference circuit (Fig. 2). It will be seen that four sink output currents I7 are removed from one sink output current 1z. The circuit consisting of current mirrors (71> and (72)) generates a plurality of output currents having the same value and direction as its input current, and is therefore essentially a current distribution circuit.

In other words, a circuit that generates multiple output currents in the same direction as the input current is called a current distribution circuit, and a circuit that generates multiple output currents in the opposite direction to the input current is called a multi-output circuit (multi-output current mirror). I decided to.

14) Multi-output limit difference circuit By further expanding the multi-output circuit, it is possible to configure a multi-output limit difference circuit as shown in FIG. One input side of a wired OR is connected to each output drain of a multi-output current mirror (80) (for simplicity, four outputs are assumed). The other input side of this wired OR is the input terminal (9
1> to (94), and the output side is connected to a diode (81
) to (84) respectively to the output terminals (101) to (
104). Input terminals (91) to (94)
), respectively, and the output currents of the output terminals (101) to (104) are [2, to
124. Then, the following output current is obtained corresponding to equation (3).

However, n-1 to 4 (44) The circuit shown in FIG. 23 achieves four types of limit difference calculations at once. This shows that when one membership function μy is constant and the other membership function μ×n is a variable, it is possible to calculate μ×nθy for many values μχn at once. , which means that the performance speed can be increased and the temporal scanning of μxn can be omitted.

In addition, IX + -IX 2- IX 3 = IX
4-IX, the circuit of FIG. 23 becomes equivalent to the circuit of FIG. 22.

FIG. 24 shows the structure of the multi-output limit difference circuit of FIG. 23 when it is integrated into an IC.

(A) is a planar pattern, and (B), (C), and (D) are cross-sectional views taken along the bb line, CC line, and dd line of (A), respectively. A comb-shaped p region 11 (110) is formed on the mouth-shaped substrate (30), and this p region (
The source of the multi-output current mirror (80) is created by the ohmic contact of the A/pattern (146) to 110). This p-region (110) has five protruding parts, and other five p-regions (111) to (115) are formed to face these protruding parts at appropriate intervals. The width and length of the channels formed between the protruding portion of the p region (110) and the p regions (111) to (115) are set to be equal. p
The protruding portion of region (110) and p regions (111) to (11
5) Polycrystalline 3 that will serve as a gate so as to look into the gap between
i(50) is provided. This polycrystalline 3i (50)
An A/pattern (145) serving as an input side drain is connected to. The AI pattern (145) also has p-region (
115) is in ohmic contact.

The diodes (81) to (84) each have a p-region (1
21) to (124) and n@ regions (131) to (134). A/Pattern (141) above
〜(144) are respectively n 1TII(131)〜(1
34). Output terminals (101) to (10
4) A/patterns (151) to (
154) is connected to pfI areas (121) to (124).

Figure 25 shows the multi-output limit difference circuit as an OR circuit (first
Figure 1) shows an example of its application.

Current mirror (1) and diode (2) in Figure 11
The limit difference circuit consisting of is replaced with a multi-output limit difference circuit shown in FIG.

Further, an input terminal 6) for supplying an input current 1y is connected to the anode side of each of the diodes (81) to (84). The four input terminals (6) d') and the input terminal (4) are connected to the current distribution circuit (20th
It is possible to supply an input current 1y of equal value by using the input current 1y shown in FIG.

From each output terminal (161) to (164), the (19th)
By referring to the formula, it can be easily understood that the logical sum output given by the following formula is obtained.

Iz=[xnV(y where x=1~4...(45) The multi-output limit difference circuit uses diodes (81)~(84
) (Fig. 23) can be omitted.

15) IC circuit with limit difference circuit as a basic element As described above, the basic arithmetic circuit of fuzzy logic can be constructed by a combination of limit difference circuit and wired OR.

Therefore, by creating a logic array of limit difference circuits on the substrate in advance, it becomes possible to realize any fuzzy logic operation circuit by designing only the A/wiring pattern.

As shown in FIG. 26, an IC is prepared in which a large number of basic circuits (180) are provided on a substrate (170). An insulating protective film with contact holes formed at appropriate locations is formed on the upper surface of this IC, and an A/thin film (171), which is a conductor, is further deposited on the negative side of the insulating protective film. Insulating protection film on the top surface of the IC instead of the insulating protection film with contact holes and the Δ/ill film! ! Only the film may be formed over one surface. The basic circuit (180) is in principle the basic element of the limit difference circuit (that is, the limit difference circuit minus its connections). As mentioned above, the diode in front of the current mirror can be omitted, so the basic circuit (
180), it is also possible to use the basic element of a current mirror (current mirror minus the wiring), or these two
Various types of basic elements may be employed.

For example, a manufacturer sells such an IC semi-finished product as 11131.
and provide it to 1-the. Users can add 1 to 3 parts to IC semi-finished products.
By performing a small number of steps, a wiring pattern is created that allows a desired fuzzy logic circuit to be obtained. This allows the user to easily configure a desired fuzzy logic circuit or system.

As shown in FIG. 27, one substrate (170)
It is more preferable to provide not only the basic circuit (1ao) but also a current distribution circuit and multi-output circuits (183) (186) on the top.

Figure 28 shows a circuit connected using an IC semi-finished product equipped with a current distribution circuit and a multi-output circuit as shown in Figure 27.
= An example of a fuzzy logic circuit is shown. Input terminal (20
1) An input current 1yS lx and a current with a value of 1 are given to (202) and (203), respectively. Multi-output circuit (185) formed on substrate (170)
, a number of currents 1y having a value equal to the input current 1y are generated. Similarly, the multi-output circuit (184) (
183) by! A current having a value equal to × and 1 is created. The terminal (204) has a power supply voltage of +V.
are added, and each multi-output circuit (183) to (185)
is applied to.

A large number of limit difference circuits (18) formed on a substrate (170).
0) (181) are connected appropriately, a fuzzy logic circuit having a certain function (this example does not have any particular meaning) is constructed. The output currents of the multi-output circuits (183) to (185) are input to this fuzzy logic circuit. The output current 0 of this fuzzy logic circuit appears at the output terminal (205) (a specific terminal for wire bonding etc. is hypothetical for convenience on the A/pattern).

Since this output current 0 is a source output, a current mirror of the limit difference circuit (182) is used to convert it to a sink output. The diodes of the limit difference circuit (182) have no effect. The cathode side of this diode is open. Limit difference circuit (182
) is sent to a multi-output circuit (186), which provides a number of output currents IO with the same value. This output current IO is at the terminal (
206) to the outside.

The multi-output circuits (183) to (18G) are P-MOS, and the limit difference circuits (180) to (182) are N-MOS.
Each is composed of: In this way, it is possible to provide many types of circuits on one board (170), or it is possible to separate them at the chain line M and provide a multi-output circuit on one board and a limit difference circuit on the other board. Of course, it is also possible to do so.

FIG. 29 shows the part surrounded by the broken line A in FIG. 28, that is, the ICWa construction pattern of the multi-output circuit (1B3) and the limit difference circuit (181). This IC is a polysilicon gate self-alignment PMOS
It is created through a manufacturing process. Substrate (170)
There is an n-type. The multi-output circuit (183) is made of almost the same structure as the multi-output current mirror (symbol (80) in Fig. 24 (A>)).However, one output side drain is made of polycrystalline 3.
The difference is that it is composed of two layers of wiring: i (211) and AI pattern (212).

The other output side drain is connected to the limit difference circuit (181) by an AI pattern (213).

A limit difference circuit (181) is installed in the p region 14 (220). This n area (220) is an AI pattern (
214). n area (221) is A
/ pattern (215) connects to the n region (220) and constitutes the source of the current mirror (191). One of the other n regions (223) is A/pattern (21
3) (drain), and the other (222) is connected to polycrystalline Si (230) which becomes the gate, and is also connected to the input AI pattern (216) (train). The diode (192) is composed of an n region and a p-type polycrystal 3i (225).

The polycrystalline Si (225) is connected to the A/pattern (213), and the n region (224) is connected to the output A/pattern (217).

16) Multi-Functional Fuzzy Logic Circuit FIG. 30 shows a multi-functional fuzzy logic circuit formed on one substrate. This circuit can also be made using a polysilicon gate self-aligned P-MO8 fabrication process.

This circuit also has 12 fuzzy logic operation functions. That is, the outside limit μ8゜y and μyex, the logical product μ
m and μy, limit μ, marginal product IE17 μ, logical sum μ, logical product μ, absolute difference %Oy
XtJ7
Xn7μ(x-yj, the implication μ8→y and μ2.1, and the equality μk17. In FIG. 30, the symbol μ of the membership function represents the current instead of the symbol of the current I for the sake of clarity. It is directly used as a mouse.

The sink input currents μ×, μy, and 1 (currents with values corresponding to the value of 1 in fuzzy logic) are input to the multifunctional fuzzy logic circuit on the board at input terminals (, 211) (
242) (243). In addition, each of the above 12 fuzzy logic performance combinations has an output terminal (2
51) to (262) are output as discharge output currents.

The current μX input from the terminal (241) is input to the N-MOS multi-output circuit (current mirror) (244),
From this circuit (244) six currents μX of the same value and opposite direction are obtained. One of the output currents of this multi-output circuit (244) roughly becomes a source input to a P-MOS multi-output circuit (245), and this circuit (245)
), two currents μX having the same direction and the same value as the current input to the terminal (241) are obtained. In this way, the multi-output circuits (244) (245) output two currents μX that are in the same direction and have the same value and five currents μX that are in the opposite direction and have the same value. can get.

Similarly, multi-output circuit (246) (247)
As a result, one current μy having the same direction and the same value as the current input to the input terminal (242) and four currents μy having the same value and opposite direction are generated.

The current with a value of 1 given to the input terminal (243) is N-M
The direction is reversed by the O8 current mirror (248) and P
- Input to MOS multi-output circuit (249). This circuit (249) provides eight currents having the same direction and the same value 1 as the current input to the terminal (243).

Multi-output circuit (247) and wired OR (281)
and the multi-output current mirror (271), μ%ey
A multi-output limit difference circuit is configured to calculate . This multi-output limit difference circuit uses a multi-output current mirror (
271), five currents μx representing the same value calculation results.
ey is output (exhalation output). That is, if we focus on the current input and output to the wired OR (281),
If μ×>μy, a current of (μ×−μy) flows from the gate (drain connected to the gate) of the multi-output current mirror (271) into the wired OR (281). When μX = μy, the current flowing from the gate of the current mirror (271) to the wired OR (281) is naturally 0.
It is. In the case of μ×<μy, a current of (μy−μ×) tries to flow from the wired OR (281) to the multi-output current mirror (271), but for the current in this direction, the current mirror (271) ) acts as a diode, so in the end, the current mirror (
271) becomes O. Therefore, the first (
2) The calculation of the marginal difference shown in the equation is achieved. The multi-output current mirror (271) performs the dual functions of a diode and a multi-output circuit (corresponds to the diode (2) and multi-output circuit (71) in Figure 22, but the current mirror (72)
) does not exist in Fig. 30). One of the output currents of the multi-output current mirror (271) is sent to the output terminal (253) as a current representing the limit difference μxey.
sent to. Other output currents are used for other fuzzy logic operations.

In the same way, a multi-output circuit (245), a wired OR (282) and a multi-output current mirror (272)
A multi-output limit difference circuit that calculates limit differences μ and θ8 is configured. Multi-output current mirror (272)
Five discharge output currents μyQX are obtained, one of which is sent to the output terminal (252) and the others are used for other calculations.

The logical product μXn7 is expressed as μXθ(μ×θ
μy)=μxeμXQy.

Since the limit difference μ is 11J from the multi-output current mirror (271) Q7, the logical product operation is performed using μx and μxe.
) can be calculated. This operation is accomplished by a multi-output current mirror (271), a wired OR (283), and a current mirror (273) (acting as a diode). The current mirror (273) reverses the direction of the current representing the result of this calculation and outputs it to the output terminal (251).
send to

As can be seen from equation (11), the limit product μ8 is (
It is expressed as μ×10μy〉θ1. (μ×+μl/ )
G, t'fit'-1-'OR (288) kls1l
It3 is done. The limit difference between (μX 10 μy) and 1 is implemented by a circuit consisting of a current mirror (250) and a wired OR (284). The current mirror (250) acts as a diode and has the role of reversing the direction of the output current and outputting it from the terminal (254).

Since the absolute difference μtome 1 is expressed as the sum of the limit difference μxey and μ, θ8 (see equation (27)), it can be realized by these limit difference circuits and wide OR (285), which have already been explained. , the calculation result is output from the terminal (25!i).

The logical complement μV can be expressed as a limit difference (19 μy) (see equation (4)), and a diode is not required in this limit difference circuit. Multi-output circuit (246)
The limit difference (1θμy
) can be realized, and the output current of the logic complement μ7 is given to the terminal (256).

Similarly, the output terminal (261) for the output current of the logic complement μ or the multi-output circuit (244) and the wired OR (292)
> is obtained from a limit difference circuit consisting of.

The implication μy, x is equivalent to the marginal difference (1θμ, Qx) and (
(see equation (34)), and no diode is required in this limit difference circuit. The limit difference circuit that calculates the limit difference (10 μyex >
This is realized by a double-OR (287), and its output appears at the output terminal (257). N-MO8 current mirror (27
6) is used, the direction of the current is opposite to that of the circuit shown in FIG.

Similarly, the implication .mu. (output terminal (259)) is calculated by the equation 1y (1.theta..mu.xey >), and the circuit that performs this marginal difference calculation consists of a current mirror (278) and a wired OR (290).

Equivalent μyay is [1θ(μX617 tenμ79X)
1 (see equation (40)). By Vuyer FOR (293) (μxe7-1μ, ex>
is calculated. A limit difference circuit for calculating the limit difference between 1 and (pxey 10μ, θ8) is composed of a current mirror (277) and a soi-X hood OR (289). A diode can be omitted in this limit difference circuit. The output of this comparable calculation appears at the output terminal (258).

The logical sum μ (output terminal (260)) can be calculated by (μyey γ 10 μ×) (see formula (1G))
, the OR circuit is a limit difference circuit of μy6.7 and a wired O
R(291).

The limit μx87 is expressed as follows from equations (6) and (7).

... (6) = 18 (1θ (μχ 10 μy)) ... (7)'7-1
'-t'OR (295) calculates (μ×+fly), and this current becomes a source input to the gate (drain connected to the gate) of the If-MO8 current mirror (279). This game] has a multi-output circuit (24
One output side of 9) is connected (wired OR
< 296) ), a current with a value of 1 is input. Therefore, a current expressed by the following equation flows into the drain of the current mirror (279).

(No discharge current flows through the drain)...(46
) By the wired OR (294), the current mirror (2
79) drain output current (Equation (46)) is subtracted from the current with a value of 1, and this subtracted current is applied to the output terminal (2
62) appears as a discharge output. Therefore, the current appearing at the output terminal (262) is given by the following equation.

...(47) Equation (47) represents the marginal sum.

In the multifunctional fuzzy logic circuit shown in FIG. 30, many multi-output circuits (FFI-style mirrors) are provided as described above, and (multi) i! Since the diode effect of the current mirror is utilized, the number of elements (for example, the number of drains) is reduced compared to the case where 12 fuzzy logic circuits are individually created.

In Figure 30, the multi-output current mirror (250)
Both (249) are of the P-MOS type, but the number of drains is different.

If a large number of multi-output current mirrors having different numbers of trains are manufactured on the same substrate, the design becomes complicated, so it is preferable to keep the number of drains continuous. By doing this, it is possible to uniformly manufacture elements in the IC board manufacturing process, and it is only necessary to consider the connection between each element when designing the wiring pattern. This makes it possible to simplify the process.

FIG. 31 shows another embodiment of the multifunctional fuzzy logic circuit. This circuit has F in the circuit shown in FIG.
The ET current mirror is replaced by a bipolar junction transistor current mirror and the FET multi-output current mirror is replaced by a bipolar junction transistor multi-output current mirror. These transistor current mirrors and multi-output current mirrors are constructed from multi-collector transistors with two or more collectors. As described above, in a current mirror using a bipolar element, the function as a current mirror is achieved only when the current amplification factor β is very large.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the current input/output form, Figure 2 is a circuit diagram showing a limit difference circuit, Figure 3 is a graph showing its input/output characteristics, and Figure 4 is a circuit diagram of two equivalent current mirrors. , Fig. 5 shows the elm when the limit difference circuit is made into an IC, where <A) is a planar pattern diagram, and (B) is the b-b of (△>).
(C) is a cross-sectional view taken along the line C-C of (A>), Figure 6 is a circuit diagram showing a limit difference circuit constructed of N-MOS FETs, and Figure 7 is an AND circuit. Figure 8 is a graph showing its input/output characteristics, Figure 9 is a circuit diagram showing a marginal sum circuit, Figure 10 is a circuit diagram showing a marginal product circuit, and Figure 11 is a logical sum circuit. 12 is a circuit diagram showing an AND circuit, FIG. 13 is a planar pattern diagram of the IC, FIG. 14 is a circuit diagram showing an absolute difference circuit, and FIG. 15 is a circuit diagram showing an AND circuit.
The figure shows the IC plane pattern, FIG. 16 shows the circuit diagram of the implication circuit, and FIG. 17 shows the IC pattern.
) is a planar pattern diagram, (B) is a cross-sectional view taken along line bb of (A), Fig. 18 is a circuit diagram of the equivalent circuit, Fig. 19 is an IC plane pattern diagram, and Fig. 20 is a multi-output current. A circuit diagram showing a mirror, Fig. 21 is a circuit diagram showing an OR circuit using a current distribution circuit, Fig. 22 is a circuit diagram showing a limit difference circuit using a current distribution circuit, and Fig. 23 is a circuit diagram showing a multi-output limit difference circuit. A circuit diagram showing the circuit, FIG. 24 shows the ICll3'a, (A) is a plane pattern diagram, (B) (C) (
D> is a sectional view taken along line b-b of (A>, C-C
25 is a circuit diagram showing an OR circuit using a multi-output limit difference circuit, 26 is a fuzzy logic +C, and <A) is (B) is a schematic layout configuration diagram of a cross section taken along line bb of (A); FIG. 27 is a schematic layout configuration diagram showing another fuzzy logic IC; FIG. A circuit diagram showing an example of a fuzzy logic circuit, FIG. 29 is a part of the I
This shows the C pattern.
30 is a circuit diagram of a multifunctional fuzzy logic circuit according to an embodiment of the present invention, and FIG. 31 is a circuit diagram of another example of a multifunctional fuzzy logic circuit. (241) to (243)...input terminals, (244) to
(247) (249)...multi-output circuit input circuit), (248)...current mirror (input circuit), (
251) to (262)...output terminals, (271) to (
273)...multi-output current mirror, (250)
(276) to (279)...Current mirror, (281)
~(296)...Wired OR. Other 4 people (A) (B) (C) (D) ,, 2, + ”, t3 +”r
i, H'341'11 (A) (B) 5th ii-i th °61 nu J 1y! rib” 9, ), i, 0 卜) M'1.5月1gl Fig. 12 j (3t3+sentence 1 41 i 67 ・1・14・°l s1) Fig. 15・;='1161g: Ch. ,I,7Figure 1;jj31”? 1 Figure 20 Center 1 Figure VDD 1゛PazG; -1; ・(蓼'7i°:i

Claims (3)

[Claims] (1) At least one of the same value and direction as the input current
It generates two currents and at least one current with the same value and opposite direction as the input current, and is configured with a single-output current mirror, a multi-output current mirror, or a combination thereof, and is configured to generate two currents with respect to two types of input currents. first and second input circuits each provided with a single output current mirror or multiple output current mirror of either input circuit; an output current of a single output current mirror or multiple output current mirror of either input circuit; A wired OR that calculates the difference between one output current of the input circuit and one output current of the other input circuit, and this wired OR
A multi-output limit difference circuit consisting of a multi-output current mirror that receives the output current of R, and at least one of the output currents of the first and second input circuits and the output current of the multi-output limit difference circuit, respectively. A multifunctional fuzzy logic circuit comprising a plurality of different fuzzy logic circuits, each of which has at least one current. (2) 1-output current mirror or multi-output current mirror of either other input circuit, output current of 1-output current mirror of either other input circuit or one output current of multi-output current mirror and one output current of one input circuit. Another multi-output limit difference circuit is provided, comprising a wired OR that calculates a difference with one output current, and a multi-output current mirror that receives the output current of this wired OR as input. The multifunctional fuzzy logic circuit described in item 1). (3) The multifunctional fuzzy logic circuit according to claim (1), which is formed into an IC on one substrate.