JPS60199228A - Fuzzy logical circuit - Google Patents

Abstract

PURPOSE:To offer a basic circuit suitable for the fuzzy logic by connecting a wired OR to an output of a current mirror whose input consists of an FET and an input current source. CONSTITUTION:The limit difference circuit consists of the current mirror 1 comprising a P-MOSFET, wired OR, diode 2, two current source 3, 4 and an output terminal 5. The current source 3 having a sweep-out current Ix and the output terminal 5 via a diode 2 in opposite polarity to the sweep-out direction of the current mirror 1 are connected to the output drain. Since the current Ix is drawn by the current source 3, an output current of Iz=Ix-Iy is sucked through the diode 2 from the terminal 5 when the relation of Ix>Iy exists. In case of Ix<=Iy, the output current of Iy-Ix is about to be flowed forcibly, since it is blocked by the diode 2, the current flowing to the terminal 5 is zero.

Description

[Detailed description of the invention] Background of the invention This invention relates to fuzzy logic circuits.

Fuzzy logic is a logic that deals with fuzziness, or "ambiguity." Ambiguity surrounds human thoughts and actions. Therefore, if such ambiguity can be quantified or theorized, it should be possible to apply it to the design of social systems such as traffic pipes, emergency systems, applied medical systems, and robots created to imitate humans. Since the concept of fuzzy sets was proposed by A. Zadeh in 1965, research on fuzzy logic has been conducted from this perspective as a means of dealing with ambiguity. However, the current situation is that much of this research is directed toward application to software systems using digital computers. Digital computers perform calculations based on binary logic consisting of 0 and 1, and although the calculation processing is extremely strict, it is necessary to add an A/D converter circuit (=J) to the analog input. There is,
For this reason, there is a problem in that when attempting to process a huge amount of information, it takes a long time to obtain the final result.

Further, programs for applying fuzzy logic must be extremely WIN, and complex processing requires a large digital computer, which is not economical.

In the first place, fuzzy logic is a logic that handles continuous values (0, 1) in the interval from 0 to 1, so it has the aspect that it is not compatible with digital 31 calculators based on binary logic. Furthermore, since fuzzy logic deals with wide and ambiguous quantities, calculations performed by digital computers do not require any degree of rigor. Therefore, it is desired to realize circuits and systems suitable for handling fuzzy logic.

SUMMARY OF THE INVENTION The present invention aims to provide a basic circuit suitable for fuzzy logic.

The fuzzy logic circuit according to the present invention includes a current mirror consisting of a FET, a first input current source connected to the Ti current mirror input horn side, a second input current source, and an input side connected to the output side of the current mirror and a second input current source connected to the Ti current mirror input side. The wired OR1 is connected to the input current source of the wired OR, and the output terminal is connected to the output terminal of the wired OR. In principle, a diode is provided between the wired OR and the output terminal, which is in the forward direction with respect to the direction of the output mi.
As will become clear from the embodiments described later, this diode can be omitted in special cases. There are various types of input current sources. For example, the sensor detection signal is
Continuous 1l from O to 1 used in fuzzy logic
A device that represents ti (0, 1) and converts it into a current value corresponding to the detection signal and outputs that value of current, or a commanded or input voltage or current value (regardless of analog or digital). For example, there is a device that converts the input current into a corresponding value and outputs it.Also,
When fuzzy logic circuits are connected in multiple stages, the fuzzy logic circuit in the previous stage will become the input current source for the fuzzy logic circuit in the subsequent stage. Furthermore, one that generates a current corresponding to a certain fixed l11 (for example, a value of 1 in fuzzy logic) may also be used as an input current source. The output terminal includes not only a terminal for wire bonding, but also a conductor for simply guiding the output m current.

For example, the concept of an output terminal also includes an A/pattern for connecting to the next stage fuzzy logic circuit.

Since this invention uses FETs to form 1M 'Fi style mirrors, it is possible to always keep the mirror constant at 1, allowing accurate Fuzzy Theory II calculations and increasing the calculation speed. It is.

Furthermore, since it operates in current mode, arithmetic sums and arithmetic differences can be realized by wired OR, and the circuit configuration can be extremely simplified. Since the fuzzy logic circuit according to the present invention is a basic circuit for various types of fuzzy logic operations, the combination of these circuits enables various types of operations, making it ideal for IC (integrated circuit) implementation.

Description of Embodiments 1) Current input/output mode in fuzzy logic circuit The fuzzy logic circuit in this invention operates in current mode. Therefore, the current input/output format will be briefly explained.

In FIG. 1, the input current of the fuzzy logic circuit (10) is represented by 11, and the output current is represented by IO.

(A) shows an input/output configuration in which the input current 1i flows into the circuit (10) and the output ffi flow IO flows out from the circuit (10). These are called suction input and discharge output. In (B), the input current ■i is the circuit (10
), and the output current IO flows into the circuit (10). Similarly, (C) is the suction input and suction output, and (D
) indicate the discharge input and discharge output, respectively.

When connecting fuzzy logic circuits in multiple stages (cascade), it is preferable to adopt the configuration shown in FIG. 1 (A) or (B). Although FIG. 1 shows an example of one-manpower, one-output circuit, the current input/output form remains the same even in multiple-input, multiple-output circuits.

2) Basic performance of fuzzy logic A fuzzy set X is characterized by a membership function μ×. The membership function represents the degree to which the variable belongs to the fuzzy set X, and this degree is represented by continuous values (0, 1) in the interval from 0 to 1. Therefore, it can be said that the membership function converts the variable into (0, 1). The fuzzy set Y is similarly characterized by a membership function μy.

Fuzzy logic expresses ambiguity in the form of fuzzy sets, and uses this to extend normal logic so that it can handle ambiguity. The basic operations of fuzzy logic include marginal difference, logical complement, marginal use, marginal product, logical sum, logical product, absolute difference, implication, and equality. As will become clear later, these nine basic operations can be expressed by marginal differences and arithmetic sums. This means that the minimum units of basic calculations in fuzzy logic are the marginal difference and the n-arithmetic sum.

One of the advantages of circuits operating in current mode is that the arithmetic sum (
(arithmetic difference) can also be realized with wired OR. Below, these fuzzy theories J! mentioned above will be explained based on the marginal difference circuit. ! The circuit that executes basic calculations is a P-channel MO8 type FET (m field effect transistor) (P-MOS FET).
) will be described in detail. These basic arithmetic circuits employ a current input/output configuration of source input and sink output. Fuzzy logic circuit is P-MO
Not only S FET, but also N channel MO3 type FET (N
-MOS FET>, Complementary MO8 (C-MOS) FE
Needless to say, this can also be achieved using T.

3) Limit difference circuit For fuzzy sets X, Y, the limit difference is defined by their membership functions μX, μy as follows.

XeY#μx6y 3μ×θμy -OV (μX-μy) ... (1) Here, θ is the limit difference, ■ is the logical sum (IllaX) (select the larger one)
) and - represent arithmetic subtraction (arithmetic difference), respectively. Since negative values are not used in fuzzy logic, when (μ×−μy) becomes a negative value in equation (1), the limit difference becomes O due to the logical sum V. That is,
Specifically, Equation (1) expresses the following relationship.

...(2) A limit difference circuit is shown in Fig. 2. The limit difference circuit is P
- a current mirror (1) composed of MOS FETs,
Wired OR, diodes (2), two current sources (3)
) (4) and one output terminal (5). Current mirror (1) is equivalent to a current mirror consisting of two P-MOS FETs. In Fig. 4, (A) shows the current mirror (1) in Fig. 2, and (B) shows the two P-MOS
Current mirrors consisting of FETs (11) and (12) are shown, respectively.

In FIG. 4(B), two FETs (11) (12)
The source (S) of is grounded. Further, these gates (G) are connected to each other, and these gates (G) are connected to the drain (D) of one FET (11). When a source input current 1i is applied to the train (D) of one FET (11), a source output current from the drain (D) of the other FET (11) becomes 1i-1o.
0 is obtained. This is because the gate voltage (voltage between gate and wharf) is applied so that the drain current of FET (11) is equal to li, and this gate voltage also acts on the other FET (12). ) is also equal to li. However, two F
Structure of ET(11) (12) and Si-8i 0
The condition is that the physical properties of the two interfaces are equal. No current flows through the short circuit between the gate (G) and the drain (D) of one FET (11).

If the structures of the two FETs and the physical properties of the Si -8t 02 interface are the same, an output N current 0 equal to the input current 11 can be obtained regardless of the magnitude of the input horn current, which means that the FET
This is a major feature of current mirrors using . In a current mirror using a bipolar element, for example a common junction transistor, li
-1o holds true. When the input current r1 is small, the current amplification factor β also becomes small, so the above equation no longer holds true. The N-flow mirror shown in FIG. 4(B) will be expressed below using the symbols shown in FIG. 4(A).

Returning to Fig. 2, if a current source (4) with a Dl output vB flow 1y is connected to the input drain (gate) of the current mirror (1), the output train has a value equal to this y
It will be clear from the above description that the discharge current of 1g is reduced. A source current of 1 is applied to this output drain.
A current source (3) of x is connected to an output terminal (5) via a diode (2) whose direction is opposite to the direction of discharge of the current mirror (1). lx by current source (3)
Since a current with a value of is drawn, the output jW1 current of Iz-1x-1y will be sucked from the terminal (5) through the diode (2) only when rx>Iy. I×
When ≦IV, an output current of Iy -IX tries to be discharged, but it is blocked by the diode (2), so the output current flowing to the terminal (5) becomes zero. The above relationships can be summarized as follows.

...(3) Membership functions μX and μy are respectively input currents IX
, IV, and the limit difference μxey are made to correspond to the output current Iz, the equation (3) expresses exactly the same relationship as the equation (2). It will be understood that the circuit shown in FIG. 2 is a basic calculation circuit for limit differences.

Figure 3 shows the relationship between the input current IV and the output current 1z.
It shows the relationship between Here, both the person and the output current are normalized so that the maximum value is 1.

FIG. 5 shows an example of the structure of an IC (integrated circuit) in which the limit difference circuit shown in FIG. 2 is implemented as an IC (integrated circuit). <A) is a planar pattern diagram, (B) is a sectional view taken along line b-bl, and (C) is a sectional view taken along line C-C, all of which are shown schematically. Also, the substrate straight (second gate) is omitted. This circuit can be fabricated on an n-type substrate (30) by a normal P-MO3 fabrication process.

The A/(conductor) pattern (61) which becomes the source in the current mirror (1) is in ohmic contact with the pfi region (41). AI pattern (62) that becomes the drain on the input side
is connected to the n area (42). The AI pattern (63) which becomes the drain on the output side is also connected to the n-region (43).

The channels of the two FETs are manufactured so that the channel length and gate oxide film thickness are the same. Between n area (41) and (42) <43>,
Polycrystalline Si ([3 doped, p type) (50
) are StJ-connected via the S+02 insulating film (51). This polycrystal 5i (50) is connected to the A/pattern (62), but the ζAI pattern (63) is Si 02
(51). A diode (2) is configured by the n region (44) and the n region (45).

n region (45) where the AI pattern (63) is on the cathode side
) and is connected to this n region (45). △l pattern (64N) connected to output terminal (5)
It is connected to area 1fc (44).

FIG. 6 shows a limit difference circuit constructed of N-MOS FEI'. r of suction input and discharge output
It has an inflow and output type.

Two drains are also provided, one connected to the gate and the other connected to the output side.

Source is grounded. The diode (2) is of course opposite in orientation to that shown in FIG. It goes without saying that the calculation of equation (3) can be achieved in such a circuit as well.

In FIG. 6, the current sources are replaced by input terminals (3)<4), but the same approach is adopted in the various circuits described below for simplicity.

4) Conjunction For the fuzzy set Y, the conjunction is defined as follows using its membership function μy, and can be expressed using the marginal difference.

Yψμy 31−μy −1θμy (4) Comparing the equation (1) or (2) with this equation (4), the logical product is set to μ×−1 at the marginal difference. It will turn out to be something.

Therefore, the AND circuit may be set to lX-1 in FIG. 2, as shown in FIG. That is, a source that generates an input current of 1 (+n (maximum value)) may be used as the input current source (3).

In this case, the current flowing out from the output side drain (equal to N') is the input voltage of terminal (3)? ! Since the f current cannot be greater than 1, it is possible to omit the diode (2). FIG. 8 shows the relationship between the input current 1y and the output current Jz in the AND operation.

5) For the limit fuzzy sets X and Y, the limit is defined by their membership functions μX and μy as follows.

X■Y@μ%ey -μ×■μy 31Δ(μχ1μy) ...(5) Here, ■ is for limit, Δ is logical product (IIin) (select the smaller one), + is Each represents an arithmetic sum. In fuzzy logic, values greater than 1 are not used, so
If (μχ 0 μy) exceeds 1, the limit value becomes 1 due to the logical product Δ.

That is, Equation (5) specifically expresses the following relationship.

...(6) The limit value of equation (5) can be expressed as follows.

1Δ(μχ+μy) -1θ (1θ(μ×+μy)) ...(7) Equation (7) can be proven as follows.

1θ(1θ(μ×+μy))31θ(1θ(X+y)) -OV(1-(1θ(x+y)))-OV(
1-(OV(1-x-y)))-OV((1-0)A(1-(1-x-V)))=OV(1△(x+y))-1Δ(x+y) 31Δ(μX+μy) (8) As can be seen from equation (7), the limit value can be determined by ten arithmetic sum operations and two limit difference operations. This shows that the marginal sum circuit can be realized by one wired OR and two marginal difference circuits.

FIG. 9 shows a marginal sum circuit. Input terminals (3) (4
) is the arithmetic sum of the source input currents IX and IV 1a-Ix+
Iy is calculated by wired OR, and this current 1a
becomes the input to the first stage limit difference circuit. The other input terminal (6) of this limit difference circuit is provided with a discharge input pipe flow having a value of 1. Therefore, the sink output type 1RIb of the first stage limit difference circuit is given by the following equation.

(9) This output current 1b becomes the input to the second stage limit difference circuit. This limit difference circuit is composed of a current mirror (21) and a diode <22), and also The sink output current 1z is given by the following equation.

(10) Equation (10) corresponds to Equation (6), and it will be understood that the calculation of the marginal sum is executed by the circuit shown in FIG. The circuit shown in FIG. 9 can also be easily integrated into an IC by providing the IC pattern shown in FIG. 5 in two stages.

Although the currents flowing out of the output drains of current mirrors (1) and (21) (equal to Ia and lb, respectively) can be larger than the input current 1 of terminals (6) and (23), respectively, It is possible to omit the diode (2>(22)). This is convenient for IC implementation of the circuit.

6) Marginal score For fuzzy sets X, Y, the marginal score is defined by their membership functions μ×, μy as follows,
and can be expressed using a marginal difference.

XOY#μ8゜.

30V (μχ 10 μy−1) − (μX 10 μy) θ1 (11) Here, 0 represents the limit performance. According to the definition of the marginal score in equation (11), the marginal score means subtracting 1 from the arithmetic sum of the membership functions μ× and μy, and selecting the larger of this subtraction result and O. are doing. Specifically, this shows the following relationship.

...(12) On the other hand, Equation (11) shows that the calculation of the marginal score is performed by an arithmetic sum and a marginal difference. The marginal product circuit is the 10th
As shown in the figure. In this figure, the current mirror (1)
A source input current having a value of 1 is supplied to the gate side input terminal (6) of the circuit. Also, two inputs? tf style 1
The sum of x and 1y is calculated by a wired OR circuit,
This sum current is input to the output side drain of the current mirror (1). Therefore, the output current 11 of this circuit is given by the following equation.

...(13) Since equation (13) corresponds to equation (12), the first
It is clear that the marginal result is calculated by the circuit shown in FIG. The marginal product circuit of FIG. 10 can be easily integrated into an IC by providing another A/pattern (65) connected to the A/pattern (63) in FIG. 5(A).

7) For the disjunctive fuzzy sets X and Y, the theory J! ! The sum is defined by their membership functions μX and μy as follows.

X LI Y #Itlxuy 3μXVμy (14) Since the logical sum ■ means to select whichever is larger μX or μy, equation (14) can be rewritten as follows. can.

...(15) Equation (14) can be transformed as follows.

μXVμy-(μXθμy) 10μy −kuμyθμ×) 10μ× ...(16) Equation (16) is proven as follows.

(μXθμy) 10μy3 (Xθy>10y= [OV (
x −y ) ) ] +y−(V 10)V CV→
-(x-y))! y3μyVμX (17) From equation (16), it can be seen that the logical sum operation Fi can be realized by a limit difference circuit and a wired OR. FIG. 11 shows an OR circuit.

In this figure, the output/J current 1a of the limit difference circuit is given by the following equation.

10 (lx≦Iy) (18) Current IV is supplied to the input terminal (6), and currents 1a and 1y are added by wired OR. Since the final output current 1z is given by Iz-Ia+Iy, 11 is as follows.

(19) It can be seen that a logical sum operation is performed by making the equation (19) correspond to the equation (15).

The IC circuit for the OR circuit is a Δl pattern (64) connected to the AI pattern (64) in FIG. 5(Δ).
6) should be added.

Note that the logical IJ port is as shown in FIG.
Two current sources are required for one input voltage of 1% E (Iy in FIG. 11). Furthermore, in FIG. 11, it goes without saying that the same result can be obtained even if the input currents Ix and IV are exchanged (10).

8) Conjunction For fuzzy results X and Y, the conjunction is defined by their membership functions μ× and μy as follows.

XnYoμxny 3 μ× to μy ... (20) Since the logical product △ means to select the smaller of μX and μy, equation (20) (reshaping the mountain as follows) I can do it.

...(21) Equation (20) can be transformed as follows.

μX/ly −μ×θ(μXθμy) −μyθ(μyeμ×) (22) Equation (22) is proven as follows.

μ×θ(μ×θμy)3x e (x ey )−OV
[X - (XθY)] -OV [x - [OV (x - y)] ] -O
V [(x-0)Δ(x-(x-Y))]-OV (x
Δy) 田XΔy 3μ×μy ...(23) From equation (22), Theory 1! I! It can be seen that the product operation can be realized by two marginal difference circuits. FIG. 12 shows an AND circuit. In this figure, the output current 1a of the first stage limit difference circuit is given by the following equation.

...(24) This current 1a becomes one input ii current of the second stage limit difference circuit, and the other input current (terminal (23)) is 1
× is given. Therefore, the output current 1z of this second-stage limit difference circuit is calculated using the following equation (25) By corresponding equation (25) to equation (21),
Theory@! You can see that the product operation is being performed.

Since it is impossible for current to flow into the gate of the current mirror (21) in the subsequent limit difference circuit, the diode (2) can be omitted.

FIG. 13 shows a structure when the AND circuit of FIG. 12 is integrated into an IC. In Figure 12, die A-de (2)
This diode is omitted in FIG. 13 because it can be omitted. Furthermore, the IC patterns of the current mirror (1) in the first stage limit difference circuit are given the same reference numerals as the corresponding ones in FIG. 5 (Δ). The cross section along the line bb and the cross section along the line C-C are shown in Figure 5(B) (
c>. And d-d
The line cross-section is the same as a part of the cross-sectional view shown in FIG. 5(B) (FIG. 17(B) described in I). The first stage current mirror is connected to the second stage current mirror by an A/pattern (63). From the correspondence with FIG. 5, it can be easily understood that the IC pattern shown in FIG. 13 constitutes the circuit shown in FIG. 12.

In addition, the IC pattern of the marginal sum circuit in FIG. 9 is d3 in FIG. 13, and △? This is realized by adding A/pattern (61) connected to pattern (62).

9 Absolute Difference For fuzzy sets X, Y, the absolute difference is defined by their membership functions μX, μy as follows.

l　X-Y　1@μ is -71 31μ×−μy1 ...(26) Equation (26) can be transformed as follows.

μmx−γ1−(μ×θμy)+(μyθμX)...
(27) Equation (27) is proven as follows.

(μ×θμy) + (μyθμ×) 3(x ey ) + (YθX) −(xey)+[0V(y−x)] −t(xey )+O]V[(xey ) +(y −
X ) ] - [[0V(x-y)]+O]V [[OV (x -V) ] + (Y -X)
] − [(0+O) V (0+x −V ) ] V[
(y-x+0)V(x-y+y-x)]-0V(x-y
)V(y-x)VO = (x-y)V(y-x)3(μX-μ
y) V(μy−μ×)...(28) From equation (27), the calculation of the absolute difference requires two marginal difference circuits and one wire F.
It can be seen that this can be realized by OR. FIG. 14 shows an absolute difference circuit. In this figure, J3 is current mirror (1)
The output current 1a of one of the limit difference circuits including the diode (2) and the diode (2) is given by the following equation.

...(29) In the other limit difference circuit 83 including the current mirror (21) and the diode (22), its input currents X and IY are exchanged with the input current of the one limit difference circuit. Therefore, the output current 1b is given by the following equation.

(30) The output current 1z of the absolute difference circuit is the sum of the output currents (a and 1b) F1@, so it is as follows.

1z-1a0lb...(31) By corresponding equation (31) to equation (26),
It will be understood that an absolute difference operation is being performed.

FIG. 15 shows the lateral movement when the absolute difference circuit shown in FIG. 1114 is integrated into an IC. Two diodes (2) (22>
cannot be omitted, so the IC circuit shown in FIG. 15 has two limit difference IC circuits shown in FIG. are connected to each other to lead to a single exit point. The bb-line cross section and the C--C line cross section are the same as those shown in FIGS. 5(B) and 5(C), respectively.

10) Implications For fuzzy sets X, Y, implication is defined by their membership functions μX, μy as follows.

X → Y9 μ×+n31△(1−μχ×μy) ... (32) Since μ× represents the degree to which it belongs to the set Xk, (1−μ×) belongs to the set X. It expresses the degree to which this is not the case. Also, the smaller of the logical products Δ is selected. As stated above, implication represents the sum of the degree of not belonging to the set X and the degree of belonging to the set Y, and if this arithmetic sum is greater than 1, the result is set to 1. It means. Equation (32) can be expressed more easily as follows.

1Δ(1−μ×10 μy) (33) Moreover, the equation (32) can be modified as follows.

1Δ(1−μ×10μy) −1θ(μXθμy) (34) Equation (34) is proven as follows.

1θ(μXθμy)31θ(x ey )=OV[1-
(xθy)] −OV N −[OV (X −V) ] ] −OV
[(1-0)△(1,-(x-y)))-OV
[1△ (1-X +'/') J-1△ (1-
× →・y) 31△(1−μχ10μy) ...(35)th (34)
From the formula, it can be seen that the operation of implication can be realized by two marginal difference circuits. FIG. 16 shows the implication circuit. In this figure, the output current 1a of the first stage limit difference circuit is given by the following equation.

...<36) This current 1a becomes one input terminal of the second stage limit difference circuit, and an N current with a value of 1 is given as the other input current (terminal (23)). Therefore, the output ri current I2 of the second stage limit difference circuit is given by the following equation.

... (31) By corresponding equation (37) to equation (33),
It will be understood that an operation of implication is being performed.

In the wj16 diagram, the diode (2> is an AND circuit (
It is possible to omit it for the same reason as in the case of FIG. 12). In addition, since the current (equal to Ia) flowing out from the output side drain of the second stage FFI mirror (21) cannot be larger than the input current 1 of the terminal (23), the diode (22) can also be omitted. Therefore, when implementing the implication circuit of FIG. 16 into an IC, it is not necessary to provide diodes (2) and (22) as shown in FIG. 17 (Δ).

A cross section taken along line bb in FIG. 17(A) is shown in FIG. 17(B). The cross section taken along the line CC is the same as that shown in FIG. 5(C).

11) For peer fuzzy sets X, Y, equality is defined by their membership functions μ×, μy as follows.

X→Yφμ mark y ← 3 μx, ) Δμ7.8 (38) Equality is thus expressed by the smaller of the two implications μ, μ Using the definition (Equation 33), it can also be expressed as follows.

...(39) Equation (39) can be transformed as follows.

μxgy −1θ((μXθμy)+(μyθμ×))... 40) Equation (40) is proven as follows.

cY 3(X-Y)Δ(Y-X) Snow 1x-yl Tomi 1-1x-yl -1-((xθy)+(yex)) -1θ((x ey) + (y ex))-(
41) From equation (40), the equality operation is based on the three marginal differences [
It can be seen that this can be realized with one lil path and one wire FOR. FIG. 18 shows an equivalent circuit. A first limit difference circuit including a current mirror (1) and a current mirror (21)
) are connected in parallel. These two marginal difference circuits connected in parallel are the above-mentioned absolute difference circuits. Therefore, the output current 1c can be expressed as follows by referring to equation (31).

(42) The limit difference circuit of the third formula is composed of a current mirror (31) and a diode (32), and the input if current of one of them is the above output current! c, the other input ffi current is a current with a value of 1. Therefore, the output current 1z of this third limit difference circuit
is given by the following equation.

... (43) By making the equation (43) correspond to the equation (39), it will be seen that the equivalent 1i style is executed.

In equation (43), when IX = IV, (l
x-IV )-(ly-1x)-0, so Iz
-1. That is, when the two input currents lx and ly are equal, the output current lx takes a value of 1, and in other cases, 12≠1. Therefore, if we focus only on whether the output current +2 is 1 or not, the equivalent circuit can be considered to be a matching circuit.

The (42nd) formula is empty? ti style 1c is IX and 1
It represents the difference from y. In the case of 1x-1y, Ic-
It is 0. Also, in the current mirror (31), when the short circuit (34) is opened, this element becomes just one F
It becomes ET. This FET is turned off only when Ic-0. If F = E 'r is off, the input terminal (33
) is given a source current of 1, so Iz=
It becomes 1. When the FET is on (Ic≠0), the discharge input mi of the input terminal (33) flows from F E 'l, so it becomes Iz-0. It will be appreciated that the circuit of FIG. 18 becomes a matched circuit with a 211ti output when the short circuit (34) is opened.

Also, the current (equal to Ic) flowing out from the output drain of the current mirror (31) of the IC cannot be greater than the input current 1 of the terminal (33), so the diode (32) can be omitted. is possible.

FIG. 19 shows a planar pattern when the circuit of FIG. 18 is integrated into an IC. In the equivalent circuit, the diode (32) can be omitted as described above, but the diode (2><22) cannot be omitted. To this end, two limit difference circuits consisting of a current mirror and a diode and another current mirror are installed on the 10th base board. The cross section along the line bb and the cross section along the line C-C are
This is the same as shown in FIGS. 5(B) and 5(C).

12) Other limit sum circuits (iTi Figure 9) require two current sources for J3. Similarly, the OR circuit (Figure 11)
, AND circuit (Figure 12), absolute difference circuit (Figure 14),
In the equivalent circuit (Fig. 18), the input current I× and IV
Two current sources are required. In this way, if the same value of current is required, a current distribution circuit may be used. A current distribution circuit can be easily created by extending the current mirror concept. That is, the size of the ffi style mirror shown in FIG. 4(A) is as follows.
As can be seen from the IC shown in FIG. 5, two drains, a common source, and a common gate are provided on the substrate, and one drain is connected to the gate. If three or more drains are connected to the gate of an IC on a long board (multi-output current mirror), a current equal to the gate current (input drain current) will be transferred to the other two or more drains. From (q) at the same time.

Using the multi-output current mirror described above, for a given input lx
Various operations can be performed simultaneously between the input signal 1y+, IV2, . . .

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the current input/output form, Figure 2 is a circuit diagram showing a limit difference circuit, Figure wI3 is a graph that does not show its input/output characteristics, and Figure 4 is a circuit diagram of two equivalent current mirrors. , Fig. 5 shows the structure of the limit difference circuit when it is integrated into an IC.
(C) is a cross-sectional view taken along line C-C in (A), Figure 6 is a circuit diagram showing a limit difference circuit configured with N-MOS FETs, Figure 7 is a logic oil circuit. Figure 8 is a graph showing its input/output characteristics, Figure 9 is a circuit diagram showing a marginal sum circuit, Figure 10 is a circuit diagram without a marginal product circuit, and Figure 8R11 is a logical sum circuit. The circuit diagram, FIG. 12 is a ρ11 diagram showing an AND circuit, FIG. 13 is a plane pattern diagram of the IC, and FIG. 14 is a circuit diagram showing an absolute difference circuit.
Figure 5 shows the IC plane pattern, Figure 16 shows the circuit diagram of the implication circuit, and Figure 17 shows the IC pattern.
A) is a planar pattern diagram, (B) is a sectional view taken along line bb of (A), FIG. 18 is a circuit diagram of an equivalent circuit, and FIG. 19 is a planar pattern diagram of the IC. <1> (21) (31)...Current mirror, (2
)(22) (32)...Diode, (3)(4)
(6) (23) (24n (33)... Input current source (input terminal), (5) (25)... Output terminal. Above and above 4 people ff1r>5 Figure 0 Figure dJ '- (Figure 0 Figure xy Figure 9 Figure 10 Figure 71 Figure Jt) Figure 12 Figure 13 Figure 14 Figure 16 Figure 17

Claims (3)

[Claims] (1) A current mirror consisting of a FET, a first input current source connected to the input side of the current mirror, a second input current source, the input side of which is the output side of the current mirror and the second input current source wired OR connected to each. and an output terminal connected to the output side of the wide 17-OR, a fuzzy logic circuit consisting of (2) The fuzzy logic circuit according to claim (1), wherein a diode is provided between the wire FOR and the output terminal. (3) The fuzzy circuit according to claim e-pupil (1), wherein the directions of the currents of the first input rli current source and the second input current source are in the same direction with respect to the fuzzy logic circuit. logic circuit.