JPS61203715A - Trigger circuit - Google Patents

Abstract

PURPOSE:To facilitate circuit integration by allowing two comparators whose reference voltage have a difference to generate a square wave signal so as to eliminate the need for a capacitor controlling a trigger transistor (TR). CONSTITUTION:In switching a switch 100 from ON to OFF, a level of a base of a TR 20 rises with a slope decided by a time constant comprising a capacitor 54 and a constant current 53. In this case, a voltage of a constant voltage source 50 being a reference voltage of a comparator comprising TRs 10, 11 is set lower than the voltage of a constant voltage source 60 being a reference voltage of a comparator comprising TRs 20, 21. Thus, a square wave signal is obtained by a resistor 12. A trigger is given to a clock terminal of a load FF 200 by using the square wave signal to drive a trigger TR 15. Thus, the capacitor controlling the trigger TR 15 is not required to facilitate circuit integration.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse circuit that utilizes charging and discharging of a capacitor, and more particularly to a trigger circuit.

[Conventional technology]

FIG. 2 shows an example of a conventional trigger circuit. capacitor 1
This circuit, which generates six trigger signals by means of a copy circuit consisting of a switch 100 and a resistor 14, has a switch 100, its control terminal 1, a trigger output terminal 2, and a ground terminal 3. Switch 1
One end of 00 is connected to the ground terminal 3, and the other end is connected to the other end of the capacitor 54 whose one end is grounded, the current source 53, and the PN
P The pace of transistor 10 is connected. P.N.
The collector of the P transistor 10 is connected to the ground terminal 3, and its emitter is connected to the current source 52 and the PNP transistor 11.
is connected to the emitter of PNP) U/Raster 11
The collector of is connected to the pace of the buffer NPN) transistor 16, and is further connected to the ground terminal 3 via a resistor L2t-. The pace of the PNP transistor 11 is connected to one end of the voltage source 50, and the other end of the voltage source 50 is connected to the ground terminal 31C. Current source 52. The collector of the current source 53 and the NPN transistor [6 is connected to the power supply 51
One is connected. Buffer NPN transistor 16
The emitter of is connected to a capacitor 13 constituting a differentiating circuit, and this capacitor 13 is further connected to a resistor 14 and the base of a triggering NPN transistor 15.

The other end of the resistor 14 and the emitter of the trigger NPN transistor 15 are connected to the ground terminal 3. The collector of the trigger NPN transistor/register 15 is connected to the output terminal 2, and is also connected to the clock terminal of the 7-rip flop 200 as a load.

The operation of this circuit will be explained using FIG. Switch lOO
When the control terminal 1 of the PNP transistor 10 is controlled and changed from closed to open, the base of the PNP transistor 10 rises with a slope determined by the time constant of the capacitor 54 and the constant current 530, as shown in FIG. 4(A) a. and the potential of the voltage source 50 (Fig. 4(A)
b), the buffer NPN transistor 160
A step signal shown in Fig. 4 (B))C is obtained,
The step signal is a buffer NPN transistor 16
After the current is amplified by the current, it is applied to the capacitor 13, and the differential waveform shown in FIG. flip flop 200
Give a trigger signal to the collector terminal of.

[Problem that the invention seeks to solve]

In the conventional trigger circuit described above, in order to turn on the trigger NPN transistor 15, it is necessary to make the capacitance value of the capacitor 13 sufficiently large, and the step signal applied to the capacitor 13 has a sufficient current capacity. It must be something that has. However, there are limits to the capacitance value of the capacitor and the value of the step signal, and there is a drawback that a sufficient trigger signal cannot be obtained, which is a major drawback especially in an integrated trigger circuit.

Furthermore, a pulsed trigger signal could not be obtained and could not be used as a pulse.

[Means for solving problems]

The trigger circuit of the present invention includes a capacitor, a switch that controls charging and discharging of the capacitor, a first comparator that compares the charging voltage of the capacitor with a first reference voltage, and a second comparator that compares the charging voltage of the capacitor with a first reference voltage.
The output of the first comparator is used as the operating current source of the second comparator, and the output is obtained from the second comparator.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

This circuit has a switch lOO, its control terminal 1, trigger output terminal 2, and ground terminal 3. One end of the switch lOO is connected to the ground terminal 3tζ, and the other end is connected to the other end of the capacitor 54 whose one end is grounded, the current source 53, and the PNP
) The base of the transistor IO, the base of the transistor I, KPNP) The base of the transistor 200 is connected. The collector of the PNP) raster 10 is connected to the ground terminal 3, and its emitter is connected to the collector of the PNP) transistor 20 and the emitter of the PNP) transistor 11. PNP)
The collector of the transistor 11 is connected to the base of a trigger NPN transistor 15 and further connected to the ground terminal 3 via a resistor 12. The base of the PNP) transistor tt is connected to one end of a voltage source 50, and this voltage source 50
The other end is connected to the ground terminal 3. The emitter of the PNP transistor 20 is connected to the emitter of the PNP transistor 21 and further connected to a constant current source 52. The PNP transistor 210 pace is connected to one end of a voltage source 60, the other end of this voltage source 60 is connected to the ground terminal 3, and the collector of the PNP transistor 21 is also connected to the ground terminal 3.
It is connected to the. The other end of the current source 52° and the current source 53 are connected to the power source 51.

The emitter of the trigger NPN transistor 15 is connected to the ground terminal 3, and its collector is connected to the output terminal 2 and the clock terminal of the flip-flop of the load.

The operation of this circuit will be explained using FIG. switch 100
When the switch 100 is opened from closed by controlling the control terminal 1 of the PNP transistor 200, the base of the PNP transistor 200 changes as shown in FIG.
As shown in I of 1 capacitor 54 and constant current 530
It rises with a slope determined by a time constant. At this time, if the voltage of the constant voltage source 50 (b' in Figure 3 (A)) is set lower than the voltage of the constant voltage source 60 (c' in Figure 3 (A)), the constant current source The current flowing from 52 is PNP)
The potential of the voltage source 50 (b/ in FIG. 3(A)) flows through the raster 20 and the PNP transistor 10 to the ground terminal 3.
When the base potential of the PNP) run raster 100 pace potential and the base potential of the PNP) transistor 2o (a/ in Figure 3 (A)) exceeds the current flowing from the constant current source 52, the current flows through the PNP) transistor 20 and the PNP transistor 1 and becomes the resistor. 12t
- to the ground terminal 3 through. Further, the potential of the voltage source 60 (c' in FIG. 3(A)) of the t-PNP transistor 100
Base potential and base potential of PNP transistor 2o (
When a') in FIG. 3(A) is exceeded, the current flowing from the constant current source 52 flows through the PNP transistor 21 to the ground terminal 3II (fi).This state can be seen from the base potential of the trigger NPN transistor t5. When viewed, a square wave signal shown in FIG. 3 (CB) is obtained. If the resistor 12 is set so that the amplitude of the square wave signal becomes a voltage sufficient to turn on the trigger NPN transistor 15, this signal will
By driving the triggering transistor 15, a trigger can be applied to the clock terminal of the seven lip-flop 200 of the load. Furthermore, the square wave signal obtained at the base of the trigger NPN transistor 15 can be used as a pulse signal.

〔Effect of the invention〕

As explained above, since the present invention generates a square wave signal using two comparators with different reference voltages, a capacitor is used to control the trigger transistor using the signal as a control signal. A trigger circuit that does not require a control signal and can be driven even with a control signal having a small current capacity can be obtained.

Since it does not use a capacitor, it is very advantageous for integrated circuits, and it is also possible to obtain pulses as an output.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional example, FIGS. 3A and 3B are graphs showing the operation of the embodiment of the present invention, and FIG. Figure (A). (B) and (C) are graphs showing the operation of the conventional example. l... Switch control terminal, 2... Trigger output terminal, 3... Ground terminal, to, 11, 20
．． 21...PNP) transistor, 15.16.
...NPN transistor, 12.14...
・Resistance, 13.54...Capacitor, 50.6
0... Constant voltage source, 51... Power supply, 52
．． 53... Constant current source, 100... Switch, 200... Flip-flop. Mine 5 times τ Mei 4-Kuni

Claims (1)

[Claims] a capacitor; a switch that controls charging and discharging of the capacitor; a first comparator that compares the charging voltage of the capacitor with a first reference voltage;
a second comparator for comparison with a reference voltage of the first
A trigger circuit characterized in that the output current of the comparator is used as a constant current for driving the second comparator, and an output signal is obtained from the second comparator.