JPS6120358A - Substrate for mounting semiconductor element - Google Patents

Substrate for mounting semiconductor element

Info

Publication number
JPS6120358A
JPS6120358A JP14200384A JP14200384A JPS6120358A JP S6120358 A JPS6120358 A JP S6120358A JP 14200384 A JP14200384 A JP 14200384A JP 14200384 A JP14200384 A JP 14200384A JP S6120358 A JPS6120358 A JP S6120358A
Authority
JP
Japan
Prior art keywords
layer
ceramic
substrate
metal
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14200384A
Other languages
Japanese (ja)
Inventor
Akira Otsuka
昭 大塚
Masanori Tsujioka
正憲 辻岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP14200384A priority Critical patent/JPS6120358A/en
Publication of JPS6120358A publication Critical patent/JPS6120358A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To obtain the titled substrate of high heat-dissipation excellent in electrical insulation by a method wherein the surface of the base metal is coated with a thin layer of Ti or TiO2 to a thickness of 0.5-10mum and provided with a ceramic coat layer thereon by a vapor phase method. CONSTITUTION:The surface of the base metal 1 of composite material or a sintered compact of infiltrated powder is coated with a thin layer of Ti or TiO2 2 and with a ceramic layer 3 thereon. The Ti or TiO2 layer has a large effect in preventing the diffusion of a metal such as Cu when coating the base metal; besides, a Ti oxide layer or a TiO2 layer produced in the outermost surface by spontaneous oxidation in the case of a Ti layer is very dense and prevents the oxidation of the base metal, and is excellent in wetting with ceramic materials. The Ti layer or TiO2 layer in this case is preferably 0.5-10mum. As the material of a ceramic layer is the outer layer, any of Al2O3, SiO2, MgO, etc. or their composite can be used. It is preferable that the ceramic layer is 1.0-20mum thick.

Description

【発明の詳細な説明】 イ、産業上の利用分野 この発明は半導体素子搭載用の基板、特に高放熱性で電
気絶縁性に優れた基板に関するものである。
DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application This invention relates to a substrate for mounting semiconductor elements, particularly a substrate with high heat dissipation and excellent electrical insulation.

口、従来技術 従来から半導体素子を搭載する基板としてはアルミナ系
のものが多く用いられている。しかし近来IC素子の高
密度化、高速度化に伴い半導体搭載用基板としてはアル
ミナ系のものより高放熱性のものが要求されるようにな
ってきた。
BACKGROUND OF THE INVENTION Conventionally, alumina-based substrates have been widely used as substrates on which semiconductor elements are mounted. However, in recent years, as the density and speed of IC devices have increased, substrates for mounting semiconductors have come to be required to have higher heat dissipation than alumina-based substrates.

高放熱性を目的とした電気絶縁性の半導体素子搭載用基
板としてアルミナ系でなく次のような材料のものが提案
されている。
The following materials other than alumina-based materials have been proposed as electrically insulating semiconductor element mounting substrates aimed at high heat dissipation.

■ Cu板あるいはCu合金板にAl2O2薄板を張り
合わせたもの ■ AI板の表面をアルマイト処理して電気絶縁性を付
与したもの ■ BeOを用いたもの しかしながら■のタイプではAhOa薄板が100μm
以下の厚さの板が得られず、従って薄板が熱伝導に対す
るバリア(障壁)となり、十分な熱伝導性が得られない
。またCuの熱膨脹係数も半導体素子基板より大きい。
■ A thin Al2O2 plate laminated to a Cu plate or a Cu alloy plate ■ An AI plate whose surface is treated with alumite to give it electrical insulation ■ A type using BeO However, in the type ■, the AhOa thin plate is 100 μm thick.
Therefore, the thin plate becomes a barrier to heat conduction and sufficient thermal conductivity cannot be obtained. Further, the coefficient of thermal expansion of Cu is also larger than that of the semiconductor element substrate.

■タイプのものはアルマイト処理で得られるA10層が
多孔質であるため十分な電気絶縁性が得られないばかり
か、金属Alの熱膨脹係数がSi 、 GaAs 等の
半導体素子に比し大きすぎるため大型の半導体素子を搭
載すると熱膨脹係数のミスマツチ(差)により素子の割
れやクラックが生ずる等の欠点がある。■タイプのもの
は高価であり、且つBeOが毒性を有する欠点がある。
■The A10 layer obtained by alumite treatment is porous, so not only does it not provide sufficient electrical insulation, but the thermal expansion coefficient of metal Al is too large compared to semiconductor elements such as Si and GaAs, so it is large. When a semiconductor device is mounted, there are drawbacks such as cracks or cracks in the device due to a mismatch (difference) in the coefficient of thermal expansion. Type (2) is expensive and has the disadvantage that BeO is toxic.

これらの欠点を解消するために近年に熱膨脹係数が10
XIOcI11/(’III°C以下である金属板の表
面に気相法によりセラミックを薄層コーティングした基
板が提案された。この方法であると、セラミック層は2
0μm以下であり、従って熱伝導のバリアとはならず且
つ金属板の熱膨脹係数が10×10171°C以下で半
導体素子及びコーティングするセラミックのそれに近似
しているので半導体素子やセラミック層に割れやクラン
クが生じることがない。熱膨脹係数が10×10cTs
/α°C以下の金属板の材料としてはW 、 Mo 、
 Ta等の熱膨脹係数の小さな金属やそれらの金属の粉
末焼結体に熱伝導率の大きな金属例えばCu、Ag及び
その合金等を複合した材料が用いられる。例えばW焼結
体にCuを溶浸(Infiltration) したC
u−W合金等である。
In order to eliminate these drawbacks, in recent years the coefficient of thermal expansion has been increased to 10.
A substrate has been proposed in which a thin layer of ceramic is coated on the surface of a metal plate whose temperature is below
0 μm or less, therefore, it does not act as a barrier to heat conduction, and the thermal expansion coefficient of the metal plate is 10 × 10171°C or less, which is close to that of the semiconductor element and coating ceramic, so it will not cause cracks or cracks in the semiconductor element or ceramic layer. never occurs. Thermal expansion coefficient is 10×10cTs
/α°C or less metal plate materials include W, Mo,
A composite material is used that is a combination of a metal with a small coefficient of thermal expansion such as Ta, or a powder sintered body of such metal, and a metal with high thermal conductivity, such as Cu, Ag, or an alloy thereof. For example, C made by infiltrating Cu into a W sintered body.
u-W alloy, etc.

ハ0発明が解決しようとする問題点 ところがこのような複合材料または溶浸粉末焼結体にお
いてCu或いはCu合金等の熱伝導性の良い材料が表面
に露出している材料にセラミック薄層をコーティングし
た場合には十分な電気絶縁性が得られない欠点があった
Problems to be Solved by the Invention However, in such composite materials or infiltrated powder sintered bodies, materials with good thermal conductivity such as Cu or Cu alloys are coated with a ceramic thin layer on the exposed surface. In this case, there was a drawback that sufficient electrical insulation could not be obtained.

この発明はかかる従来技術の欠点を省みてなされたもの
で、表面の少なくとも一部にCu或いはCu合金等の熱
伝導性の良好な材料が露出した複合材料や溶浸粉末焼結
体に確実に電気絶縁性の良好なセラミックを薄層コーテ
ィングした半導体素子搭載用基板であり、熱膨脹係数が
半導体素子に近似し熱伝導性が良好で且つ表面の電気絶
縁性がありしかも耐蝕性にすぐれた半導体素子搭載用基
板を提供することを目的とするものである。
This invention was made in consideration of the drawbacks of the prior art, and it is possible to reliably apply a composite material or an infiltrated powder sintered body in which a material with good thermal conductivity such as Cu or Cu alloy is exposed on at least a part of the surface. This is a substrate for mounting a semiconductor element coated with a thin layer of ceramic with good electrical insulation, and has a coefficient of thermal expansion close to that of the semiconductor element, good thermal conductivity, electrical insulation on the surface, and excellent corrosion resistance. The purpose is to provide a mounting board.

二0問題点を解決するための手段 本発明者らは上記従来の半導体素子搭載用基板のセラミ
ック層の電気絶縁性が低下する原因を詳細に調査した結
果、 ■ 複合材料或いは溶浸粉末焼結体の表面が粗いこと。
20 Means for Solving the Problems The inventors of the present invention have conducted a detailed investigation into the cause of the decrease in the electrical insulation properties of the ceramic layer of the conventional substrate for mounting semiconductor elements, and have found that: ■ Composite materials or infiltrated powder sintering The surface of the body is rough.

従って一様な厚さのセラミック層が形成しないこと ■ セラミックコーティングする時の雰囲気によってC
u等の熱伝導性材料の表面が酸化反応を起こしてセラミ
ック層との密着を害すること■ セラミックコーティン
グする時の温度(加熱)によってCu等の金属材料がセ
ラミック層の表面まで拡散すること の3つの原因によるものであることを見い出した。
Therefore, a ceramic layer of uniform thickness may not be formed.
The surface of a thermally conductive material such as u causes an oxidation reaction that impairs its adhesion to the ceramic layer. ■ The temperature (heating) during ceramic coating causes metal materials such as Cu to diffuse to the surface of the ceramic layer. We found that this was due to two causes.

そこでこの問題を解決する為に、複合材料または溶浸粉
末焼結体の表面粗さを緩和し且つ露出したCu 等の金
属表面を被覆して金属表面の酸化反応やセラミック層へ
の拡散を防止する目的で複合材料、粉末焼結体等の下地
金属の表面に他の物質を一部コーティングすることを考
えて、種々の物質をコーティングしたものを造り、その
上にセラミックコーティングを施して電気絶縁性を調査
した結果Ti或いはTiO2をコーティングしたものが
Cu等の金属の拡散防止効果は勿論上層のセラミック層
との密着性も優れており、満足すべき電気絶縁性を有す
るセラミック層を形成することができることを発見して
本発明をなしたものである。
Therefore, in order to solve this problem, the surface roughness of the composite material or infiltrated powder sintered body is alleviated and the exposed metal surfaces such as Cu are coated to prevent oxidation reaction on the metal surface and diffusion into the ceramic layer. For the purpose of electrical insulation, we consider coating a part of the base metal surface of composite materials, powder sintered bodies, etc. with other substances, and then coat them with various substances, and then apply a ceramic coating on top of them to create electrical insulation. As a result of investigating the properties, it was found that a coating coated with Ti or TiO2 not only has an effect of preventing the diffusion of metals such as Cu, but also has excellent adhesion with the upper ceramic layer, and forms a ceramic layer with satisfactory electrical insulation properties. The present invention was made based on the discovery that this can be done.

本発明は熱膨脹係数の小さな金属と熱伝導性の良好な金
属との複合材料或いは前者の粉末焼結体に例えばCuや
Cu合金等の後者の金属を溶浸した材料、即ち表面に後
者の材料が露出している材料の金属板にTiもしくはT
iO2を05〜10μmの厚さに薄層コーティングした
上にセラミックを薄層コーティングしたことを特徴とす
る半導体素子搭載用基板である。
The present invention relates to a composite material of a metal with a small coefficient of thermal expansion and a metal with good thermal conductivity, or a material in which a powder sintered body of the former is infiltrated with the latter metal such as Cu or a Cu alloy, that is, a material in which the latter metal is infiltrated on the surface. Ti or T is added to the exposed metal plate.
This is a substrate for mounting a semiconductor device, characterized in that it is coated with a thin layer of iO2 to a thickness of 05 to 10 μm and further coated with a thin layer of ceramic.

以下図面により本発明を説明すると、第1図に示すよう
に複合材料あるいは溶浸粉末焼結体の下地金属(1)の
表面に薄層のTiもしくはTiO2層(2)を薄層コー
ティングし、その上にセラミック層(3)をコーティン
グした構造を有するものである。
The present invention will be explained below with reference to the drawings. As shown in Fig. 1, a thin Ti or TiO2 layer (2) is coated on the surface of a base metal (1) of a composite material or infiltrated powder sintered body, It has a structure in which a ceramic layer (3) is coated thereon.

一般にコーティングすることによって表面粗さが減少す
ることは勿論であるが、コーテイング材としてTi及び
T i O2を選ぶのは、TiあるいはTlO2層は下
地金属を被覆するとCu等の金属の拡散防止に効果が大
きく且つTi層の場合に最表面に自然酸化によってでき
るTi酸化層やTlO2層は非常に緻密で下地金属の酸
化を防止すると共にセラミック材料との濡れ性が良いた
めである。
It goes without saying that surface roughness is generally reduced by coating, but the reason why Ti and TiO2 are selected as coating materials is that when the Ti or TlO2 layer is coated on the underlying metal, it is effective in preventing the diffusion of metals such as Cu. This is because, in the case of a Ti layer, the Ti oxide layer or TlO2 layer formed on the outermost surface by natural oxidation is very dense, prevents oxidation of the underlying metal, and has good wettability with the ceramic material.

この場合のTi層もしくはTiO2層は0.5〜10μ
mが良い。05μm以下では本発明の効果がなく、また
10μm以上ではTi層やTiO2層の内部応力の為に
セラミックコーティングの際の加熱によってTi層やT
iO2層にクラックやハガレが生ずるからである。
In this case, the Ti layer or TiO2 layer is 0.5 to 10μ
m is good. If the thickness is less than 0.05 μm, the present invention has no effect, and if the thickness is more than 10 μm, the Ti layer or Ti layer may be damaged by heating during ceramic coating due to internal stress in the Ti layer or TiO2 layer.
This is because cracks and peeling occur in the iO2 layer.

外層のセラミック層の材質としてはA120a 。The material of the outer ceramic layer is A120a.

5i02 、 MgO等のいずれか或いはそれらの複合
体を用いることができる。またセラミック層の厚さは1
.0〜20μmが良い。1.0μm以下では十分な電気
絶縁性が得られず、20μm以上になるとセラミック層
の内部応力の為にセラミック層にクランクやハガレが生
じ易く、たとえクラックやハガレが生じなくても、セラ
ミック層自体の厚さのために熱伝導のバリアとなり、ま
たコーティング作業に要するコストが大きくなるからで
ある。
5i02, MgO, etc., or a complex thereof can be used. Also, the thickness of the ceramic layer is 1
.. 0 to 20 μm is good. If it is less than 1.0 μm, sufficient electrical insulation cannot be obtained, and if it is more than 20 μm, the ceramic layer tends to crack or peel due to the internal stress of the ceramic layer, and even if no cracks or peeling occur, the ceramic layer itself This is because the thickness of the coating acts as a barrier to heat conduction and increases the cost required for coating.

これらのコーティングは真空蒸着、イオンプレーティン
グ、イオンスパッタリング、CvD1プラズマCVD等
の種々の方法があるが、いずれの方法を用いても本発明
の効果には変わりはない。
There are various methods for forming these coatings, such as vacuum deposition, ion plating, ion sputtering, and CvD1 plasma CVD, but the effects of the present invention remain the same no matter which method is used.

ホ、実施例 実施例1゜ Wの粉末焼結体に15 von%溶浸した1100X1
0011の厚さ1鰭の基板を造り、Tiを真空蒸着法に
より、4.0μmの厚さ薄層コーティングした。真空蒸
着は真空度2 X 10−5Torr 、基板温度20
0°Cで99.9%の純Ti原料に電子ビームを照射し
てTlを溶融し、1μm/劃の蒸着速度で基板に蒸着し
た。このようにして得られたTiを表面に40μm薄層
コーティングしたCu−W(銅−タングステン)複合材
料にプラズマ−CVD法によりAl2O3を6,0μm
の厚さにコーティングした。プラズマ−CVD法は基板
を600°Cに加熱した後、ガス圧1.0Torr に
コントロールした室内にAICβB、CO2,H2の3
種類のガスを流し、基板を取りつけた平行平板電極に高
周波(13,56MHz)電圧を300W印加してガス
の一部をイオン化し気相反応を行い、2μm/hr  
の速度でA120aを表面に析出させた。
E, Example Example 1゜W powder sintered body was infiltrated with 1100
A substrate of 0011 with a thickness of 1 fin was prepared, and a thin layer of Ti was coated with a thickness of 4.0 μm by vacuum evaporation. Vacuum deposition is performed at a vacuum level of 2 x 10-5 Torr and a substrate temperature of 20
A 99.9% pure Ti raw material was irradiated with an electron beam at 0° C. to melt Tl, and the material was deposited on a substrate at a deposition rate of 1 μm/mt. The thus obtained Cu-W (copper-tungsten) composite material whose surface was coated with a 40-μm thin layer of Ti was coated with 6.0 μm of Al2O3 by plasma-CVD.
Coated to a thickness of . In the plasma-CVD method, after heating the substrate to 600°C, AICβB, CO2, and H2 are placed in a chamber controlled at a gas pressure of 1.0 Torr.
A high frequency (13,56 MHz) voltage of 300 W was applied to the parallel plate electrodes attached to the substrate to ionize a part of the gas and perform a gas phase reaction.
A120a was deposited on the surface at a rate of .

このようにして得られたAJhOaコーティングした基
板は2MΩ以上の絶縁抵抗を有し、温度90°C1湿度
90%の多湿雰囲気中に60時間放置しても、腐食や膜
(コーティング層)のハガレ等は生じなかった。
The thus obtained AJhOa-coated substrate has an insulation resistance of 2 MΩ or more, and even if it is left in a humid atmosphere at a temperature of 90°C and a humidity of 90% for 60 hours, there will be no corrosion or peeling of the film (coating layer). did not occur.

実施例2゜ 実施例1と同様な下地金属にTi層を4.0μmの厚さ
にコーティングした試料とTiをコーティングしない試
料に種々の厚さにAl2O8をコーティングして、その
表面にAβ金属を2X2j11の面積に9点蒸着しM金
属と下地金属の間にIOVの電圧を印加してその間の絶
縁抵抗値を測定した。
Example 2 A sample in which the same base metal as in Example 1 was coated with a Ti layer to a thickness of 4.0 μm and a sample without Ti coating were coated with Al2O8 to various thicknesses, and Aβ metal was coated on the surface. Nine points were deposited on an area of 2×2j11, a voltage of IOV was applied between the M metal and the underlying metal, and the insulation resistance value therebetween was measured.

9点の平均抵抗値の結果は第2図に示す通りであった。The results of the average resistance values of the nine points were as shown in FIG.

この結果から下地金属にTi層をコーティングしてその
上にセラミック層をコーティングした基板の方が明らか
に絶縁抵抗値が大きく優れていることがわかる。
From these results, it can be seen that the substrate in which the base metal is coated with a Ti layer and the ceramic layer is coated thereon has a significantly superior insulation resistance value.

へ9発明の効果 以上に詳しく説明したように、本発明による下地金属に
TiあるいはTiO2を薄層コーティングして、それを
下地にセラミックコーティングした金属板の半導体素子
搭載用基板は電気絶縁性、耐熱性及び耐蝕性に優れ且つ
熱放散性が良好であり、高密度化、高速度化した半導体
素子を搭載したパンケージやハイブリットIC用基板及
びマザーボード等に用いて優れた性能を有するものであ
る。
9. Effects of the Invention As explained in detail above, the substrate for mounting a semiconductor element, which is a metal plate in which a thin layer of Ti or TiO2 is coated on a base metal and a ceramic coating is applied to the base metal, according to the present invention has electrical insulation and heat resistance. It has excellent properties such as hardness and corrosion resistance, and good heat dissipation properties, and has excellent performance when used in pancages, hybrid IC substrates, motherboards, etc. on which high-density, high-speed semiconductor elements are mounted.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の半導体素子搭載用基板の断面図、第2
図は実施例2の場合のセラミック層の厚さと絶縁抵抗の
関係を示すグラフである。 (1)・・・下地金属、    (2)・・・コーティ
ング薄層、(3)・・・セラミック層。 代理人 弁理士  1)中 理 夫 第1図 A/2031のノ啄さく<t7rL) 第2図 手続補正書(自発)
FIG. 1 is a cross-sectional view of a substrate for mounting a semiconductor element according to the present invention, and FIG.
The figure is a graph showing the relationship between the thickness of the ceramic layer and the insulation resistance in Example 2. (1) Base metal, (2) Thin coating layer, (3) Ceramic layer. Agent Patent Attorney 1) Rio Naka Figure 1 A/2031 no Takusaku<t7rL) Figure 2 Procedural Amendment (Voluntary)

Claims (1)

【特許請求の範囲】 1、熱膨脹係数が10×10^−^6cm/cm℃以下
であり且つ熱伝導性の良好な金属を含む金属複合体或い
は溶浸粉末焼結体で材料表面の少なくとも一部に熱伝導
性の良好な金属が露出している下地金属板の表面にセラ
ミック層をコーティングした半導体素子搭載用基板にお
いて、該下地金属の表面にTiもしくはTiO_2を0
.5〜10mm厚さに薄層コーティングを施し、その上
に気相法によりセラミックコーティング層をもうけたこ
とを特徴とする半導体素子搭載用基板 2、熱伝導性の良好な金属がCuあるいはCu合金であ
ることを特徴とする特許請求の範囲第1項記載の半導体
素子搭載用基板 3、下地金属板がW、Mo、Taの粉末焼結体にCuあ
るいはCu合金を溶浸した金属板であることを特徴とす
る特許請求の範囲第1項記載の半導体素子搭載用基板 4、セラミック層が厚さ1.0〜20μmのAl_2O
_3、SiO_2、MgOのいずれか或いはそれらの複
合体であることを特徴とする特許請求の範囲第1項乃至
第3項いずれかに記載の半導体素子搭載用基板 5、Ti或いはTiO_2薄層が真空蒸着法、イオンプ
レーティング法、イオンスパッタリング法のいずれかの
方法によつて形成せしめた層であることを特徴とする特
許請求の範囲第1項乃至第3項いずれかに記載の半導体
素子搭載用基板
[Scope of Claims] 1. A metal composite or infiltrated powder sintered body containing a metal having a coefficient of thermal expansion of 10×10^-^6cm/cm°C or less and having good thermal conductivity, at least one part of the material surface. In a substrate for mounting a semiconductor element in which a ceramic layer is coated on the surface of a base metal plate in which a metal with good thermal conductivity is exposed, the surface of the base metal is coated with 0 Ti or TiO_2.
.. A semiconductor element mounting substrate 2 characterized in that a thin layer coating is applied to a thickness of 5 to 10 mm, and a ceramic coating layer is formed thereon by a vapor phase method, and the metal with good thermal conductivity is Cu or a Cu alloy. The substrate 3 for mounting a semiconductor element according to claim 1 is characterized in that the base metal plate is a metal plate obtained by infiltrating a powder sintered body of W, Mo, and Ta with Cu or a Cu alloy. A semiconductor element mounting substrate 4 according to claim 1, characterized in that the ceramic layer is Al_2O with a thickness of 1.0 to 20 μm.
_3, SiO_2, MgO, or a composite thereof, the semiconductor element mounting substrate 5 according to any one of claims 1 to 3, wherein the thin Ti or TiO_2 layer is in a vacuum state. The semiconductor element mounting device according to any one of claims 1 to 3, wherein the layer is formed by any one of vapor deposition, ion plating, and ion sputtering. substrate
JP14200384A 1984-07-09 1984-07-09 Substrate for mounting semiconductor element Pending JPS6120358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14200384A JPS6120358A (en) 1984-07-09 1984-07-09 Substrate for mounting semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14200384A JPS6120358A (en) 1984-07-09 1984-07-09 Substrate for mounting semiconductor element

Publications (1)

Publication Number Publication Date
JPS6120358A true JPS6120358A (en) 1986-01-29

Family

ID=15305116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14200384A Pending JPS6120358A (en) 1984-07-09 1984-07-09 Substrate for mounting semiconductor element

Country Status (1)

Country Link
JP (1) JPS6120358A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100244822B1 (en) * 1995-09-28 2000-02-15 니시무로 타이죠 High thermal conductivity silicon nitride circuit substrate and semiconductor device using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100244822B1 (en) * 1995-09-28 2000-02-15 니시무로 타이죠 High thermal conductivity silicon nitride circuit substrate and semiconductor device using the same

Similar Documents

Publication Publication Date Title
US5011732A (en) Glass ceramic substrate having electrically conductive film
JPS5815241A (en) Substrate for semiconductor device
WO2005091360A1 (en) Substrate for semiconductor device and semiconductor device
US5382471A (en) Adherent metal coating for aluminum nitride surfaces
TWI283463B (en) Members for semiconductor device
US5134461A (en) Ceramics substrate with an improved surface structure for electronic components
JPS6120358A (en) Substrate for mounting semiconductor element
US5250327A (en) Composite substrate and process for producing the same
JPH0679444B2 (en) Electric film
JP2003089883A (en) Functional element and method of manufacturing the same
US5190601A (en) Surface structure of ceramics substrate and method of manufacturing the same
JPS6027188B2 (en) Substrate for mounting semiconductor elements
US6914330B2 (en) Heat sink formed of diamond-containing composite material with a multilayer coating
JPS63310956A (en) Film forming metal mask
JPS6130042A (en) Semiconductor element loading substrate
JPS62182182A (en) Aluminum nitride sintered body with metallized surface
JP3282700B2 (en) Coating film formation method
JP3230260B2 (en) Surface coated metal material for vacuum equipment
JPH029457B2 (en)
JP2573991B2 (en) Heat sink and method of manufacturing the same
JPH04232248A (en) Multilayer insulating structural body and its manufacture
JPS60245153A (en) High electrically insulating substrate for semiconductor device
JPS6214445A (en) Composite material for electronic part
JPH0794355B2 (en) Method for producing aluminum nitride sintered body having metallized surface
JPH0816262B2 (en) Electrical wire