JPS61202246A - メモリアクセス制御方式 - Google Patents
メモリアクセス制御方式Info
- Publication number
- JPS61202246A JPS61202246A JP60043205A JP4320585A JPS61202246A JP S61202246 A JPS61202246 A JP S61202246A JP 60043205 A JP60043205 A JP 60043205A JP 4320585 A JP4320585 A JP 4320585A JP S61202246 A JPS61202246 A JP S61202246A
- Authority
- JP
- Japan
- Prior art keywords
- access
- ports
- port
- circuit
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Complex Calculations (AREA)
- Memory System (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60043205A JPS61202246A (ja) | 1985-03-05 | 1985-03-05 | メモリアクセス制御方式 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60043205A JPS61202246A (ja) | 1985-03-05 | 1985-03-05 | メモリアクセス制御方式 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61202246A true JPS61202246A (ja) | 1986-09-08 |
| JPH0350298B2 JPH0350298B2 (enExample) | 1991-08-01 |
Family
ID=12657423
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60043205A Granted JPS61202246A (ja) | 1985-03-05 | 1985-03-05 | メモリアクセス制御方式 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61202246A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022164244A (ja) * | 2021-04-16 | 2022-10-27 | 株式会社リコー | メモリアクセス制御装置 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5757370A (en) * | 1980-09-22 | 1982-04-06 | Fujitsu Ltd | Access control system |
-
1985
- 1985-03-05 JP JP60043205A patent/JPS61202246A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5757370A (en) * | 1980-09-22 | 1982-04-06 | Fujitsu Ltd | Access control system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022164244A (ja) * | 2021-04-16 | 2022-10-27 | 株式会社リコー | メモリアクセス制御装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0350298B2 (enExample) | 1991-08-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4542455A (en) | Signal-processing multiprocessor system | |
| US3959775A (en) | Multiprocessing system implemented with microprocessors | |
| US4672536A (en) | Arbitration method and device for allocating a shared resource in a data processing system | |
| US5179705A (en) | Asynchronous arbiter state machine for arbitrating between operating devices requesting access to a shared resource | |
| US3943494A (en) | Distributed execution processor | |
| JPS6353678A (ja) | ベクトル処理装置 | |
| JPS62208158A (ja) | マルチプロセツサシステム | |
| EP0409285B1 (en) | Method and apparatus for data transfer between processor elements | |
| US4583162A (en) | Look ahead memory interface | |
| US5142682A (en) | Two-level priority arbiter generating a request to the second level before first-level arbitration is completed | |
| US4068214A (en) | Asynchronous logic array | |
| EP0295646B1 (en) | Arithmetic operation processing apparatus of the parallel processing type and compiler which is used in this apparatus | |
| JP2008181551A (ja) | ベクトルレジスタを備えたコンピュータにおけるベクトルテールゲーティング | |
| JPS6259495A (ja) | 通信接続スイッチの優先処理手順を修正する方法 | |
| US3710349A (en) | Data transferring circuit arrangement for transferring data between memories of a computer system | |
| USRE31287E (en) | Asynchronous logic array | |
| US4089052A (en) | Data processing system | |
| EP0081358A2 (en) | Data processing system providing improved data transfer between modules | |
| US3713109A (en) | Diminished matrix method of i/o control | |
| CN117112246B (zh) | 自旋锁的控制装置 | |
| JPS61202246A (ja) | メモリアクセス制御方式 | |
| US4803655A (en) | Data processing system employing a plurality of rapidly switchable pages for providing data transfer between modules | |
| EP0359192B1 (en) | Vector processors and vector register control | |
| GB2138182A (en) | Digital processor | |
| JP2538874B2 (ja) | 共通バス調停方式 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |