JPS6120153A - Memory access control device - Google Patents

Abstract

PURPOSE:To remove competition in the processing of requests by invalidating the succeeding requests by an invalidating means when the preceding request out of continuous requests outputted from the same requesting source is disabled to be processed in a buffer memory. CONSTITUTION:Requests are sent from requesting sources 10-12 to a memory access control device 20 on occasion. After adjusting the competition of the requests, the device 20 executes the processing of the requests. The device 20 is provided with a processing means 21, an index means 22, an invalidating means 23, a memory access means 24, and a buffer memory 25. When the preceding request can not be processed in the buffer memory 25 and access to a main memory 30 is generated, the succeeding requests are invalidated by the means 23, and after completing the access of the preceding request to the main memory 30, the processing of the succeeding requests is started.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buffer memory control device used in an information processing device. In particular, it relates to access control means for buffer memory.

[Conventional technology]

In conventional information processing devices, the buffer memory is first indexed in response to a data request from a request source such as a central processing unit or an input/output device, and if the requested data exists in the buffer memory, the buffer memory is accessed. and if the main memory does not exist, the main memory is accessed.

Therefore, if requests from the same request source are sent out consecutively, it can be determined that the preceding request is an access to the buffer memory, or if the request is an access to the main memory, the main memory Processing for the subsequent Nori Query 1 cannot be executed until the completion of access to is confirmed, so continuous processing cannot be executed even if all consecutively sent requests are accesses to the buffer memory. There were drawbacks.

[Problem that the invention seeks to solve]

SUMMARY OF THE INVENTION The present invention aims to eliminate the above-mentioned drawbacks, and aims to provide a buffer memory access device that can continuously process requests as long as they can be processed within the buffer memory, even if the requests are consecutive from the same request source.

[Means for solving problems]

The present invention provides a buffer memory connected to a main memory and a plurality of request sources that output requests related to data held in the main memory, and holding a part of the data held in the main memory; An index means for indexing the data held in the sofa memory, and based on the index result by this index means, if the data required by the request source is in the buffer memory, the buffer memory is accessed, and the data is stored in the buffer. A memory access control device is provided with a processing means for accessing the main memory when there is no memory in the memory, and as a means for solving the above-mentioned problem, a memory access control device is provided with a memory indexing means and an invalidating means connected to the processing means. and the processing means, when a new request arrives from the same request source before the index result of the index means is notified, makes the index result equivalent to accessing the buffer memory. means for initiating processing of said new request;
The present invention is characterized by comprising means for activating the invalidation means to invalidate the new request when it is notified that the index result is for accessing the main memory.

[Effect]

The processing means systematically processes requests that arrive consecutively from the same request source, assuming that the requests access the buffer memory, even if it is not yet known whether the requests access the buffer memory or the main memory. have it done. However, if it is found that the main memory is to be accessed, the invalidation means is activated to invalidate the process that has started. This process will be repeated again later.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of essential parts of an apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of FIG. 1 in detail.

In FIG. 1, numerals 10 to 12 indicate request sources such as a central processing unit and an input/output device, numeral 20 indicates a memory access control device, and numeral 30 indicates a main memory. Memory access system [1F20 is the processing means 21,
The apparatus includes an indexing means 22, a buffer memory 25, an ineffective means 23, and a memory access means 24, and this apparatus receives requests sent from requesters 10 to 12 and performs the processing requested by the requests. That is, in the processing means 21, the buffer memory 25 is indexed by the indexing means 22 in response to the received request, and the existence of data requested by this request in the buffer memory 25 is checked. If it exists in the buffer memory 25, the buffer memory 25 is accessed, and if it does not exist, the main memory 30 is accessed via the memory access means 24.

Further, the request sources 10 to 12 send requests to the memory access control device 20 at any time.
In the memory access control device 20, requests are processed in stages as requests conflict.

The processing means 21 of the memory access control device 20 executes processing for each request source, so if requests from different request sources occur consecutively, the subsequent requests will be processed continuously regardless of the processing of the preceding request. However, if requests from the same request source occur consecutively,
The address requested by the preceding request is buffer memory 2
5, the access time of the buffer memory 25 is about the same as the processing speed of the request, so the subsequent request is processed immediately; however, the data requested by the preceding request is
If the main memory 30 does not exist in the main memory 30, the main memory 30 is accessed via the memory access means 24, which takes a long access time, and subsequent requests are not processed until this access is completed.

Therefore, in the case of consecutive requests from the same request source, the processing of the subsequent requests must be waited until the index results of the indexing means 22 for the preceding requests are determined, making continuous processing impossible.

By the way, in the present invention, the ineffective means 23 is added as follows:
It is assumed that all requests from request sources 10 to 12 can be processed by the buffer memory 25, and even in the case of consecutive requests from the same request source, processing is continued regardless of the index result of the preceding request.
Continuous processing is performed as long as the requests from 0 to 12 can actually be processed in the buffer memory. However, when the preceding request cannot be processed in the buffer memory 25 and an access to the main memory 30 occurs, part of the processing of the subsequent request has already started, and this causes a conflict in processing, so the invalidation is disabled. The means 23 invalidates the subsequent request and stores the preceding request in the main memory 30.
The occurrence of this conflict is prevented by restarting the process after access to is completed.

Next, the detailed configuration of this embodiment device will be explained based on FIG. 2. This embodiment device 20 includes a processing means 21, an indexing means 22, an invalidating means 23, and a memory accessing means 2.
4 and a buffer memory 25, where the processing means 21 includes first to third buffer means 210 to 212,
Selection means 213 and first to third control means 215 to 2
]7.

The output of the first buffer means 210 is connected to the first input of the selection means 213, the output of the second buffer means 211 is connected to the second input of the selection means 213, and the third buffer means 212 is connected to the second input of the selection means 213. The output of the selection means 213 is connected to the input of the first control means 215, and the first output of the first control means 215 is connected to the first input of the second control means 2]6. a second output of the first control means 215 is connected to an input of the indexing means 22; a first output of the indexing means is connected to a second input of the second control means 216; The output of the disabling means 23 is connected to the input of the disabling means 23, and the output of the disabling means 23 is connected to the second control means 2.
16, the first output of the second control means 216 is connected to the input of the buffer memory 25, and the second output of the second control means 2+6 is connected to the second input of the third control means 217. a third output of the second control means 216 is connected to an input of the memory access means 24; an output of the buffer memory 25 is connected to a first input of the third control means 217; The output of the main memory 30 is connected to the input of the main memory 30, and the output of the main memory 30 is connected to the second input of the buffer memory 25 and the third control means 21.
7, and the output of the third control means 217 is connected to the input of the first requester 10, the input of the second requester 11 and the input of the third requester 12, The output of the second request source 11 is connected to the input of the second buffer means 211, and the output of the third request source 12 is connected to the input of the first buffer means 210.
connected to the input of

Next, the operation of this embodiment device will be explained based on FIG. 2. Requests from the first to third request sources 10 to 12 are stored in the first to third buffer means 210 to 212 corresponding to the respective requests, and are sent to the selection means 2]3, which selects a predetermined number. One of the Nori quests is selected based on the conditions. Now, when requests are successively selected by the selection means 213, the first request that passed through the selection means 213 in advance is sent to the first control means 215, and this request causes the indexing means 22 to buffer the requests. An index for the memory 25 is executed and sent to the second control means 216 together with the index result. In the processing after the first control means 215, all requests selected by the selection means 213 are processed on the assumption that they can be processed within the buffer memory 25, so the second request following the first request is At the same time as the request is received by the second control means 216, it is received by the first control means 215, and the indexing of the buffer memory 25 by the indexing means 22 is started.

If the buffer memory 25 can process the data based on the index result related to the first request, the buffer memory 25 is accessed by the first request, and the data is sent to the request source via the third control means 217. Ru. Also, based on this index result, the buffer memory 25
If processing is not possible, an access request is sent to the main memory 30 via the memory access means 24. Since accessing the main memory 30 takes a long time compared to accessing the buffer memory 25, the first request is held by the memory access means 24 until the data in the main memory 30 is accessed, and then the main memory 3
When data is sent from 0, the data is sent to the buffer memory 25 and also sent to the request source of the first request via the third control means 217.

On the other hand, if the first request can be processed within the buffer memory 25, the buffer memory 25 is accessed by the first request and information in the buffer memory 25 is sent to the third control means 217, and at the same time the second request is processed. The request is sent to the second control means 216, and the main memory 30 is accessed via the buffer memory 25 or the memory access means 24 based on the index result of the second request.

Next, the first request cannot be processed by the buffer memory 25 and is sent to the main memory 3 via the memory access means 24.
0, and if the second request is output from the same request source as the first request, the main memory 30
At the time when it is determined that access is necessary, the ineffective means 23 invalidates the second request that has already been accepted by the first control means 215 and has started indexing the buffer memory 25, and Second control means 216 for requests
The selection means 213 will not make any selection until the main memory access for the first request is completed, and the request processing will be in a waiting state.

Next, when the access to the main memory 30 is completed, reading from the buffer means 210 to 212 is started again, and the second request is accepted by the first control means 215 by the selection means 213, and the request processing is restarted.

〔Effect of the invention〕

As explained below, the present invention disables the subsequent request by invalidating the subsequent request by the invalidating means when the preceding request of consecutive requests from the same request source cannot be processed in the buffer memory. Processing conflicts between requests and subsequent requests are avoided, and therefore consecutive requests from the same requester can be processed as long as they can be processed in the buffer memory. In general request processing, which has a high probability of being processed in , it has the effect of being able to process most requests in succession.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of main parts of an apparatus according to an embodiment of the present invention. FIG. 2 is a block configuration diagram showing the detailed configuration of the apparatus according to the embodiment of the present invention. DESCRIPTION OF SYMBOLS 10-12... Request source, 20... Memory access control device, 21... Processing means, 22... Indexing means, 2
3... Invalidation means, 24... Memory access means,
25...Buffer memory, 30...Main memory,
210-212... Buffer means, 213... Selection means, 215-217... Control means.

Claims (1)

[Claims] (1) A buffer memory that is connected to a main memory and a plurality of request sources that output requests related to the data held in the main memory, and that holds part of the data held in the main memory; an indexing means for indexing the data held in the memory; and, based on the indexing result by this indexing means, if the data required by the request source is in the buffer memory, the buffer memory is accessed, and the data is stored in the buffer memory. and a processing means for accessing the main memory when the main memory is not available, further comprising an invalidating means connected to the indexing means and the processing means, the processing means notifying the index result of the indexing means. When a new request arrives from the same request source before the index result is accessed, a means for starting processing of the new request in a state equivalent to accessing the buffer memory; A memory access control device comprising means for activating the invalidation means to invalidate the new request when it is notified that the new request is to access memory.