JPS61198911A - Switched capacitor filter - Google Patents

Switched capacitor filter

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Publication number
JPS61198911A
JPS61198911A JP3917085A JP3917085A JPS61198911A JP S61198911 A JPS61198911 A JP S61198911A JP 3917085 A JP3917085 A JP 3917085A JP 3917085 A JP3917085 A JP 3917085A JP S61198911 A JPS61198911 A JP S61198911A
Authority
JP
Japan
Prior art keywords
noise
capacitor
circuit
switched capacitor
switches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3917085A
Other languages
Japanese (ja)
Inventor
Kenji Nakayama
謙二 中山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3917085A priority Critical patent/JPS61198911A/en
Publication of JPS61198911A publication Critical patent/JPS61198911A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To process a signal having various signal speeds at a low output noise by connecting a circuit having a switch and a capacitor operated at a frequency MfS (1<M) to an input terminal or an output terminal of an operational amplifier. CONSTITUTION:The circuit having the switches 101, 102 and the capacitors 103, 104 operated at a frequency MfS (1<M) is connected to an input terminal or an output terminal of the operational amplifier 3. The switches 101, 102 are driven by clocks phi10 and phi20. M-set of sample values are added to the capacitor 103 at one period of the clocks phi1, phi2 with respect to noise component. M-set of noise samples are added also to the capacitor 104 and averaged. Thus, the signal having various signal speeds is processed with low output noise.

Description

【発明の詳細な説明】 本発明はスイッチトキャパシタフィルタに関する。[Detailed description of the invention] The present invention relates to switched capacitor filters.

従来のスイッチトキャパシタフィルタ(以下SCFと略
す)の構成を第1図(a)に示す。図において、参照数
字1【および12はスイッチであり、それぞれ第1図←
)に示すクロックφ、およびφ2が高レベルのとき閉じ
、低レベルのとき開く。このように、スイッチが周期的
に開閉を繰り返してSCFは動作する。このスイッチの
開閉によシミ圧(電荷)が標本化されて各キャパシタに
蓄えられる。従って、SCFは標本化された信号を処理
するサンプル系フィルタを構成する。5CFK:用いら
れている演算増幅器3は雑音を発生する。これは主にl
/f雑音と白色雑音とからなる。この白色雑音は高周波
数帯域にまでのびており、これがSCF内部の標本化に
よシ基本周波数帯域に折り返って増幅されるという問題
がある。この様子を第2図に示す。同図(a)が演算増
幅器の出力雑音fと電カスベクトルPとの関係を示し、
同図Φ)が標本化周波数f、で標本化されたときの電カ
スベクトルを示す。出力雑音の帯域幅をf・ とすると
、同図(b)におけるKFif@/fsとなる。すなわ
ら、雑音電力としてはl Oflog (f、/f、 
) dBだけ増幅される。一方、実際のスイッチは閉じ
た状態でオン抵抗は零ではなく通常lO〜30(KΩ)
程度である。このオン抵抗とキャパシタとが1次低域通
過フィルタ(LPF”)を形成し、第2図(a)のfc
 が等測的に下がることになり、Kの値も小さくなる。
The configuration of a conventional switched capacitor filter (hereinafter abbreviated as SCF) is shown in FIG. 1(a). In the figures, reference numerals 1 and 12 are switches, respectively in Figure 1 ←
) is closed when the clocks φ and φ2 are at high level, and opened when the clocks are at low level. In this way, the SCF operates by periodically repeating opening and closing of the switch. By opening and closing this switch, the stain pressure (charge) is sampled and stored in each capacitor. Therefore, the SCF constitutes a sample-based filter that processes the sampled signal. 5CFK: The operational amplifier 3 used generates noise. This is mainly l
/f noise and white noise. This white noise extends to a high frequency band, and there is a problem in that it is reflected back to the fundamental frequency band and amplified by sampling inside the SCF. This situation is shown in FIG. Figure (a) shows the relationship between the output noise f of the operational amplifier and the electric waste vector P,
The figure Φ) shows the electric scum vector when sampled at the sampling frequency f. Letting the bandwidth of the output noise be f., it becomes KFif@/fs in FIG. 2(b). In other words, the noise power is l Oflog (f, /f,
) is amplified by dB. On the other hand, the on-resistance of an actual switch in the closed state is not zero, but is usually lO~30 (KΩ).
That's about it. This on-resistance and the capacitor form a first-order low-pass filter (LPF), and fc
will decrease isometrically, and the value of K will also decrease.

従って、フィルタ出力における雑音を低減するためにス
イッチのオン抵抗を大きくシタク、f、そのものを低く
<シたシする方法が考えられる。しかし、例えば、檀々
の帯域の信号を処理する場合、これらのパラメータは最
も高い帯域の信号に対して選択する必要があり、その場
合、最も低い帯域の信号に対して標本化周波数f、を下
げて処理する場合は当然に= f、/f、が大きくなる
Therefore, in order to reduce the noise in the filter output, a method can be considered in which the on-resistance of the switch is increased and f itself is decreased. However, for example, when processing signals in various bands, these parameters need to be selected for the highest band signals, and in that case, the sampling frequency f, should be selected for the lowest band signals. When processing is performed with a lower value, =f, /f naturally becomes larger.

本発明の目的は種々の信号速度を有する信号を低出力雑
音で処理できるSCFを提供することにある。
An object of the present invention is to provide an SCF that can process signals having various signal speeds with low output noise.

本発明のSCFは、複数のスイッチ、キャパシタおよび
演算増幅器から構成され標本化周波数f。
The SCF of the present invention is composed of a plurality of switches, capacitors, and operational amplifiers, and has a sampling frequency f.

で動作するスイッチトキャパシタフィルタにおいて、前
記演算増幅器の入力端子または出力端子に周波数Mfs
 (L<M )で動作するスイッチおよびキャパシタを
有する回路を接続しである。
In a switched capacitor filter that operates at
A circuit having a switch and a capacitor operating at (L<M) is connected.

次に本発明について図面を参照して詳細に説明する。Next, the present invention will be explained in detail with reference to the drawings.

第3図は本発明の一実施例を示す回路図であり、第4図
(a)は本実施例に用いる高速積分器201および20
2の詳細を示す回路図である。
FIG. 3 is a circuit diagram showing one embodiment of the present invention, and FIG. 4(a) shows high-speed integrators 201 and 20 used in this embodiment.
FIG. 2 is a circuit diagram showing details of No. 2;

第4図(a) において、スイッチ101および102
は同図(b)に示すクロックφ1oおよびφ2oによシ
駆動され、その周波数はMfs(Mal)である。キャ
パシタ103には雑音成分に関してφ1およびφ2の1
周期に2いてM個の標本値が加算される。
In FIG. 4(a), switches 101 and 102
is driven by clocks φ1o and φ2o shown in FIG. Capacitor 103 has 1 of φ1 and φ2 for noise components.
M sample values are added every 2 cycles.

また、この積分器の出力側に接続されるキャパシタ10
4にもM個の雑音標本値が加算されて平均化される。
In addition, a capacitor 10 connected to the output side of this integrator
M noise sample values are also added to 4 and averaged.

第3図において、スイッチ11が閉じている間はキャパ
シタ22.26′&よび27に雑音成分が加算される。
In FIG. 3, noise components are added to capacitors 22, 26' and 27 while switch 11 is closed.

積分キャパシタ103においてもその出力が標本化され
るまでの間において雑音成分が加算される。従って、ク
ロックφ1およびφ2で標本化される信号中に含まれる
雑音成分はM個またはM72個の標本値の和となってお
シ、平均値化により無相関雑音が低減される。第5図は
第3図の8CFの等価回路である。これから定性的に言
えることは、抵抗とキャパシタとを有する一次LPFで
高域の雑音成分が抑圧され、周波数f。
Noise components are also added to the integrating capacitor 103 until its output is sampled. Therefore, the noise component contained in the signal sampled by the clocks φ1 and φ2 becomes the sum of M or M72 sample values, and uncorrelated noise is reduced by averaging. FIG. 5 is an equivalent circuit of 8CF shown in FIG. What can be said qualitatively from this is that high-frequency noise components are suppressed by the primary LPF having a resistor and a capacitor, and the frequency f.

で標本化する場合の折返し成分が低減されるということ
でおる。この場合、等価抵抗1はSC回路で構成され、
実際の抵抗よりも高精度で実現することが可能である。
This means that the aliasing component when sampling is reduced. In this case, the equivalent resistance 1 is composed of an SC circuit,
It is possible to achieve higher precision than actual resistance.

以上、本発明には、80Fの出力雑音の低減を達成でき
るという効果がある。
As described above, the present invention has the effect of achieving a reduction in output noise of 80F.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図6)および[有])はそれぞれ従来のSCFを示
す回路図およびクロック信号を示す波形図、第2図(a
)および(b)は従来のSCFの欠点を説明するたおよ
びクロック信号を示す波形図、第5図は第3図の等価回
路を示す回路図である。 図において、l・・・・・・等価抵抗、3・山・・演算
増幅器、4・・・・・・入力端子、5・・・・・・出力
端子、11゜12、 101.102・・・・・・スイ
ッチ、103,104゜22.23,24,26,27
.28・・・・・・キャパシタ、201,202・・・
・・・積分器。 を 代理人 弁理士  内 原   晋(。 ≦公 ジ ぼ
Figure 1 (a) and (a) are a circuit diagram showing a conventional SCF and a waveform diagram showing a clock signal, respectively.
) and (b) are waveform diagrams illustrating clock signals and for explaining the drawbacks of the conventional SCF, and FIG. 5 is a circuit diagram showing an equivalent circuit of FIG. 3. In the figure, l...Equivalent resistance, 3...Operation amplifier, 4...Input terminal, 5...Output terminal, 11°12, 101.102... ...Switch, 103,104゜22.23,24,26,27
.. 28... Capacitor, 201, 202...
...integrator. is represented by patent attorney Susumu Uchihara (.

Claims (1)

【特許請求の範囲】[Claims] 複数のスイッチ、キャパシタおよび演算増幅器から構成
され標本化周波数f_sで動作するスイッチトキャパシ
タフィルタにおいて、前記演算増幅器の入力端子または
出力端子の少なくとも一方に周波数Mf_s(1<M)
で動作するスイッチおよびキャパシタを有する回路を接
続したことを特徴とするスイッチトキャパシタフィルタ
In a switched capacitor filter that is composed of a plurality of switches, capacitors, and operational amplifiers and operates at a sampling frequency f_s, a frequency Mf_s (1<M) is applied to at least one of the input terminal or output terminal of the operational amplifier.
1. A switched capacitor filter, characterized in that a circuit having a switch and a capacitor that operates is connected to each other.
JP3917085A 1985-02-28 1985-02-28 Switched capacitor filter Pending JPS61198911A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3917085A JPS61198911A (en) 1985-02-28 1985-02-28 Switched capacitor filter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3917085A JPS61198911A (en) 1985-02-28 1985-02-28 Switched capacitor filter

Publications (1)

Publication Number Publication Date
JPS61198911A true JPS61198911A (en) 1986-09-03

Family

ID=12545642

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3917085A Pending JPS61198911A (en) 1985-02-28 1985-02-28 Switched capacitor filter

Country Status (1)

Country Link
JP (1) JPS61198911A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007164007A (en) * 2005-12-16 2007-06-28 Hitachi Ltd Optical element having free curved surface, and projective optical unit including the optical element or projection type image display apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007164007A (en) * 2005-12-16 2007-06-28 Hitachi Ltd Optical element having free curved surface, and projective optical unit including the optical element or projection type image display apparatus

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