JPS61198820A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To attain ADC with high accuracy by utilizing the result of the 1st path conversion so as to re-adjust the gain of an amplifier and applying the 2nd path conversion in the range from a half of ADC to the full scale with respect to the amplified signal. CONSTITUTION:The ADC consists of a timing controller 70, a sample and hold circuit 80, an amplifier 90, an ADC 100, a latch/encoder 120 and a decoder/driver 125. The ADC generates a digital output signal with a form of MX2N, where M is a mantissa of binary notation, i.e., a proportional part and N is an exponent in binary notation with respect to base 2. An analog signal is stored in the sample and hold circuit 80, and the gain of the variable gain amplifier 90 is varied from 0dB to 42dB at an interval of 6dB. The gain is set to 0dB at the start of analog/digital conversion of the analog signal, the ADC 100 applies the 1st path, 8-bit conversion to obtain a digital estimated value of the analog input level, and the 8-bit estimated value is used to address a ROM reference table of the encoder 120.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to an analog-to-digital converter that converts an analog signal into a digital signal.

[Prior art]

In a typical residue class analog-to-digital converter (ADC), an analog input signal is converted into a highly approximate digital signal by repeating approximation conversion operations in successive "passes," that is, virtually continuously in time.・Converted to word. In the conventional ADC of FIG. 2, during the first pass, the ADCIO converts the analog input, signal stored in the sample and hold 8 and received via the amplifier 9, into a number of digital bits. is stored in latch 12. During the second pass, a digital-to-analog converter (DAC) 14 converts the approximation of the first pass back to an analog signal, which is transferred to junction 15.
is subtracted from (i.e., negatively added to) the input signal. The remainder of the difference represents the error in the first pass transformation. During the second pass conversion, the remainder received from the amplifier 16, whose gain is set to 12R, is converted to fractional bits at the ADCIO and combined with the first pass conversion at the latch 12 to further convert the input signal. Create accurate approximations. More than one pass can be performed, each producing an arbitrary bit value.

In the redundant ADC of FIG. 2, successive passes improve the linearity of the converter to the accuracy limits of the DAC 14.

In this way, linearity can be further improved by performing three or more buses, if allowed by the signal conversion time and the accuracy of the DAC 14.

For floating point ADCs, see Electronic Design, September 6, 1984.
"Floating point ADCJ with hardware configuration to obtain 20-bit dynamic range" announced in
It is stated in a paper titled. This ADC uses a "fluffy type automatic range controller" with an encoder to set the gain of an amplifier whose gain is programmable after the first pass, as shown in FIG.

[Purpose of the invention]

An object of the present invention is to provide a highly accurate ADC.

[Summary of the invention]

The ADC of the present invention uses the results of the first pass conversion to readjust the amplifier gain. Next, a second pass conversion is performed on the amplified signal in the range from 1/2 to full scale of the ADC.

The present invention eliminates the high precision DAC in the feedback loop, which speeds up the conversion since only a small number of first pass bits are converted and stored and not further reconverted or processed. will improve. AD of the present invention
C can convert a wider range of signals than traditional ADCs. In conventional ADCs, even if you sacrifice some potential accuracy for high-level signals,
Due to technical limitations in its components, similar conversion speeds cannot be achieved.

〔Example〕

As shown in FIG. 1, the ADC of the present invention includes a timing controller 70. Sample and hold circuit 80. Amplifier 90.
It consists of ADCloo, a latch/encoder 120°, and a decoder/driver 125.

Input resistors R0 through RN are selected after selecting Ro according to the recursive relationship shown below.

(A) S+ = R.

(2R6+S= ) However, 1≦i<n (n is the number of range steps) (C)S!
+l = 86 +R6 The last resistor R, is (D)R, = 2RO-3N S is the corresponding switch.

The values of these resistors are used to set the gain of amplifier 9o over the range 1 to 21-1 in octave steps by closing switches S, -SN.

The ADC according to the invention generates a digital output signal of the form M X 2 N, where M is the mantissa, or proportional part, in binary representation and N is the exponent in binary representation to base 2.

Referring again to FIG. 1, an analog signal is stored in sample and hold circuit 80. The gain of the variable gain amplifier 90 is variable from OdB to 42dB in 6dB steps. At the start of analog-to-digital conversion of an analog signal, the gain is set to the initial OdB and the AD
Cloo performs a first pass, 8-bit conversion to obtain a digital estimate of the analog input level. This 8-bit estimate is then used to address the encoder 120 ROM lookup table. The output of encoder 120 is used to set the amplifier 90 gain to the optimum value via decoder 125. This value is selected so that the level of the human input signal to ADCloo is as close to positive or negative full scale as possible without exceeding full scale. ADCloo then performs a more accurate 12-bit conversion.

The result of the 12-bit conversion represents the mantissa and the gain setting of amplifier 90 represents the binary exponent. As shown in FIG. 1, the result of the 12-bit conversion is multiplied by the reciprocal of the gain of amplifier 90, ie, 1/G, by amplifier 110.

This is analogous to multiplying by binary exponents, and AD
Complete by adding appropriate zeros to the 12-bit result obtained from Cloo. This technique provides accuracy better than ±0.02 dB and dynamic range of 1
8 with a resolution of 0.004 dB, greater than 0.00 dB.
An analog-to-digital converter is obtained that performs at kHz speeds. Resolution is improved to better than 0.001 dB by averaging over multiple samples with noise present.

Amplifier 90 consists of a standard inverting amplifier, the gain of which is varied by controlling the position of the summing junction relative to the resistor network on and off of a FET switch. Only one of the FETs is always "on" at any given time. Resistors R0-R.

The sequential addition to the left of the FETs that are "on" corresponds to the input resistors of the inverting amplifier, and resistors R0 to R
The sequential addition to the right of the FETs that are "on" up to 8 corresponds to their feedback resistors.

The resistor network is patterned in a thin film of tantalum nitride. The thin film resistors are ratio trimmed to ±0.02% to provide the desired analog-to-digital conversion linearity. Guarding techniques and low leakage FETs are used in amplifier 90 to prevent leakage currents from adding to the amplifier and introducing nonlinearity.

Resistor R, is only switched into the circuit when performing the first pass 8-bit estimation of the input signal level. As discussed elsewhere in this specification, this estimation is done with the gain of the preconditioning amplifier set to 1 (OdB). To provide some margin for the 8-bit estimate, the amplifier gain is actually set to 1.1 by switching R9 in parallel with the effective input resistor. This 10% margin allows the input signal to the ADC100 to
When choosing the optimal gain value for a 2-bit conversion from an 8-bit estimate, full scale is not exceeded.

During the first bus conversion, the ADC 100 converts the analog signal received from the amplifier 90 to the highest binary encoded exponent, which does not overflow from the mantissa as shown in Appendix 1 below. do not have.

Appendix I ADC output signals Encoded exponent (2's complement) (negative, binary value) 01XXXXXX-00
0 10XXXXXX-000 001XXXXX-001 110XXXXX-001 0001XXXX-010 1! 10XXXX-010 00001XXX-011 11110XXX-011 000001XX-100 111110XX-100 0000001X-101 1111110X-101 The second bus conversion generates a mantissa, which is combined with the exponent in latch 120 to produce an output in the form of MX2" create a signal .

4A to 4D are detailed circuit diagrams of the analog-to-digital converter of the present invention. FIG. 4 is an assembled view of FIGS. 4A-4D. 4A-4D, the sample and hold circuit 80 is shown at a rate of 8 kllz at an IF of 10 kHz.
is sampled. This sampling operation is 10kHz
z IF to a 2 kHz digital IF. The 2 kHz signal is a stepped output signal.

Variable gain amplifier 90 is a programmable 8-bit
It is a radical amplifier whose gain can be varied between 1 and 128 in octave steps. The gain of amplifier 90 is set by ADCloo. First, ADCloo sets the gain of amplifier 90 to 1.1 and performs 8-bit conversion. The conversion value is then used to convert the input voltage to the amplifier 9.
Program as close as possible to the full scale input signal level of the zero gain ADC 100. In this way, amplifier 90 provides seven more bits of dynamic range to ADCloo.

ADCloo is 2 from the sample and hold circuit 80.
A 2 kHz analog staircase signal is converted into a 2 kHz digital I
Convert to F. After first setting the gain of variable gain amplifier 90 with 8-bit conversion, ADCloo performs 12-bit conversion on the amplified signal. This 8-bit/12-bit cycle is repeated for each stepped signal for the digital 2 kHz IF signal.

The rat/encoder 120 stores the optimal gain settings in half of the ROM (AlU8) for a given 8-bit conversion. The other half of AlU3 generates the number of zeros to be added to the result of the digital filter 12-bit conversion.

The right-angle digital filter 140 includes a digital mixer and converts the output signal value from ADCloo to 2 kHz.
digitally mixed with the signal and processed.

One of the mixers is fed what is equal to a 2 kHz sine wave, and the other is fed a cosine wave. The output signal of filter 140 is a digital representation of the "real" and "imaginary" components of the human input.

Timing controller 70 is used to interrupt operation of the algorithm state machine. The algorithm test machine is a ROM-based state machine that stores the current state and qualifiers.
) information and are provided with latches U31 and U32 for use by ROM U3 to determine the next state. Multiplexer U1 determines which qualifier to use in making the decision.

The decoder 125 transfers the state information to the FET of the amplifier 90.
Decodes into various control signals that operate switches. The input/output boat 130 converts the output signal of the ADC 100 into 1/
It is provided with an inverting amplifier U 28a that amplifies by G.

〔Effect of the invention〕

According to the present invention, highly accurate A/D conversion can be performed in a relatively short time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an analog-to-digital converter of the present invention. FIGS. 2 and 3 are block diagrams of conventional analog-to-digital converters. 4A to 4D are detailed circuit diagrams of the analog-to-digital converter of the present invention. FIG. 4 is an assembly diagram of FIGS. 4A to 4D. 70: Timing controller 6 80: Sample and hold circuit. 90: Amplifier. 100: ADC. 110: Amplifier. 120: Latch/encoder. 125: Decoder/driver. Applicant Yokogawa Huylett Packard Co., Ltd. Agent Patent Attorney Hasegawa “Second Son Proceedings Amendment Form” February 19, 1986

Claims (1)

[Claims] sample and hold means for sampling and holding an input signal; variable gain amplification means for amplifying the signal from the sample and hold means; and A/D conversion means for A/D converting the signal from the variable gain amplification means. , and control means for changing the gain of the variable gain amplification means based on the signal from the A/D conversion means.