JPH01241223A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To obtain a digital output with high resolution by arranging two analog digital converters(ADCs) in parallel, providing one ADC with an amplifier to the pre-stage and an attenuator to the post-stage, and using the output of two systems selectively. CONSTITUTION:A 1st ADC 12 AD-converts an input analog signal. Moreover, the input signal is amplified by an amplifier 13 at a multiple of (d) and then supplied to a 2nd ADC 14. A digital signal subject to AD conversion by the 2nd ADC 14 is attenuated to 1/alpha by an attenuator 15. On the other hand, the digital output of the ADC 12 is compared with a level AS set by a level detector 16, and the resulting signal is outputted. The output of the ADC 12 and the output of the attenuator 15 are fed to a changeover device 17, by which one of the outputs is outputted depending on the output of the level detector 16.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to an analog-to-digital converter used in digital audio equipment and the like.

BACKGROUND OF THE INVENTION In recent years, audio equipment has become increasingly digital. In order to digitally process audio signals, an analog-to-digital converter (hereinafter referred to as ADC) is required.

ADCs for audio signals are required to have a resolution of 16 bits or more, and in response to this requirement, various attempts have been made to improve the performance of ADCs.

On the other hand, using an ADC with a resolution of less than 16 binoto,
There is an ADC device that attempts to obtain a pseudo resolution of 16 binoto or more by amplifying an analog input signal and attenuating a digital output signal. A conventional ADC device will be described below with reference to the drawings.

FIG. 6 is a 174-component block diagram of a conventional ADC device. In FIG. 5, 51 is an analog signal input terminal 5.
2 is an amplifier that amplifies the analog signal according to the controller/1/ signal; 53 is an attenuator that converts the output signal of the amplifier 62 into a digital signal; ADC 154 is an attenuator that attenuates the digital output signal of the ADC 53 according to the control signal; A level detector outputs a load signal corresponding to the analog input signal level to control the amplifier 62 and the attenuator 64, and 5e is a digital signal output terminal that outputs the output of the attenuator.

The operation of the ADC device configured as described above will be described below.

FIG. 6 is an input/output characteristic diagram of a conventional ADC.

In the figure, a digital signal of Dmln is output for an analog input signal of Am1n or less. For analog input signals from Amiyu to A□engineering, a digital signal proportional to the input is output. For analog inputs greater than or equal to Amax, a constant digital signal is output from Dma. Therefore, in conventional ADC systems, analog input signals below a certain level are amplified and input to the ADC, and after becoming a digital signal, they are attenuated.
The resolution of ADC is increased.

First, the analog input signal is input to the level detector 66. The level detector 55 compares a preset level vAB with the analog input signal, and outputs the result as a control signal to the amplifier 62 and attenuator 54.

The amplifier 52 receives an analog input signal, and depending on the control signal from the level detector 65, the analog input signal becomes level /l/Al! When it is smaller, it is amplified six times,
When the analog input signal is above the level (V A s), it is output as is. The output of the amplifier 52 is converted into a digital signal by the ADC 53 and input to the attenuator 64. Attenuator 6
4 attenuates the input digital signal to 1/a according to the control signal from the level detector 53 when the analog input signal is less than the level /V A s; When , it is output as is. The output of attenuator 54 is output to digital signal output terminal 66 as the output of the ADC system.

By the way, the level As and the amplification factor α must satisfy equation (1).

A, <As-a≦A, a>1
-・-(1)mx)1m
aw Furthermore, if the attenuator 54 is realized by bit shifting,
Since the circuit is simple, α=2" n=1.2.3...
- (2) is practical.

Problems to be Solved by the Invention However, in the above configuration, since the level detector and the amplifier are implemented by analog circuits, there is a problem in that it is not possible to follow steep changes in the analog signal. For example, a system sampling at 48 K) lz must output data every 20.8 μs. In order to complete level detection, amplifier switching, and AD conversion during this time, high-speed elements are required.

Furthermore, this time will be even shorter if an oversampling ADC is used. If the operating speed of the analog circuit is insufficient, the amplification factor of the amplifier 52 cannot be switched in time, resulting in a phenomenon called blazing, which deteriorates sound quality.

In view of the above problems, the present invention provides a high-resolution ADC device that does not depend on the operating speed of analog circuits.

Means for Solving the Problems In order to solve the above problems, the present invention includes a first ADC that directly converts an analog input signal into a digital signal, an amplifier that amplifies the analog input signal six times, and an output of the amplifier. a second ADC that converts into a digital signal; an attenuator that attenuates the output of the second ADC to 1/a;
A preset level of the output of the first ADC) V
A level detector that compares A s with A s and outputs the result; and a level detector that inputs the output of the tenth ADC and the output of the attenuator;
If the output of C is above the set value, the output of the first ADC is
It is comprised of a switch that outputs an attenuator output when the first ADC output is less than a set value.

Effect of the Invention With the above-described configuration, the present invention performs level detection using a digital signal, and by making the amplification factor of the amplifier constant, it is possible to output a high-resolution digital signal regardless of the operating speed of the analog circuit. Make it.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of an ADC device in an embodiment of the present invention. In FIG. 1, 11 is an analog signal input terminal, 12 is a first ADC 113 is an amplifier that amplifies the analog signal by α times, 14 is a second ADC that converts the output of the amplifier 13 into a digital signal, and 1s is a second ADC ADCl4 of
16 is an attenuator that reduces the digital signal to 1/a, 16 is the output of the first ADC and a preset ratio) V A s
A level detector 17 inputs the output of the first ADC and the output of the attenuator 15, and outputs the result when the output value of the first ADC≧AsO. , a switch that outputs the output of the attenuator 15 at other times,
18 is a digital signal output terminal.

The operation of the ADC device configured as described above will be described below.

FIG. 2 is an input/output characteristic diagram of the ADC. Therefore, in the ADC device of the present invention, two ADCs are used, and the first ADC
l2 converts the input signal directly into AD. Second ADC
l4 AD converts the input signal multiplied by α, multiplies the digital output by 1, detects the level from the output signal of the first ADC, and converts one of the digital signals to A.
This is the output of the DC device.

First, the first ADCl 2 converts the input analog signal into an AD
Convert. Further, the input signal is amplified by α times by the amplifier 13 and inputted to the second ADCl 4.

The digital signal AD-converted by the second ADC is attenuated by the attenuator 16. On the other hand, the digital output of the first ADC is compared with a preset value /V A s by a level detector 16, and the result is output.

The output of the first ADCl 2 and the output of the attenuator 16 are input to a switch 17, and one of them is output depending on the output of the level detector 16. That is, the output value of the first ADCl2≧
At the time of A9, the output of the first ADCl 2 is the output of the first ADCl 2.
Output value of Cl2 (when As, output of attenuator 13 is ADC
The signal is output from the digital signal output terminal 18 as an output of the system.

FIG. 3 shows the input to the analog signal input terminal 11 and the input to the first
The input/output characteristics of the ADC and the digital output of the second ADCl4 are shown. The first ADC has the same characteristics as the ADC shown in FIG. The second ADC receives the signal multiplied by α from the amplifier 2 at the previous stage. Therefore, while the output of the second ADC increases linearly up to the input of the first ADC1, the output of the second ADC14 is Amax2=
When AvQax1/a or more, a constant value of D is output. Anti-m&X On the other hand, the first ADCl2 is a constant value D below Atn1n1
, whereas the second ADCl4 maintains linearity until ln Am1n2=A111ax/α.

FIG. 4 shows the input/output characteristics of the ADC device of the present invention. AX
The part shown by the solid line from na engineering 1 to As is the 1st (7)
The output of the ADC, the part shown by the broken line from As to Am1n2, is the output of the second ADC14. //It is multiplied by a.

As described above, according to this embodiment, the second ADC, which has a 4x amplifier in the front stage and a 17a attenuator in the rear stage, is connected to the first ADC.
By installing the ADC on the north side and switching the outputs of both, it is possible to realize an ADC device with a wide dynamic range by 201og α (dB), that is, a high resolution ADC device. In this embodiment, the amplification factor of the amplifier 13 is constant, and the level detector 16 and the switch 1a are connected to the digital /L/(
Il! Since it is a circuit, the speed of analog circuits is not an issue as in the conventional example. Therefore, it can also be applied to oversampling type ADCs.

Note that in this embodiment, the level detector may have hysteresis characteristics. If there is an offset in the ADC or amplifier, or if the characteristics of the amplifier and attenuator do not match, noise will be generated when the switch performs switching. If a switch without hysteresis is used, and a large amplitude sine wave is input, switching will be performed four times during a - period, which may generate a lot of noise.

In such a case, if the level detector has hysteresis characteristics, it will be possible to always select the output of the first ADC while the amplitude of the input signal is large, and noise generation will be reduced.

Effects of the Invention As described above, the ADC device of the present invention has two ADCs arranged in parallel, one ADC has an amplifier in the front stage and an attenuator in the rear stage, and the output of the two systems is switched and used. , high-resolution digital output can be obtained. Furthermore, since the analog circuit does not require high-speed operation, it can also be applied to an oversampling link type ADC.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an ADC device in an embodiment of the present invention, FIG. 2 is an input/output characteristic diagram of the ADC, and FIG.
The figure shows a first ADC, a second ADC, and a second ADC in an embodiment of the present invention.
FIG. 4 is an input/output characteristic diagram of the ADC system according to an embodiment of the present invention, and FIG. 5 is a diagram of the conventional AD
A block diagram showing the configuration of the C device, Fig. 6 is a conventional ADC.
FIG. 3 is an input/output characteristic diagram of the device. 11.61...Analog signal input terminal, 12゜14.53...Analog-digital conversion "Hl"
l 3゜52...Amplifier, 15, 54...
...Attenuator, 16°55...Level detector,
17...Switcher, 18°56...Digital signal output terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure A 10, Heka Ug4i'' Level Figure 3

Claims (1)

[Claims] a first analog-to-digital converter; a second analog-to-digital converter arranged in parallel with the first analog-to-digital converter and provided with an amplifier with an amplification factor of a in the front stage and an attenuator with an amplification factor of 1/a in the rear stage; a level detector that compares the output of the first analog-to-digital converter with a preset value; and an output of the level detector that inputs the output of the first analog-to-digital converter and the output of the attenuator. Depending on the result, if the output of the first analog-to-digital converter is greater than or equal to the set value, the output of the first analog-to-digital converter is output, and if the output of the first analog-to-digital converter is less than the set value, the output is An analog-to-digital converter comprising: a switch for outputting the output of the attenuator.