JPS61196638A - Data transmission system - Google Patents

Abstract

PURPOSE:To make the constitution of a terminal station simple and to improve the using efficiency of a bus line by counting the presence and the absence of a transmitting signal on the bus line, comparing counting results with the address of respective terminal stations, and at the time of coincidence, executing the data transmission from the terminal station corresponding to this to the central processing device, and at the time of dissidence, continuing the data transmission from the terminal station. CONSTITUTION:When the data transmission is completed from a terminal station ST1', the output of a carrier detecting circuit 1 goes to be L, one of counters 2 in terminal stations ST', ST2' and ST3'... is counted up and the contents are n+1. Next, by the same procedures, the data transmission from the terminal station whose address is n+1 is executed. When the terminal station of the address of #n does not exist, dummy data DD are sent from a central processing unit CPU' and then, the carrier detecting circuit 1 of the terminal stations ST1', ST2', ST3'... detects this, and by the fall of the detecting signal, one of the counter 2 is counted up and n+1 is obtained. For this reason, the data transmission is started from the next #n+1 terminal station. Thus, the action of a system is continued.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention is characterized in that a central processing unit and a plurality of terminal stations are connected via a bus line, and data is transmitted from the terminal stations to the central processing unit during a time allotted to each terminal station. The present invention relates to a data transmission system for sending data to a device.

<Prior Art> FIG. 5 shows a central processing unit CPU and a plurality of terminal stations ST1. S
FIG. 2 is a configuration diagram of a data transmission system in which r1.5T3--8Tn are connected by a bus line BLIS. In such a system, there are the following two methods for transmitting data held by each end and station to the central processing unit CPU.

The first method is a time division method as shown in the timing chart of FIG. 6, in which the central processing units C and PU
．． Sr1, 5T3---8Tn sends a clock signal (Figure (a)) that allocates a time slot for data transmission, counts this at each terminal station, and compares this content with a preset address within the terminal station. When they match, the corresponding terminal station sends the data Dn- within the allotted time.
1゜1) This is a method in which n -1, D n , D n + 1 are sent to the central processing unit CPU.

The second method uses the central processing unit CPU and each terminal station ST1. ST
2,5T3---8Tn This is a method (conversation method) in which data is collected by talking with the Tn, and as shown in the timing chart in Figure 7, a transmission request RF1 specifying the address of the terminal station is sent to the center. When a signal is sent from the processing device CPIJ, the terminal station ST1°Sr1. Among Sr1...STn, a data frame TF1 is sent to the central processing unit CPU from the terminal station that has received a transmission request. Next, when the central processing unit CPU issues a transmission request RF,2 specifying a new terminal station address, data is sent from the terminal station requested for transmission in the same manner as before.

By the way, in the case of such a data transmission system, the above-mentioned time division method does not require a function to receive data from the central processing unit CPU in each terminal station, so it has the advantage that the configuration of the terminal stations can be simplified. In addition to the bus line for data transmission, it was necessary to provide one circuit for sending a clock.

In the case of the conversation method, the terminal station ST1. Sr1.
Sr1...STn must be equipped with a function to receive transmission requests sent from the central processing unit CPU, which has the disadvantage of complicating the terminal station configuration. Since requests are issued, there is a drawback that the efficiency of using the bus line decreases.

<Problems to be Solved by the Invention> The technical problems to be solved by the present invention are that the terminal station has a simple configuration, does not require a bus line for purposes other than data transmission, and
Another object of the present invention is to realize a data transmission system in which data transmission on the bus line is used with high efficiency.

Means for Solving the Problems> In the data transmission system, the present invention includes a carrier detection circuit that is provided in the terminal station and the central processing unit and detects the presence or absence of data on the bus line; A counter provided in the terminal station and the central processing unit is counted each time data is detected by the carrier detection circuit, and when the contents of the counter match the set terminal address, the information stored in the terminal station is counted. means for transmitting data to the central processing unit via the bus line; The device is configured to send data to the bus line, reset the counter when data transmission from all terminal stations is completed, and send dummy data to the bus line.

Function> The above technical means works as follows. That is, the presence or absence of a transmission signal on the bus line is counted, the count result is compared with the address of each terminal station, and when they match, data is transmitted from the corresponding terminal station to the central processing unit. On the other hand, when there is no terminal station whose address matches the contents of the counter, dummy data is sent from the central processing unit to the bus line so that data transmission from the terminal station can be continued.

<Example> Examples of the present invention will be described below according to the drawings. 1st
The figure is a block diagram showing an embodiment of the present invention. In the figure, CPtJ' is a central processing unit, terminal stations ST1',
It is connected to ST2', ST3', . . . via a bus line BUS. In the terminal station ST1', 1 is a carrier detection circuit that detects the presence or absence of data on the bus line BtJS, 2 is a counter that counts up based on the signal detected by the carrier detection circuit 1, and 3 is a counter of this counter. A coincidence circuit 5 that compares the content with the content set by the address setting switch 4 starts operating when the detection signal of the carrier detection circuit 1 disappears, and at a predetermined timing, outputs the signal T1. This is a timer that generates T3 and is cleared when the signal is detected by carrier detection circuit 1. Signal T3 is sent to the clear terminal of counter 2, and signal T1 is an AND gate to which the output from minus number circuit 3 is given. 6 has been added.

Reference numeral 7 denotes a transmission control circuit that sends the data in the memory 8 to the bus line BUS1 via the x-multiplier circuit 9 based on a signal applied from the AND gate 6 to the enable terminal.

Although the terminal stations ST2', ST3', . . . are simply shown as blocks, their configuration is basically the same as that of the terminal station ST1'.

In the central processing unit cpu', 10 is a terminal station ST1'.

11 is a reception control circuit for storing data from the reception circuit 10 in the memory 12; 13 is a bus line B
a carrier detection circuit that detects the presence or absence of data on the LIS;
14 is a counter that counts up based on the signal detected by the carrier detection circuit 13; 15 is a setting switch that sets a value that is the maximum address N of the system plus 1; and 16 is the content of the counter 14 and the address setting switch 1.
A match circuit 17 for comparing the contents of the match circuit 17 with the contents of the match circuit 17 is an AND gate to which the output of the match circuit 16 is applied via an inverter 18 to one input.

19 starts operating when the detection signal of the carrier detection circuit 13 disappears, and at a predetermined timing, the signal T2. This is a timer that generates T3, and the signal T2 becomes H if there is no output from the carrier detection circuit 13 even after time t2 has elapsed after the previous data transmission is completed, and when the signal is detected by this carrier detection circuit. cleared. This signal is AND gate 1
The signal T3 is applied to the other input of the counter 14, and the signal T3 is applied to the clear terminal of the counter 14. A transmission control circuit 20 transmits dummy data in the memory 12 to the bus line BUS via the transmission circuit 21 based on a signal applied to an enable terminal from the AND gate 17.

The operation of the apparatus according to the embodiment of the present invention configured as described above is explained in the second section.
This will be explained according to the timing charts shown in FIGS.

FIG. 2 is a timing chart for explaining the basic operation of the device according to the embodiment of the present invention, in which data is transmitted from a terminal station at a corresponding address based on transmission data on the bus line BtJS.

In FIG. 2, (a) shows data on the bus line BUS, and (b) shows terminal stations ST1' and ST2'.

ST3'... The detection signal of the carrier detection circuit 1 in the central processing unit fcPtJ' (the carrier detection circuit 13 in the central processing unit fcPtJ' also operates in the same way), Figure (C) shows the detection signal of the carrier detection circuit 1 The output of the counter 2 is incremented by one at the falling edge of the counter 2 (the counter 14 in the central processing unit CPU' also operates in the same manner). FIG.

The output of the matching circuit 3 in ST2', ST3'... Figure (e) shows the terminal stations STI', ST2', ST3'
-- Waveform of output T1 of timer 5 in --- Figure (f>
shows the output waveform applied from the AND gate 6 to the enable terminal of the transmission control circuit 7.

In order to avoid malfunctions due to noise on the bus line BUS, the carrier detection circuit 1 detects the transmitted data.
It is set so that it rises with a delay of t5 and falls with a delay of t5 after the data becomes null.

Assume that data transmission up to station #n-1 has now been completed. Terminal stations ST1', ST2', ST3'...
The counter is incremented by one at the falling edge of data #n-1, so its content is n (Figure (C)
). At this time, if the address of the terminal station ST1' is set to n by the address setting switch 4, the terminal station ST1'
A coincidence output is generated from the coincidence circuit 3 in 1' (Figure (d)
).

On the other hand, the timer 5 generates the signal T1 after the time tl has elapsed since the fall of the detection signal of the carrier detection circuit 1, and when the output signal of the minus number circuit 3 and the signal @T1 are output simultaneously, the transmission control circuit 7 Enabled. As a result, the data stored in the memory 8 of the #n terminal station ST1' is sent to the bus line BUS via the transmitting circuit 9 (FIG. (a)). still,
The timer 5 is cleared when the carrier detection circuit 1 detects the data of the #n station.

When the data transmission from the terminal station ST1' is completed, the output of the carrier detection circuit 1 becomes L, and the terminal station ST1' is transferred.

The counter 2 in ST2', ST3', . . . is incremented by one, and its content becomes n+1.

Next, data is transmitted from the terminal station whose address is n+1 using the same procedure.

By the way, if the terminal station addresses are set consecutively as 1, 2, 3...
Data can be transmitted one after another from T1', ST2', ST3', etc., but if there is no terminal station corresponding to the address, it is not possible to continue data transmission with only the above basic operation. I can't do it.

FIG. 3 shows the auxiliary operation in the apparatus according to the present invention, which allows data transmission from the terminal station even if the address is unmanageable. In FIG. 3, diagram (a) shows the bus line Bt
Data on JS, Figure (b) is the detection signal of the carrier detection circuit 13 in the central processing unit CPLI', Figure (C) is the output waveform of the output T2 of the timer 19 1 in the central processing unit CPU', Figure ( d) is the terminal station STI', ST2'.

ST3'... Indicates the output of counter 2.

In the case of this figure, there is no terminal station with address #n. When the output of the carrier detection circuit 13 becomes L after sending out the data of the #n-1 station, the timer 19 starts operating. Terminal station ST1'.

In ST2', ST3'..., counter 2
The content of is n (Figure (d)), but since there is no terminal station with address n, there is no output from minus number circuit 3 (,t
Even after one elapse, no transmission data is added on the bus line BUS.

Time t2 (however, t2 > t1) I! If the data does not appear even after the time has elapsed, the timer 19 of the central processing unit CPU' generates a signal T2.

On the other hand, the coincidence circuit 16 of the central processing unit cpu' is given a value obtained by adding 1 to the maximum address N determined according to the number of terminal stations from the address setting switch 15, and the counter 1
There is no output unless the contents of signal MT2 match this value. 20 is enabled, and dummy data DD is sent from the memory 12 to the bus line BLIS via the transmission circuit 21.The dummy data DD is
For example, a meaningless data string such as all 1's is sent out for a certain period of time.

When dummy data DD is sent from the central processing unit cpu', the terminal stations ST1', ST2', ST3'...
The carrier detection circuit 1 detects this, and at the fall of this detection signal, the counter 2 is counted up by one and set to n+1. Therefore, data transmission starts from the next terminal station #n+1. In this manner, operation of the system continues.

FIG. 4 shows the central processing unit c in the apparatus according to the embodiment of the present invention.
pu' and terminal stations ST1' and ST2'.

ST3' . . . indicates an initialization operation for resetting the counters 14 and 2 and causing data transmission from these terminal stations to be performed again. In this diagram, diagram (a) is bus line B.
Data on US, Figure (b) is the detection signal of the carrier detection circuit 13 in the central processing unit fCPU', Figure (C) is the output of the counter 14 in the central processing unit cpu', Figure (d) is the central processing unit The inverted output (output of the inverter 18) of the matching circuit 16 in the CPU', Figure (e) shows the central processing 'aA and cp
The waveform of output T2 of timer 19 1 in u', Figure (f) shows the waveform of output T2 of timer 19 1 in central processing unit CPU' and terminal stations ST1' and ST2'.
, ST3' . . . shows the waveform of output T3 generated at the same timing from timer 19.5.

Sequential terminal stations ST1', ST2', ST3'...
When the data transmission from the terminal station with the maximum address #N is completed, the carrier detection circuit 13
In response to the detection signal (FIG. (b)), the contents of the counter 14 become N+1 (FIG. (C)).

As a result, an output is generated in the minus number circuit 16, and the inverter 1
The output of 8 becomes L (figure (d)). As a result, timer 1
Even if the signal T2 is outputted from 9, the communication control circuit 20 does not operate and dummy data DD is not outputted.

When time t3 (where t3>t2>tl> has elapsed), signal T3 is generated, and the counter 14 of the central processing unit CPU' as well as the terminal station ST1'.

All counters 2 in ST2', ST3', . . . are reset. As a result, the output of the inverter 18 becomes H, and the transmission control circuit 20 is enabled by the AND output with the signal T2, and the dummy data DD is sent from the memory 12 onto the bus line BUS via the transmission circuit 21. System operation is resumed.

<Effects of the Invention> According to the present invention, it is not necessary to provide the terminal station with a receiving function, and it is sufficient to have a function of detecting the presence or absence of a signal on the bus line, which simplifies the configuration of the terminal station. can. Furthermore, compared to a method in which data is transmitted in a time-division manner by sending out a clock and allocating time slots for data transmission from each terminal station, the present invention does not require a line for transmitting a clock, and basically requires no line. It has the advantage that it can be configured with two lines, making it easy to configure the transmission line.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention;
4 are timing charts for explaining the operation of the device according to the embodiment of the present invention shown in FIG. 1, FIG. 5 is a configuration diagram of a conventional data transmission system, and FIGS. This is a timing chart for explaining the operation. CPU'...Central processing unit, ST1', ST2'
. ST3'...terminal station, Bus...bus line, 1゜13...carrier detection circuit, 2,14...
Counter, 3.16...-number circuit, 4.15...Address setting switch, 5,19...Timer, 1.20
...Transmission control circuit, 8.12...Memory

Claims (1)

[Claims] A central processing unit and multiple terminal stations are connected via a bus line,
In a data transmission system in which data is sent from a terminal station to the central processing unit during a time allotted to each terminal station, carrier detection is provided in the terminal station and the central processing unit and detects the presence or absence of data on the bus line. a counter provided in the terminal station and the central processing unit and counted each time data is detected by the carrier detection circuit;
means for transmitting data accumulated in the terminal station to the central processing unit via the bus line when the contents of the counter match a set terminal station address; and means provided in the central processing unit for transmitting the data; When data is not sent from any of the terminal stations after a predetermined period of time has passed after the end, dummy data is sent to the bus line, and when data transmission from all terminal stations is finished, the counter is reset and the dummy data is sent to the bus line. means for sending data to the bus line, operates a counter based on the presence or absence of a transmission signal on the bus line, compares the count result of this counter with the address of each terminal station, and takes action when they match. When data is transmitted from a terminal station to the central processing unit, and there is no terminal station with an address that matches the contents of the counter,
A data transmission system characterized in that the central processing unit sends the dummy data to the bus line so that data transmission from the terminal station continues.