JPS61196613A - Automatic equalizer control system - Google Patents

Automatic equalizer control system

Info

Publication number
JPS61196613A
JPS61196613A JP3537385A JP3537385A JPS61196613A JP S61196613 A JPS61196613 A JP S61196613A JP 3537385 A JP3537385 A JP 3537385A JP 3537385 A JP3537385 A JP 3537385A JP S61196613 A JPS61196613 A JP S61196613A
Authority
JP
Japan
Prior art keywords
circuit
reference value
value
equalization
evaluation value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3537385A
Other languages
Japanese (ja)
Inventor
Shigeru Ono
茂 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP3537385A priority Critical patent/JPS61196613A/en
Publication of JPS61196613A publication Critical patent/JPS61196613A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize an automatic equalizer in which a characteristic change is very little and stability is excellent at the time of the completion of the training and at the time of communication by detecting, by an estimation value detecting circuit from the above-mentioned equalizer circuit output, the estimation value to estimate whether or not the equalizer circuit output is a signal which can identify the correct data and comparing with the reference value. CONSTITUTION:An estimation value to estimate the equalizing condition from an output signal is detected by an estimation value detecting circuit, the output of the said detecting circuit 4 and a reference value (1) of a reference value generating device 12 are compared by a comparing circuit 13, and a reference value (2) of a reference value generating device 14 is compared by a comparing circuit 15. When the estimation value of the estimation value detecting circuit 4 is smaller than the reference value (1), an equalizing characteristic is changed to the direction to increase the estimation value, when the above-mentioned estimation value is larger than the reference value (2), the equalizing characteristic is changed to the direction to decrease the estimation value, and when the estimation value is larger than the reference value (1) and smaller than the reference value (2), the equalizing characteristic is not changed.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はディジタル伝送における伝送路の特性による符
号量干渉を状況に自動的に適応して抑圧し、正しいデー
タが受信できるようにする自動等化器の制御方式に関す
る。
Detailed Description of the Invention (Industrial Application Field) The present invention is an automatic system that automatically adapts to the situation and suppresses code amount interference due to the characteristics of the transmission path in digital transmission, so that correct data can be received. Concerning the control method of the converter.

(従来技術) 第2図は従来のこの種の自動等化器の構成例を示すブロ
ック図である。入力端子1の受信信号は、等化回路2を
通ることにより、符号量干渉の抑圧された正しいデータ
識別のできる信号となって出力端子3へ出力される。こ
のとき、等化回路2の特性を伝送路の状況に適応して最
もよく符号量干渉を抑圧するように設定する必要がある
。これは通常、出力信号から等化状況を評価するだめの
評価値を評価値検出回路4により検出し、比較回路5で
予め定めた基準値発生器6の基準値と前記評価値を比較
した結果に基づき制御回路7によシ設定する。具体的な
例として、判定帰還形等化器の収束性(電子通信学会技
術研究報告CS 82−85.1982年)に示されて
いるような判定帰還形等化器を等化回路2に用いた場合
について説明する。
(Prior Art) FIG. 2 is a block diagram showing an example of the configuration of a conventional automatic equalizer of this type. The received signal at the input terminal 1 passes through the equalization circuit 2 and is outputted to the output terminal 3 as a signal in which code amount interference is suppressed and data can be correctly identified. At this time, it is necessary to set the characteristics of the equalization circuit 2 so as to best suppress code amount interference by adapting to the conditions of the transmission path. This is usually the result of detecting an evaluation value for evaluating the equalization status from the output signal by an evaluation value detection circuit 4, and comparing the evaluation value with a predetermined reference value of a reference value generator 6 by a comparison circuit 5. The setting is made by the control circuit 7 based on the following. As a specific example, a decision feedback equalizer as shown in Convergence of Decision Feedback Equalizer (IEICE technical research report CS 82-85, 1982) is used in the equalization circuit 2. I will explain the case where

第3図は判定帰還形等化器の構成例を示すブロック図で
ある。等化回路出力信号より識別回路8でデータを識別
した信号はに段のデータ識別周期の遅延量を有する遅延
回路9を通シ、各段の出力それぞれに対し重みWlから
Wkを乗算回路10によシ乗じ、各乗算回路10の出力
信号を等化回路2の入力信号へ加算回路11により加え
ることで符号量干渉が抑圧される。このとき重みW□か
らWkは伝送路の状況に適応して、干渉を与えるパルス
よシ後へ1番目からに番目の識別時点の符号量干渉をそ
れぞれ抑えるように制御される。即ち各重みW1〜Wk
は通常通信に先だち孤立1?ルスを用いてトレーニング
されるが、受信パルスのピーク位置より後1番目の識別
時点の等化回路出力信号値をhi、受信パルスの極性を
S(+1または−1)として Wl−Δ・sgn (h i ) ・S−+W 、  
    (1)のアルゴリズムによシ更新される。但し
式(1)で1≦i≦にであシ、sgn(x)はXの極性
を表わす、Δは重み修正係数であシ、最適値に重みを収
束するためには十分小さくとる必要がある。第3図に示
す判定帰還形等化器は、各識別時点の符号量干渉量が第
2図における評価値に対応し、基準値はゼロであり、各
重みW1〜Wkが等化特性を定めるノぐラメータとなっ
ている。
FIG. 3 is a block diagram showing an example of the configuration of a decision feedback equalizer. The signal whose data is identified by the identification circuit 8 from the equalization circuit output signal is passed through a delay circuit 9 having a delay amount corresponding to the data identification cycle of each stage, and then sent to a multiplication circuit 10 by weights Wl to Wk for each output of each stage. By multiplying the output signals of each multiplication circuit 10 and adding them to the input signal of the equalization circuit 2 by the addition circuit 11, code amount interference is suppressed. At this time, the weights W□ to Wk are controlled to adapt to the conditions of the transmission path so as to suppress the code amount interference from the first to the second identification time after the interfering pulse. That is, each weight W1 to Wk
Is isolation 1 prior to normal communication? However, the equalization circuit output signal value at the first identification point after the peak position of the received pulse is hi, and the polarity of the received pulse is S (+1 or -1).Wl−Δ・sgn ( h i )・S−+W,
It is updated using algorithm (1). However, in equation (1), 1≦i≦, sgn(x) represents the polarity of be. In the decision feedback equalizer shown in FIG. 3, the amount of code amount interference at each identification point corresponds to the evaluation value in FIG. 2, the reference value is zero, and each weight W1 to Wk determines the equalization characteristics. It is a nogura meter.

トレーニングの終了は第4図に示されるような評価値の
反復、あるいは自動等化終了判定方式(特公昭58−1
97927 )に示されるような各重みW0〜Wkの反
復をもって判定される。またトレーニング終了後の通信
時の制御は、通常孤立パルスとみなせるデータ・パター
ンを検出し、トレーニングのときと同様のアルゴリズム
により行われる。
The training is completed by repeating the evaluation values as shown in Figure 4, or by using the automatic equalization completion determination method (Special Publication No.
97927) by repeating each weight W0 to Wk. Further, communication control after training is performed by detecting a data pattern that can be considered as an isolated pulse, and using the same algorithm as during training.

(発明が解決しようとする問題点) しかしながら前述の方式では、トレーニング終了時ある
いは、通信時における孤立・ぐルス検出時に常に等化特
性が変化しているため、等化出力が安定せず、等測的に
雑音が多くなるという欠点があった。
(Problem to be Solved by the Invention) However, in the above-mentioned method, the equalization characteristics are constantly changing at the end of training or when isolation/glue is detected during communication, so the equalization output is not stable and the This method has the drawback of increasing noise in terms of measurements.

本発明は自動等化器において、予め定めた基準範囲に評
価値が収まるように制御を行うことで前述の問題点を解
決し、安定性の優れた自動等化器を実現するものである
The present invention solves the above-mentioned problems by performing control in an automatic equalizer so that the evaluation value falls within a predetermined reference range, thereby realizing an automatic equalizer with excellent stability.

(問題点を解決するための手段) 本発明は、自動等化器の制御方式において、等化状況を
評価するため評価値を検出する評価値検出回路と、該検
出回路の評価値が予め定めた基準範囲内に収まっている
か、あるいは基準範囲の下限より示さいか、又基準範囲
の上限よシ大きいかを比較する上限値の比較回路及び下
限値の比較回路と、該各比較回路の結果に基づき評価値
を変更する制御回路を備えて等化特性を制御する自動等
化器制御方式である。
(Means for Solving the Problems) The present invention provides an evaluation value detection circuit for detecting an evaluation value for evaluating an equalization situation in a control method for an automatic equalizer, and an evaluation value detection circuit for detecting an evaluation value in order to evaluate an equalization situation, and an evaluation value of the detection circuit that is determined in advance. An upper limit value comparison circuit and a lower limit value comparison circuit that compare whether the value is within the reference range set, or whether it is below the lower limit of the reference range, or whether it is greater than the upper limit of the reference range, and the results of the respective comparison circuits. This is an automatic equalizer control method that includes a control circuit that changes the evaluation value based on the equalization characteristics.

(作 用) 等化回路出力が正しいデータ識別できる信号となってい
るか否かを評価するための評価値を前記等化回路出力よ
シ評価値検出回路によって検出し、基準値と比較するた
め比較回路へ送出する。評価値の比較は、上限値の比較
回路と、下限値の比較回路によって行う。即ち上限値比
較回路では基準値の上限よシ大きいか否かを検出し、下
限値比較回路では基準値の下限より小さいか否かを検出
する。前記各比較回路出力は制御回路へ送られる。
(Function) An evaluation value for evaluating whether the output of the equalization circuit is a signal that can identify correct data is detected by the evaluation value detection circuit from the output of the equalization circuit, and is compared to a reference value. Send to circuit. Comparison of evaluation values is performed by an upper limit value comparison circuit and a lower limit value comparison circuit. That is, the upper limit comparison circuit detects whether or not the upper limit of the reference value is greater than the upper limit, and the lower limit value comparison circuit detects whether or not it is smaller than the lower limit of the reference value. Each of the comparison circuit outputs is sent to a control circuit.

制御回路では上限値の比較回路出力と下限値の比較回路
出力に基づき評価値が基準範囲に収まるように等化特性
を制御する。
The control circuit controls the equalization characteristic so that the evaluation value falls within the reference range based on the comparison circuit output of the upper limit value and the comparison circuit output of the lower limit value.

(実施例) 第1図は本発明の実施例を示すブロック図である。入力
端子1よシの受信信号は、等化回路2を通ることによシ
符号間干渉の抑圧された正しいデータ識別のできる信号
となって出力端子3へ出力される。このとき、出力信号
から等化状況を評価するための評価値を評価値検出回路
4によシ検出し、該検出回路4の出力と基準値発生器1
2の基   ゛準位(1)とを比較回路13で、又基準
値発生器14の基準値(2)とを比較回路15で比較す
る。前記基準値(1)と基準値(2)は、基準範囲の上
限と下限を表わす。いま基準値(1)が下限、基準値(
2)が上限とすると、比較回路13の出力は下限よシ評
価値が上か下か、又比較回路15の出力は上限よシ評価
値が上か下かを表わすことになる。評価値が基準値(1
)より大きく、かつ基準値(2)より小さければ、基準
範囲内に収まっている。制御回路16は比較回路13と
比較回路15の出力によシ評価値が基準範囲に収まるよ
うに等化特性を制御する。即ち評価値検出回路4の評価
値が基準値(1)よシ小さければ評価値を上げる方向へ
等化特性を変更し、前記評価値が基準値(2)より大き
ければ評価値を下げる方向へ等化特性を変更し、評価値
が基準値(1)よシ大きく、かつ基準値(2)より小さ
ければ等化特性を変更しないというように制御を行う。
(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention. The received signal from the input terminal 1 passes through the equalization circuit 2 and is outputted to the output terminal 3 as a signal in which intersymbol interference is suppressed and data can be correctly identified. At this time, an evaluation value for evaluating the equalization status is detected from the output signal by the evaluation value detection circuit 4, and the output of the detection circuit 4 and the reference value generator 1
A comparison circuit 13 compares the reference level (1) of the reference value generator 14, and a comparison circuit 15 compares the reference level (2) of the reference value generator 14 with the reference level (1) of the reference value generator 14. The reference value (1) and reference value (2) represent the upper and lower limits of the reference range. Now the reference value (1) is the lower limit, the reference value (
2) is the upper limit, the output of the comparison circuit 13 indicates whether the evaluation value is above or below the lower limit, and the output of the comparison circuit 15 indicates whether the evaluation value is above or below the upper limit. The evaluation value is the standard value (1
) and smaller than the reference value (2), it is within the reference range. The control circuit 16 controls the equalization characteristics based on the outputs of the comparison circuits 13 and 15 so that the evaluation value falls within the reference range. That is, if the evaluation value of the evaluation value detection circuit 4 is smaller than the reference value (1), the equalization characteristic is changed in the direction of increasing the evaluation value, and if the evaluation value is larger than the reference value (2), the equalization characteristic is changed in the direction of lowering the evaluation value. The equalization characteristic is changed, and if the evaluation value is larger than the reference value (1) and smaller than the reference value (2), control is performed such that the equalization characteristic is not changed.

第1図の構成によれば基準範囲幅すなわち基準値(2)
と基準値(1)の差を、十分な等化精度が得られるほど
小さく、かつ比較回路13.15で十分比較可能なほど
太きい、即ち比較回路13,15の不感幅よシ大きい大
きさに選ぶとき、第5図の等化特性更新例に示すように
、トレーニング終了時には等化特性の変動がなくなる。
According to the configuration shown in Figure 1, the reference range width, that is, the reference value (2)
The difference between the reference value (1) and the reference value (1) is small enough to obtain sufficient equalization accuracy and large enough to be sufficiently compared by the comparison circuits 13 and 15, that is, larger than the dead width of the comparison circuits 13 and 15. As shown in the example of updating the equalization characteristic in FIG. 5, when the training is completed, the equalization characteristic does not fluctuate.

トレーニング終了は、評価値の変化の停止、あるいは第
3図における重みWlからWkの変化の停止によシ判定
する。
The end of training is determined by stopping the change in the evaluation value, or by stopping the change in the weights Wl to Wk in FIG.

また通信時には伝送路の特性の変化がおこるまで等化特
性の変化は生じない。
Further, during communication, the equalization characteristics do not change until the characteristics of the transmission path change.

前述の如く本発明の方式によれば等化特性の変動が少な
い安定した自動等化器を実現することができる。
As described above, according to the method of the present invention, it is possible to realize a stable automatic equalizer with little variation in equalization characteristics.

尚外部雑音があるときには、基準範囲幅が小さいと雑音
による評価値の変動が等化特性の変動を導くが、等化特
性を大きく劣化しない範囲で基準範囲幅を大きくするこ
とによシ等化特性の変動を少なく抑えることができる。
Note that when there is external noise, if the reference range width is small, fluctuations in the evaluation value due to the noise will lead to fluctuations in the equalization characteristics, but equalization can be achieved by increasing the reference range width within a range that does not significantly degrade the equalization characteristics. Fluctuations in characteristics can be kept to a minimum.

(発明の効果) 以上詳述に説明した如く、本発明によればトレーニング
終了時及び通信時に特性変動の極めて少ない安定性の優
れた自動等化器を実現でき各種の伝送装置に応用できる
(Effects of the Invention) As described in detail above, according to the present invention, it is possible to realize an automatic equalizer with excellent stability, which exhibits extremely little variation in characteristics at the end of training and during communication, and can be applied to various transmission devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る自動等化器を示すブロック図、第
2図は従来の自動等化器を示すブロック図、第3図は等
化回路の構成例を示すブロック図、第4図は従来の自動
等化器の制御状況を示す説明図、第5図は本発明に係る
自動等化器の制御状況を示す説明図である。 1・・・入力端子、2・・・等化回路、3・・・出力端
子、4・・・評価値検出回路、5・・・比較回路、6・
・・基準値発生器、7・・・制御回路、8・・・識別回
路、9・・・遅延回路、10・・・乗算回路、11・・
・加算回路、12・・・基準値発生器、13・・・比較
回路、14・・・基準値発生器、15・・・比較回路、
16・・・制御回路。 特許出願人  沖電気工業株式会社 第4図 第5図
FIG. 1 is a block diagram showing an automatic equalizer according to the present invention, FIG. 2 is a block diagram showing a conventional automatic equalizer, FIG. 3 is a block diagram showing an example of the configuration of an equalization circuit, and FIG. 5 is an explanatory diagram showing the control situation of a conventional automatic equalizer, and FIG. 5 is an explanatory diagram showing the control situation of the automatic equalizer according to the present invention. DESCRIPTION OF SYMBOLS 1... Input terminal, 2... Equalization circuit, 3... Output terminal, 4... Evaluation value detection circuit, 5... Comparison circuit, 6...
... Reference value generator, 7... Control circuit, 8... Identification circuit, 9... Delay circuit, 10... Multiplication circuit, 11...
- Addition circuit, 12... Reference value generator, 13... Comparison circuit, 14... Reference value generator, 15... Comparison circuit,
16...Control circuit. Patent applicant Oki Electric Industry Co., Ltd. Figure 4 Figure 5

Claims (1)

【特許請求の範囲】 伝送路の状況に適応して等化特性を変化する自動等化器
の制御方式において、 等化状況を評価するための評価値検出手段と、該検出手
段の評価値が予め定めた基準範囲内に収まっているか否
かを判定する比較手段と、該比較手段の結果に基づき評
価値が基準範囲の上限値より大きくなるか、又は下限値
より小さくなった場合に前記基準範囲に収めるように制
御する制御手段を有し、前記等化特性を基準範囲内に制
御することを特徴とした自動等化器制御方式。
[Claims] A control method for an automatic equalizer that changes equalization characteristics in accordance with transmission path conditions, comprising an evaluation value detection means for evaluating an equalization situation, and an evaluation value of the detection means. a comparison means for determining whether or not it falls within a predetermined reference range; and a comparison means for determining whether or not the evaluation value falls within a predetermined reference range; 1. An automatic equalizer control method, comprising a control means for controlling the equalization characteristic so that the equalization characteristic falls within a reference range.
JP3537385A 1985-02-26 1985-02-26 Automatic equalizer control system Pending JPS61196613A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3537385A JPS61196613A (en) 1985-02-26 1985-02-26 Automatic equalizer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3537385A JPS61196613A (en) 1985-02-26 1985-02-26 Automatic equalizer control system

Publications (1)

Publication Number Publication Date
JPS61196613A true JPS61196613A (en) 1986-08-30

Family

ID=12440093

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3537385A Pending JPS61196613A (en) 1985-02-26 1985-02-26 Automatic equalizer control system

Country Status (1)

Country Link
JP (1) JPS61196613A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02186839A (en) * 1989-01-13 1990-07-23 Mitsubishi Electric Corp Adaptive type automatic equalizer
JPH0548391A (en) * 1991-01-23 1993-02-26 Fujitsu Ltd Adaptive equalizer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02186839A (en) * 1989-01-13 1990-07-23 Mitsubishi Electric Corp Adaptive type automatic equalizer
JPH0548391A (en) * 1991-01-23 1993-02-26 Fujitsu Ltd Adaptive equalizer

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