JPS61195168U - - Google Patents

Info

Publication number
JPS61195168U
JPS61195168U JP7654585U JP7654585U JPS61195168U JP S61195168 U JPS61195168 U JP S61195168U JP 7654585 U JP7654585 U JP 7654585U JP 7654585 U JP7654585 U JP 7654585U JP S61195168 U JPS61195168 U JP S61195168U
Authority
JP
Japan
Prior art keywords
vertical deflection
wave signal
signal
ray tube
staircase wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7654585U
Other languages
Japanese (ja)
Other versions
JPH0314871Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7654585U priority Critical patent/JPH0314871Y2/ja
Publication of JPS61195168U publication Critical patent/JPS61195168U/ja
Application granted granted Critical
Publication of JPH0314871Y2 publication Critical patent/JPH0314871Y2/ja
Expired legal-status Critical Current

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  • Details Of Television Scanning (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例を示す回路図、第
2図は第1図のマーカー発生回路の例を示す回路
図、第3図は第2図の回路のタイミングチヤート
、第4図はマーカー信号の表示形態を示す図、第
5図は第1図のゲート回路の例を示す回路図、第
6図はスムージングの調整時の信号波形図、第7
図もスムージングの調整時の表示形態を示す説明
図、第8図はスムージング動作を得る回路図、第
9図はスムージング動作時の信号波形図、第10
図はスムージング処理を説明するための説明図で
ある。 11……映像増幅器、12……陰極線管、13
……水平偏向コイル、14……垂直偏向コイル、
17……垂直偏向のこぎり波発生回路、18……
混合回路、19……垂直偏向増幅器、20……3
ビツトカウンタ、22,35……ゲイン調整用可
変抵抗器、31……マーカー発生回路、32……
12分周回路、33……ゲート回路、34……デ
ジタルアナログ変換器、SW〜SW……スイ
ツチ。
Fig. 1 is a circuit diagram showing an embodiment of this invention, Fig. 2 is a circuit diagram showing an example of the marker generation circuit of Fig. 1, Fig. 3 is a timing chart of the circuit of Fig. 2, and Fig. 4 is a circuit diagram showing an example of the marker generation circuit of Fig. 1. FIG. 5 is a circuit diagram showing an example of the gate circuit in FIG. 1, FIG. 6 is a signal waveform diagram when adjusting smoothing, and FIG.
The figures are also explanatory diagrams showing the display form during smoothing adjustment, Fig. 8 is a circuit diagram for obtaining smoothing operation, Fig. 9 is a signal waveform diagram during smoothing operation, and Fig. 10
The figure is an explanatory diagram for explaining smoothing processing. 11...Video amplifier, 12...Cathode ray tube, 13
...Horizontal deflection coil, 14...Vertical deflection coil,
17... Vertical deflection sawtooth wave generation circuit, 18...
Mixing circuit, 19...Vertical deflection amplifier, 20...3
Bit counter, 22, 35...Variable resistor for gain adjustment, 31...Marker generation circuit, 32...
12 frequency divider circuit, 33...gate circuit, 34...digital analog converter, SW0 to SW3 ...switch.

Claims (1)

【実用新案登録請求の範囲】 階段波信号発生手段と、この階段波信号発生手
段の出力と垂直偏向のこぎり波信号を混合して合
成垂直偏向信号を作り、この信号を陰極線管の垂
直偏向コイルに印加する手段とを具備したCRT
画像表示装置において、 前記陰極線管に供給する映像信号として、隣り
合う走査線を区別するために水平方向の表示位置
が異なる表示信号を発生する手段と、 前記階段波信号発生手段として、前記走査線の
間隔に対応したステツプの階段波信号を発生し、
かつそのレベルを可変抵抗器により調整可能とし
た手段と、 前記合成垂直偏向信号のゲインを調整し垂直偏
向サイズを拡大する手段とを具備したことを特徴
とするCRT画像表示装置。
[Scope of Claim for Utility Model Registration] A staircase wave signal generating means, an output of the staircase wave signal generating means and a vertically deflected sawtooth wave signal are mixed to produce a composite vertical deflection signal, and this signal is applied to a vertical deflection coil of a cathode ray tube. a CRT equipped with means for applying
In the image display device, means for generating display signals having different display positions in the horizontal direction in order to distinguish between adjacent scanning lines as video signals supplied to the cathode ray tube; generates a staircase wave signal with steps corresponding to the interval of
A CRT image display device, comprising: means for adjusting the level thereof using a variable resistor; and means for adjusting the gain of the composite vertical deflection signal to enlarge the vertical deflection size.
JP7654585U 1985-05-24 1985-05-24 Expired JPH0314871Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7654585U JPH0314871Y2 (en) 1985-05-24 1985-05-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7654585U JPH0314871Y2 (en) 1985-05-24 1985-05-24

Publications (2)

Publication Number Publication Date
JPS61195168U true JPS61195168U (en) 1986-12-05
JPH0314871Y2 JPH0314871Y2 (en) 1991-04-02

Family

ID=30618786

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7654585U Expired JPH0314871Y2 (en) 1985-05-24 1985-05-24

Country Status (1)

Country Link
JP (1) JPH0314871Y2 (en)

Also Published As

Publication number Publication date
JPH0314871Y2 (en) 1991-04-02

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