JPS61192354U - - Google Patents
Info
- Publication number
- JPS61192354U JPS61192354U JP7435885U JP7435885U JPS61192354U JP S61192354 U JPS61192354 U JP S61192354U JP 7435885 U JP7435885 U JP 7435885U JP 7435885 U JP7435885 U JP 7435885U JP S61192354 U JPS61192354 U JP S61192354U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- bus line
- address
- latch circuit
- microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Bus Control (AREA)
- Information Transfer Systems (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7435885U JPS61192354U (es) | 1985-05-20 | 1985-05-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7435885U JPS61192354U (es) | 1985-05-20 | 1985-05-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61192354U true JPS61192354U (es) | 1986-11-29 |
Family
ID=30614582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7435885U Pending JPS61192354U (es) | 1985-05-20 | 1985-05-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61192354U (es) |
-
1985
- 1985-05-20 JP JP7435885U patent/JPS61192354U/ja active Pending
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