JPS6119131B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a linearity compensation device in an amplifier circuit having nonlinear characteristics with respect to amplitude or phase.

Conventionally, as a linearity compensation method for a high frequency amplifier having nonlinear characteristics with respect to amplitude or phase, the first method has been proposed.
As shown in the figure, a correction method is used in which a circuit 1 having characteristics opposite to an amplifier circuit 2 having non-linear characteristics is inserted. This method can compensate for the linearity of the system and prevent nonlinear distortion from occurring. However, the nonlinear characteristics of an amplifier generally fluctuate due to aging and the unique characteristics of the elements used for amplification, so the overall characteristics often deteriorate, making it difficult to accurately maintain the inverse characteristics. In order to survive, it was essential to check and readjust its characteristics from time to time.

In addition, in order to eliminate the need to constantly adjust the characteristics, a second
As shown in the figure, a method can be considered in which the nonlinear error of the amplifier 3 is detected by the detector 4, amplified by the ideal amplifier 5, and then combined with the output of the amplifier 3 by the combiner 6. Because it is necessary
It has the disadvantage of being inefficient.

Another possible method is to store non-linear data corresponding to the input signal level in memory, read it as data corresponding to the input signal level, and use the readout output to determine the amount of correction, but the characteristics of the amplifier may change over time. The disadvantage is that accurate correction cannot be made when changes occur.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a new linearity compensator which eliminates the drawbacks of the prior art.

According to the present invention, a non-linear error between the input and output of an amplifier circuit is constantly detected, it is converted into a digital signal and written into a read/write memory, and the written data is set at the signal input level using the signal input level as an address. By reading out the correction amount according to and controlling the programmable attenuator, a linearity compensator can be obtained which can perform sequential corrections and can constantly follow and correct the nonlinear characteristics of the amplifier circuit.

Next, the present invention will be explained in detail with reference to FIG. 3, which shows one embodiment of the present invention. In the figure, an input signal is outputted through a delay circuit 7, a programmable attenuator 8, and an amplifier circuit 9 having nonlinear characteristics. Further, the input signal is branched on the input side, passes through a delay circuit 13, is level-adjusted, and is applied to an error detector 14 that detects amplitude errors. The output of the amplifier circuit 9 is also level-adjusted and then applied to the error detection circuit. Here, the delay circuit 13
The amount of delay is made equal to the total amount of delay caused by the delay circuit 7, programmable attenuator 8, and amplifier circuit 9. Further, it is assumed that the signal levels on the input side and the output side applied to the error detector 14 are adjusted so that they are at the same level when the characteristics of the amplifier circuit 9 are ideal. A differential amplifier is used for the error detection circuit 14. The output of the error detector 14 is obtained as a DC voltage and is supplied to a sample and hold circuit 16.

The signal branched on the input side is further applied to a window type level comparator 10, and the more precisely the input level is determined, the more finely the correction can be made. Further, in level determination, it is not necessarily necessary to divide the levels at equal intervals, and only a necessary predetermined range can be finely divided. Comparator 1
The output of 0 is supplied as a read address signal to the read/write memory 11 and further to the latch circuit 15. The output of the sample hold circuit 16 is an A/D
After being converted into a digital signal by the converter 17, it passes through the adder 18 and the value is written into the memory 11 as non-linear error data. At this time, latch circuit 1
The output of 5 is used as the write address signal. The data read from the memory 11 passes through the latch circuit 12 and is then transferred to the programmable attenuator 8.
The attenuator 8 has an attenuation amount corresponding to the data. The data read from the memory 11 passes through the latch circuit 26 on the other hand to the adder 1.
Sent to 8. At this time, the output of the adder 18 represents non-linear error data only in the amplifier circuit 9, and this data is sequentially sent to the memory and updated.

The written data in the memory 11 is sequentially read out using the level discrimination information from the window type level comparator 10 as an address and held in the latch circuit 12. This data is sent to the programmable attenuator 8, and the attenuator 8 performs correction to give a predetermined degree of attenuation to the input signal. If the correction is performed accurately, the output of the error detector 14 is always zero, and the data that has been read once is written into the memory 11 again via the latch circuit 26 and the adder 18.

When the characteristics of the amplifier circuit 9 change, the error detector 1
4 appears, and this output is sent to an adder 18 via a sample and hold circuit 16 and an A/D converter 17. The adder 18 adds the output from the A/D conversion circuit 17 to the output from the latch circuit 26,
The corrected data of the addition result is immediately stored in memory 1.
Write it to 1. In this way, according to the present invention, even if the state of the amplifier circuit 9 changes, that is, even if the non-linearity of the amplifier circuit 9 changes, the correction data is immediately updated and continues to be written to the memory in accordance with the change. , can follow changes extremely quickly, and can make stable and accurate corrections.

Note that the delay circuit 7 is inserted to delay the input signal and match the timing until data is read from the memory 11 and correction is applied. In addition, if the timing of the level discrimination information held in the latch circuit 15 and the output signal of the error detector 14 do not match due to the delay caused by the delay circuit 13, the signal path to the latch circuit 15 is Insert a delay circuit.

In the latch circuits 15 and 26 and the sample hold circuit 16, the level determination information of the input signal at the same time, the correction amount at that moment, and the error voltage are held by control pulses from the timing control circuit 19. Also, A/D converter 17, latch circuit 1
2. A predetermined timing signal is also supplied to the memory 1 from the timing control circuit 19.

Figure 4 is a diagram showing the configuration of a programmable attenuator. Numeral 20 is an attenuation element that doubles from 0.1 dB to 3.2 dB, and when combined, can attenuate up to 6.3 dB in 0.1 dB steps. is obtained. Reference numeral 21 is a switch element, which is shown by a broken line and is interlocked so that when one is turned on, the other is turned off. In view of operating speed, a semiconductor stitch is often used for 21. Reference numeral 22 denotes an amplifier for driving the switch element, and the read data from the memory in binary representation is added to the input as a control signal. Therefore, in this example, the A/D converter 17
The output of the error detector 14 is adjusted so that the resolution is 0.1 dB.

An example of the characteristics of the linearity compensator according to the present invention is shown in FIG. In the figure, 23 is an example of the characteristics of the amplifier circuit 9, and 24 is an ideal linear characteristic. 25
indicates the output characteristics after correction, and the signal input level is discriminated in 8 stages from "1" to "8".
The gain corresponding to the difference between and 24 is adjusted by the programmable attenuator. In this example, since the correction is performed in the direction of increasing the gain, the programmable attenuator may set the attenuation amount to the maximum value in advance, and then reduce the attenuation amount in accordance with the data read from the memory. Furthermore, in order to obtain correction characteristics that are more linear, the signal input level may be determined more precisely.

As described above, in the present invention, an example of compensating for amplitude errors has been shown, but it goes without saying that the technical concept of the present invention can also be applied to compensating for phase errors. To compensate for phase errors, a program delay circuit is used in place of the program attenuator shown in FIG. 3, and a phase comparator is used as the error detection circuit 14.
If the signal is a television video signal, phase comparison may be performed using a synchronization signal as a reference. It is also possible to consider a method of determining the phase difference based on the time difference when both input signal levels of the phase comparator pass a certain specified level. In this case, if no phase difference is detected after the amplitude linearity is corrected, an error will occur in the detected phase.

There is also a method of obtaining a direct digital value instead of a DC voltage as the output of the phase comparator. In other words, this method generates a gate pulse with a width corresponding to the phase difference, and counts the number of reference clock pulses within this width. In this case, the sample and hold circuit 16 in FIG. 3 becomes a latch circuit, and the A/D converter 1
7 becomes unnecessary. Furthermore, if a programmable delay circuit is configured by combining delay elements of, for example, 0.1 .mu.s to 3.2 .mu.s, a delay of up to 4.3 .mu.s can be obtained in 0.1 .mu.s steps. Further, the operating characteristics are as shown in FIG. The reference numbers in the figures are the same as in FIG.

As described above, according to the present invention, nonlinear error data is stored in the read/write memory while being constantly updated, and data corresponding to the input level can be sequentially read out from the memory and correction can be applied. It can quickly track non-linear characteristics that tend to fluctuate and make appropriate corrections.

[Brief explanation of the drawing]

1 and 2 are diagrams showing a conventional compensation method for nonlinear characteristics, and FIG. 3 is a diagram showing an embodiment of the present invention.
FIG. 4 is a diagram showing the configuration of a programmable attenuator, FIG. 5 is a diagram showing input/output characteristics in terms of amplitude characteristics, and FIG. 6 is a diagram showing input/output characteristics in phase characteristics. In the figure, 1...Inverse characteristic circuit for non-linear characteristic compensation, 2, 3, 9... Non-linear characteristic amplifier circuit, 4, 1
4...Error detector, 5...Ideal amplifier, 6...Synthesizer, 7...Delay circuit, 8...Programmable attenuator, 10...Window type level comparator, 11...Read/write memory, 12 ,1
5, 26...Latch circuit, 13...Delay circuit, 1
6... Sample hold circuit, 17... A/D converter, 18... Adder, 19... Timing control circuit, 20... Attenuation element, 21... Switch element, 22... Switch drive amplifier circuit, 2
3...Example of amplifier circuit input/output characteristics, 24...Ideal input/output linear characteristics, 25...Example of input/output characteristics after correction.

Claims (1)

[Claims] 1 A device for compensating the non-linear characteristics of an amplifier circuit, which is a programmable compensation circuit that is inserted in series with the amplifier circuit and whose characteristics can be variably changed according to output data from a memory; an error detection circuit that detects a difference between an input signal and an output signal of a system including a programmable compensation circuit; means for receiving the output of the error detection circuit and extracting non-linear data of the amplifier circuit as a digital signal; Level determining means for determining the level of a signal and outputting it as digital data; and a read/write memory that uses the digital data from the level determining means as an address signal, stores the non-linear data at that point in time, and sends its output to the programmable compensation circuit. and means for reading data from the memory using digital data from the level determining means as an address signal, and performing correction that follows the nonlinear characteristics of the amplifier circuit.