JPS61190628A - Data transmitting device - Google Patents

Abstract

PURPOSE:To increase the number of degrees of freedom of system configuration by using asynchronous free running shift registers to constitute input, output, and branch data transmission lines and discriminating whether data is branch data or not to give data to transmission lines. CONSTITUTION:Data inputted to an input data transmission line 101 is given to a selective branch control part 104 through the transmission line 101, and normally, this output data is given to an output data transmission line 102. In this case, a branch discriminating part 105 is provided, and a branch condition is set preliminarily to this part 105 and is compared with inputted data. If they coincide with each other, data is discriminated as branch data, and this discrimination result is reported to the control art 104, and output data is controlled to be given to a branch data transmission line 103. Transmission lines 101-103 are constituted with asynchronous free running shift registers to have the data buffer function. Thus, asynchronous systems can be connected not only in series but also in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission device, and particularly to a data transmission device used as a component of a network that enables data transmission between a plurality of asynchronous systems, for example.

[Prior Art] Conventionally, as a method for transmitting data between asynchronous systems, FIFO (first-in first-out) has been used.
A common method was to use memory as a buffer between systems (Interface, August 1984 issue, pp.
, 2es-270).

For example, as shown in FIG.
A configuration is adopted in which an FO memory 73 is connected and the output of the A system 71 is buffered.

In addition, when connecting a plurality of asynchronous systems 81 to 84, as shown in FIG.
Connect with FO memories 85-87.

[Problems to be Solved by the Invention] By the way, the conventional FIFO memory merely has a data buffering function. Therefore, when asynchronous systems are connected using such a FIFO memory, each asynchronous system can only be connected in series as shown in FIG. 8 or 9. therefore,
The entire system connected by flFo memory is the ninth
The problem is that the Vibrine processing mechanism is simply constructed using a simple cascade connection as shown in the figure, and its degree of freedom is extremely low.

This invention was made in order to solve the above-mentioned problems, and it is a data transmission method that can provide a large degree of freedom in system construction when connecting asynchronous systems to construct an entire system. The purpose is to provide equipment.

[Means for Solving the Problems 1] This invention uses an asynchronous self-propelled shift register to configure an input data transmission path, an output data transmission path, and a branch data transmission path, so that data on the input data transmission path is branched. If the data should be branched, the data on the input data transmission path is given to the branch data transmission path; otherwise, the data on the input data transmission path is sent to the output data transmission path. It was designed to be given to

[Operation] The present invention has a data branching function in addition to the data buffering function of the conventional FIFO memory. Therefore, asynchronous systems can be connected not only in series but also in parallel.

[Embodiment] FIG. 1 is a schematic block diagram showing an embodiment of the present invention. In the figure, data input to an input data transmission line 101 is provided to a selective branch control unit 104 through this input data transmission line 101. Selective branch control unit 104
Normally, the data output from the input data transmission line 101 is given to the output data transmission line 102. Branch determination unit 105
A branching condition is set in advance, and the branching condition is compared with the condition of the data input to the input data transmission path 101. If the two conditions match, it is determined that the data input to the input data transmission path 101 is data to be branched, and the selective branch control unit 10
Tell 4. In response, the selective branch control unit 104
wIII so that the data output from the input data transmission path 101 is given to the branch data transmission path 103. Note that the input data transmission path 101. Output data transmission path 102
The branch data transmission path 103 is constructed using an asynchronous free-running shift register as described later, and has a data buffer function.

FIG. 2A is a schematic block diagram showing an example of an asynchronous self-running shift register used for the input data transmission path 101, output data transmission path 102, and branch data transmission path 103 shown in FIG. This asynchronous self-running shift register is a register in which input data is automatically shifted to the output direction without using a shift clock, provided that the next register is empty. It has a buffer function. In the figure, each stage of the shift register is composed of a parallel data latch and a transfer control circuit (hereinafter referred to as a C element) that provides a rising edge trigger to the parallel data latch.

Each of the C elements 301 to 303 receives two inputs, PO and P3, and outputs two outputs, Pl and P2. The internal state of the C element is determined by the states of these four signals, and takes nine states, So=Sg, as shown in Table 1 below. In addition, in the following explanation, the logical values rOJ and rlJ are respectively,
The signal value is set to O-level and high level.

Next, a transition diagram of the nine states of 5o=Sa described above is shown in FIG. 2B. In addition, in Fig. 2B, - indicates the conditional condition III.
J1 transfer is indicated, and → is an unconditional state l! Represents a transition. Furthermore, P1↑, PIJ, etc. each indicate a change in signal value from O to 1.1 to O. Whether it goes through cycle A or cycle B shown in Figure 2B depends on the time at which the next stage of the shift register becomes available for reception and the time at which the previous stage becomes available for output; By passing through cycle A or B, it is possible to propagate data from the previous stage to the next stage.

FIG. 3 is a diagram showing an example of a circuit of C elements constituting the asynchronous free-running shift register shown in FIG. 2A. By connecting such C elements in multiple stages, the C elements perform state transitions as shown in FIG. 2B and autonomously propagate data.

FIG. 4 is a diagram showing an example of a specific circuit configuration of the embodiment shown in the first factor. In the figure, input data transmission path 101
The parallel data latches 540-54 path 102 includes parallel data latches 546 and 547, and C elements 526 and 52.
1llI is formed by asynchronous free-running registers including 7 and 7. The branch data transmission line 103 is a parallel data latch 54
8 and 549 and C elements 528 and 529. The selective branch control unit 104 includes parallel data latches 550 and 551, four-man power NAND gates 582 to 585, and two-man power NAND gates 582 to 585.
ND gates 586 to 589 and two-man OR gate 581
and a D-type watch 556. The branch determination unit 105 includes a D-type flip 70 knob 552, a comparison data register 553, a mask data register 554, an exclusive OR circuit 510, and an oven collector with two manual NAs.
ND gate/circuit 511 and D-type flip-flop 55
5.

Next, the operation of the embodiment shown in FIG. 4 will be explained. In this embodiment, data is in the form of a packet consisting of a plurality of words, and each word is the first word in addition to the data value. It is assumed that the word has two pits: BOP to indicate that the word is the last word, and EOP to indicate that it is the last word, and the first word has preceding information that is a branch condition.

First, the head of bucket 1- is input to the input data transmission line 101, and when it reaches the stage of the C element 521, the P2 output of the C element 521 changes from O to 1, and the data stored in the parallel data latch 540 of the previous stage changes. The data value of the first word is stored in the parallel data latch 541. At this time, node A
(BOP pit) changes from 0 to 1, so the D-type flip 70 knob 552 latches the data value of the first word of the packet in the same way as the parallel data latch 541. The latched first word is compared with the value of the comparison data register 553 by the exclusive OR circuit 510, the pits not required for comparison are masked by the NANO gate circuit 511, and the comparison result, that is, the branch decision, is sent to the D-type flip-flop 553. Output for. During this time, the packet propagates on the input data transmission path 501, and the first word reaches the stage of the C element 523.
The D-type flip-flop 555 latches the branch decision result and outputs this result to the D-type latch 556.

On the other hand, the D-type latch 556 connects node C (EOP bit) and /-t to the packet i* that precedes this packet.
'D ((4 children 525 (7) P2 output) F.

At the point in time, the input from the D-type flip 70 knob 555 is latched, and the inputs to the four-man NAND gates 582 to 585 are controlled. When the branch condition is 0, 0 is output to the NAND gates 584 and 585 to prevent branching, 1 is output to the NAND gates 582 and 583, and the packet is propagated to the output data transmission path 102. control to do so. When the branch condition is 1, the opposite control is performed so that the packet is propagated to the branch data transmission path 103. At this time, N
Oven collector NANO gates 583 and 585, which operate in the same manner as AND gates 582 and 584, are provided, and the outputs of these gates are connected to a negative logic wired OR to form a C gate 525.
It is configured to send 23 manpower.

With the circuit configuration as described above, data branching can be realized without disturbing the natural flow of data. This is the result of configuring the circuit so that the data propagation delay at the branch is the same as in other parts of the transmission path.If the propagation delay at the branch is larger than other parts, the propagation delay at the branch Delays will regulate the overall data flow. In addition, by making the branch decision along the flow of the first word of the packet, and by using the branch decision and tll'lJ part as a vibe line processing configuration, data branching can be realized without disturbing the natural flow of data. I can do it.

FIG. 5 is a schematic block diagram showing an example of a data transmission device having a data merging function, whereas the embodiment shown in FIG. 1 has a data branching function. In the figure, input data transmission path 111 and merged data transmission path 113 are provided with data from different systems, respectively. The outputs of the input data transmission line 111g5 and the merging data transmission line 113 are given to the merging control section 115. Merging control section 11
5 normally outputs data from the input data transmission path 111 to the output data transmission path 112. Free buffer monitoring unit 1
14 constantly monitors the free status of the input data transmission line 111 and the output data transmission line 112, and when there is a free buffer on both transmission lines, a merge III 1 to that effect is sent.
111 Department 115 will be informed. In response to the empty buffer monitoring unit 114 detecting that there are empty buffers on both the input data transmission path 111 and the output data transmission path 112, the merging control unit 115 controls the merging data transmission path 113.
is applied to the output data transmission line 112. Note that the free buffer monitoring unit 114 performs input data transmission 1111.
The reason for monitoring the free status of both the output data transmission line 112 and the output data transmission line 112 is to ensure that the data propagation on the input data transmission line 111 is not obstructed, and to secure a buffer for storing the merged data in the output data transmission line 12. This is to do so. Input data transmission path 111. Output data transmission line 1
12 and the merging data transmission line 113, an asynchronous self-running shift register as described above is used.

FIG. 6 is a diagram showing an example of a specific circuit configuration of the data transmission device shown in FIG. 5. In the figure, input data transmission path 111 is constituted by an asynchronous free-running shift register including parallel data latches 640-642 and C elements 620-622.

The output data transmission line 112 includes parallel data latches 645 to 6.
47 and C elements 625 to 627.

Merging data transmission line 113 is constituted by an asynchronous free-running shift register including parallel data latches 648 and 649 and C elements 628 and 629. The free buffer monitoring unit 114 uses inverters 660 to 667 to
1 will be given. The confluence control unit 115 is a parallel data latch 64
3.644 and 650, C elements 623, 624 and 630, a two-man AND gate 671, SR flip-flops 672 and 673, and a two-man NOR gate 682.

Next, the operation of the data transmission device shown in FIG. 6 will be explained.

This data transmission device merges data on a merging data transmission path 113 with a main line consisting of an input data transmission path 111 and an output data transmission path 112, but the data flow prioritizes the flow on the main line. However, the configuration allows merging only when there is an empty buffer on the main line. That is, when there is no data on the main line, the negative logic wired OR output of the oven collector inverters 660 to 667 becomes 1, so that the combined data transmission line 1
Data arrives at 13 and node A (BOP pit) becomes 1
Then, the two-man power of the two-man AND gate 671 is both 1.
Therefore, the output of the two-man AND gate 671 becomes 1,
The SR flip-flop 672 is set, and the SR flip-flop 70 knob 673 is reset. by this,
For the merged data transmission line 113, the SR flip 70
Since the input from the knob 672 to the four-man power NAND gate 678 becomes 1, the C element 630 operates in the same way as other C elements, and at the same time, the parallel data latch 650 becomes able to output, so the merging is possible. Data on the data transmission path merges into the main line. On the other hand, input data transmission line 111
For 4-man NA from SR flip 70 Tsubu 673
Since the input to the ND gate 674 becomes O, the C element 623
does not propagate previous data. Note that at this time, since the output of the parallel data latch 643 is in a high impedance state, even if data arrives at the input data transmission line 111 during the merging operation, the merging will not be hindered.

On the other hand, when the merging of one packet of data is completed, the data on the main line is controlled to flow again. That is, when C element 629 sends out the last word of the packet, node 8
(EOP bit) becomes 0, and further, when C element 630 receives this, node C becomes 0. Therefore, node 8. Two-man power NOR gate 681 with C signal as input
The output of becomes 1, the SR flip 7O knob 672 is reset, and the propagation of the next packet is transmitted to the C elements 629 and 630.
It will not happen in the darkness. Further, when the last word of the merged packet is received at the first stage of the output data transmission path 112, that is, when both node D (EOP bit) and node E become 0, the two-man power NOR gate 68
Since the two input signals are both O, the SR flip-flop 673 is set and the C element 623 propagates the previous stage data, allowing data to flow on the main line.

Since an oven collector NAND gate is used for the C element 624 at the merging point, the number of delay stages of the C element is the same as the other C elements, two stages of gates, and since it operates at almost the same speed as the other C elements, the merging point When there is no data, it does not interfere with the natural flow of data on the main line.

As described above, while giving priority to the data flow on the main line, the packets of the merge data transmission rs113 are transferred to the output data transmission path 1 only when an empty buffer for merge is secured.
By making it possible to merge with 12, efficient merging is possible.
M structure was realized.

By using the data transmission device shown in FIG. 1 or 4 and the data transmission device shown in FIG. 5 or 6 exclusively for the network, it is possible to construct a functionally distributed system. FIG. 7 shows an example of a computing unit configured using a functional distribution network.

In FIG. 7, the packet flowing in from the external system via the interface 2oO is a two-word packet consisting of an operation code and data, as shown. On the other hand, the arithmetic processing section has an adder 207, a subtracter 2089, a multiplier 2, and
It is divided into 09.

The selective branching units 204 to 206 compare the first word of the input packet, that is, the operation code, with comparison data, and branch the packet to the corresponding arithmetic processing unit only when they match. In each arithmetic processing unit, input packet data 1 (01)
and data 2 (D2>), and outputs a packet consisting of a result flag and result data as shown in the figure.

Output packets are collected using converging units 201 to 203 and sent to interface 200. In addition, each process 2
In order to maintain a dynamic load balance between each function, a queue buffer using an asynchronous free-running shift register is provided before and after the unit.

[Effect of the invention] As described above, according to the present invention, the conventional FI
Since the FO memory has a data buffer function and a data branching function, if an asynchronous network is constructed using such a data transmission device, a network with a very high degree of freedom can be realized. and,
When a functional fractional network system is configured using such a data transmission device, the data buffers that each processing element should have individually can be integrated on the data transmission device, so the buffer 7 size for the entire system can be reduced. can be reduced.

Further, according to the present invention, since an asynchronous free-running shift register is used for each transmission path, data can be processed with a propagation delay equal to only the element delay, compared to a case where a memory such as a RAM is used as a buffer means. Can be transmitted at high speed. Such an asynchronous self-running shift register can control data transfer in a simple manner similar to the bushing and pop operations for conventional FIFO memories.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing one embodiment of the present invention. FIG. 2A shows the input data transmission line 101 shown in FIG.
Output data transmission line 102 and branch data transmission line 103
1 is a schematic block diagram showing an example of the configuration of an asynchronous self-propelled shift register used for. FIG. 2B is a diagram showing state transitions of C elements 301 to 303 shown in FIG. 2A. FIG. 3 is a diagram showing a specific circuit component of the C element shown in FIG. 2A. FIG. 4 is a diagram showing an example of a specific circuit configuration of the embodiment shown in FIG. 1. FIG. 5 is a schematic block diagram showing an example of a data transmission device having a data merging function. FIG. 6 is a diagram showing an example of a specific circuit configuration of the data transmission device shown in FIG. 5. Figure 7 is similar to Figure 1 and 5.
1 is a diagram showing an example of a functionally distributed network system configured by the data transmission device shown in the figure. FIGS. 8 and 9 are block diagrams showing the configuration of a conventional asynchronous system. In the figure, 101 is an input data transmission path, 102 is an output data transmission path, 103 is a branch data transmission path, 104 is a selective branch side iM1 section, and 105 is a branch determination section. Agent Masuo Oiwa Figure 1/Government Figure 5 Figure 2A

Claims (2)

[Claims] (1) A data transmission device for transmitting data between asynchronous systems, which includes an input data transmission path, an output data transmission path, a branch data transmission path, and the data on the input data transmission path is the data to be branched. branching determination means for determining whether or not the data on the input data transmission path is normally applied to the output data transmission path, and the branching data determination means determines whether the data on the input data transmission path is data to be branched; branching control means for controlling the data on the input data transmission path to be applied to the branch data transmission path in response to the determination, the input data transmission path, the output data transmission path, and the branch data transmission path are , is configured using an asynchronous free-running shift register in which input data is automatically shifted in the output direction without using a shift clock, provided that the next stage register is empty. Data transmission equipment. (2) The branch determining means determines whether the data is data to be branched based on whether a preset branch condition matches a condition included in the data on the input data transmission path. A data transmission device according to claim 1, characterized in that: