JPS61189301U

JPS61189301U -

Info

Publication number: JPS61189301U
Application number: JP7050585U
Authority: JP
Priority date: 1985-05-15
Filing date: 1985-05-15
Publication date: 1986-11-26

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すブロツク図
、第２図および第３図は従来のこの種上位―下位
コントローラ装置のブロツク図である。図において、１は上位コントローラ、２は下位
コントローラ、３はＰＩＤ調節計、５は設定値信
号、６はＣＡＳスイツチ、１０はＡＳＷアナログ
スイツチ、１１はデツドバンド装置である。なお
、図中同一符号は同一または相当部分を示す。 FIG. 1 is a block diagram showing one embodiment of this invention, and FIGS. 2 and 3 are block diagrams of conventional upper-lower controller devices of this type. In the figure, 1 is an upper controller, 2 is a lower controller, 3 is a PID controller, 5 is a set value signal, 6 is a CAS switch, 10 is an ASW analog switch, and 11 is a deadband device. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims

[Claims for Utility Model Registration] (1) Between the upper controller that performs process control and the ASW analog switch in the lower controller, the normal value at a predetermined period before the control cycle of the lower controller is set to the upper controller's setting value. A process control device characterized in that a dead band device is inserted to store signals as signals. (2) The process control device according to claim 1, wherein the host controller is composed of a computer, a telecontelemeter, etc. (3) The process control device according to claim 1, wherein the lower controller is constituted by a one-loop controller or the like. (4) Claim 1 of the utility model registration claim is characterized in that the lower controller is provided with a PID controller that performs proportional action, integral action, proportional-differential action, proportional-integral action, etc. process control equipment. (5) The process control device according to claim 1, wherein the ASW analog switch is used to store only the previous normal set value signal immediately before a failure of the host controller.