JPS61188783A - Clock isolator circuit unit and data stabilization related thereto - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for stabilizing unstable data inputs, and more particularly to clock isolators for stabilizing unstable data inputs into stable reference clocks. It's about circuits.

(Description of the Prior Art) Generally, electrical signals recorded as data bits on a magnetic recording medium such as a magnetic tape become unstable due to time axis errors inherent in the recording process. Timebase errors are caused by changes in media dimensions due to environmental effects such as elongation of the magnetic tape due to tension applied by a tape feeder, as well as changes in the penetration of the magnetic head chip into the media or differences in relative head-to-media recording and playback speeds. This is caused by such things. In order to stabilize the data or remove time axis errors, unstable data is processed using a time axis corrector (TBC).
) is input to a signal processing means such as however,
In order to convert unstable input data into stable input data within the TBC and to include time base correction for typically one television television line, the signal processing means must A memory circuit containing at least three separate one-line memory elements was required at different input data rates. Each television line of unregulated data is clocked at a clock rate corresponding to the input data rate.
line. One of the memory elements is continuously written to. Index Paluska Television. Identify the start of a line. The data is stabilized by reading the recorded television line from the first memory element and writing it to the second memory element at an internal reference clock rate using an index pulse device with a suitable read output circuit. Because television data is input to each memory element one line at a time, one television line correction is required when the scheme must compensate for data overlap and different data input and data output rates. In order to stabilize the input data over a range, the signal processing means requires a third memory element. This requirement of the signal processing system for memory can be reduced to two memories to stabilize the data power of the television line only when the input data rate is equal to the output data rate and there are no data overlaps. .

OBJECTS AND SUMMARY DESCRIPTION OF THE INVENTION While conventional signal processing means stabilize television human data one line at a time, the present invention's clock
The isolator circuit stabilizes the data one data word at a time, achieving high signal stability and significantly reducing the memory requirements of the signal processing means used in connection therewith.

In the present invention, unstable data inputs are written to successive discrete data addresses of the memory elements of the clocked isolator circuit at a first unstable data input rate. The clock isolator circuit converts this unstable data input into a stable reference clock. The data is then output to the clock at successive discrete data addresses and at a second, faster, stable output rate.
It is read from the evening circuit. Because data cannot be written to and read from the same data address at the same time, the tarock isolator circuit simultaneously monitors the instantaneous write address and instantaneous read address. Furthermore, the circuit of the present invention continuously compares the instantaneous write address with the instantaneous read address and compares the interfering read address of the circuit before an address interference condition occurs, i.e. before the write address is the same as or reaches the read address. includes an interference decoder that generates an inhibit signal to inhibit data output at the time. Once the interference condition is removed, data is read from the read address where the interference occurred. Therefore, all data addresses of the clock isolator circuit of the present invention are read continuously, albeit intermittently.

The stabilized data output of the clock isolator circuit of the present invention can be used alone without further processing, or in conjunction with additional signal processing means.

The clock isolator circuit of the present invention can be constructed with a relatively simple circuit for avoiding data interference in the data output to the signal processing means and stabilizing the data input to a stable reference clock. This stable reference clock speed must be no higher than the data input speed so that inhibiting the data output of the clock isolator circuit effectively reduces the frequency difference between the input data rate and the reference clock speed. No. However, the clock
Because the data input to the isolator circuit is continuous, the data output stall caused by the interferometric decoder has an effective data output rate that is reduced in the direction of (but never less than) the data input rate. Produces intermittent data output.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The clock isolator circuit 10 of the present invention shown in FIG.

It includes a memory element, such as a register file, to receive and store unstable data input. Data input line 9 consists of a plurality of individual connectors. A corresponding data output line 9a connects the memory element 12 to provide a means for transferring data from the memory element 12 to a data usage device external to the clock router circuit 10.
connected to the output of Clock isolator circuit 10
The preferred embodiment includes memory element 14 for receiving the data output of clock isolator circuit 1o via line 9a.
It is adapted to cooperate with a signal processing means 42 (FIG. 21) having the following functions. Write control element 6 receives a data clock input via line 15 to drive write control element 16 at the data clock input rate.

One output of write control element 16 is data control line 1
8 to one input GW of the memory element 12 .

The other output of write control element 16 is connected to write address counter 2o by data control line 19 to provide a divide-by-four (÷4) data clock signal to counter 20.
connected to two inputs.

The reference clock manual line 12 is the reference clock 2. ri divided by 4 (
÷4) signal to one input of clock isolator controller 24.

A read enable data control line 24 is connected from one output of clock isolator controller 24 to an input GH of memory element 12. Clock isolator controller 2
A read enable output line 26 from 4 is also connected to an input of a read address counter 30. A write enable data controller line 28 connects from the second output of the clock isolator control element 24 to one input of the external memory element 140.

In operation, the data input write sequence and data output read sequence of clock isolator circuit 10 occur at the same time. Also, because the data output speed is faster than the data input speed, the data is stored in memory 1
n is read from memory element 12 faster than it is written to n
Ru. Therefore, clock isolator circuit 10 tends to simultaneously write to and then read from the same individual memory address of memory element 12, creating an interference condition. Data must be written to a memory address before it can be read from that memory address, and cannot be associated with the same memory address and written and read at the same time.

According to the invention, the clock isolator circuit 1o has an interference decoder 32 to prevent data address interference.
Contains.

One output of write address counter 20 is connected to interference decoder 32 by data control line 34 and one output of read address counter 300 is connected to interference decoder 32 by data control line 36;
Memory elements 12 are provided with respective instantaneous write and instantaneous read addresses. The interference decoder 32 is also connected to the clock isolator controller 24 by a data control line 38 to provide the inhibit signal generated by the decoder 32 to the clock isolator controller 24.

The operation of the clock isolator circuit of the present invention is as follows. A data clock input provided to write control element 16 on line 15 generates a write enable signal, and a clock input is provided to input GW of memory element 12 via data control line 18 so that data is written to memory element 12. Set the speed at which the data is loaded. In an embodiment of the invention, the data clock rate is 6 MHz. Memory element 12 is responsive to a write enable signal received on data control line 18 to cause storage of the unstable data input on data line 9. This unstable data input is applied to one input of memory element 12 and stored in successive discrete memory addresses of clock isolator circuit 10. The write control element 16 also generates an output signal, which indicates the memory element 1 to which the input data is written.
The write address counter 20 is incremented by one count for each individual data address of two.

A clock isolator controller 24 receiving a reference clock signal on data input control line 22 generates a read enable signal, which is applied to input GR of memory element 12.
The data is transferred from the memory element 12 on the data line 9a to a data usage device external to the clock isolator circuit 10, such as a second memory element 14. This read enable signal is also read address counter 3.
0, and the output data is read out from the memory element 12.
Counter 30 t-
let it proceed.

Each write address counter 20 and read address counter 30 stores successive currants of n successive write addresses WA, WB or successive read addresses RA%RB, respectively.

Such memory addresses are provided to memory device 12 via respective data control lines 34 and 36 to indicate the next address to which data is to be written or read. The signal outputs of counters 20 and 30 are also provided to interferometric decoder 32 via respective data control lines 34,36.

Interference decoder 32 compares instantaneous write addresses WA, WB and instantaneous read addresses RA, RB. These addresses are output by each of the counters 20 and 30.

Because data is read from the clock isorter circuit 10 faster than it is written, the respective write address counter 20 and read address counter 30 sometimes generate coincident addresses. creating an address interference condition. Such an address interference condition exists, ie a matching address occurs, when the instantaneous read address RA, RB is the address at which the input data is to be written next to the memory. If an address interference condition exists, interference decoder 32 provides an inhibit signal to clock isolator circuit 30 via data control line 38 to block memory device 12 until the interference condition no longer exists or advances at least one memory address. Disable read enable signal.

In the preferred embodiment of the invention, the data input on line 9 is 8
A television line input consisting of a continuous data stream of bit-parallel words, these parallel 8-pin, 8-bit parallel words being multiplexed by a clock isolator circuit 10,
A data output consisting of a continuous data stream of 32-bit parallel words is provided over data line 9a. Clock isolator circuit 10 stores index pulses in the data stream to identify the start of each television line.

Input data is multiplexed from four consecutive 8-bit words into one 32-bit word by a clocked φ isolator circuit to satisfy the memory access cycle time of memory device 12. Data multiplexing is only used when the memory integrated circuit is not fast enough to handle the data rate.

Therefore, multiplexing is not necessary to make the clock isolator circuit 10 of the present invention functional.

To perform multiplexing of the input data, the memory element 12 consists of a 4 word x 32 pit register file 12;
This is organized as four independent 4 word x 8 bit register subfiles.

Register file 12 consists of four 8-bit word subfile storage locations tG1, G2), G3, and G4, each subfile providing 4-bit word storage. Each subfile has 4
It is configured as a matrix of bit strings by 8 bit rows, with each row represented by Oll, 2.3. Write address WA%WB is used to address storage locations in each subfile. Write controller 16 provides a subfile write enable signal via control line 18 that identifies the subfile containing the storage location where the input data is to be stored.

The read addresses are arranged similarly except that all addresses of each subfile are sequentially read simultaneously for multiplexing purposes. Table 1 represents the corresponding sequence of addresses and subfile representations for typical non-interfering data storage write and read sequences for clock isolator circuit 10.

Table 1, Word number WA WB G RA RB G
oloolol, to λ4 15011111.213%4 8 0 l 4 29101001.84 313111011.21λ4 This sequence repeats itself as long as there is no address interference. Each read address RA, RB and each write address WA, WB has a period equal to four consecutive subfile write enable signals, and all four subfiles are written to four consecutive 8 bits 1 . register for English
Enabled for simultaneous reading to read one 32 bit data word from file 12.

Data input is written to register file 12 in parallel form by write controller 16, which provides a subfile write enable signal to register file 12 via data control line 18. and write four consecutive 8-bit words to each of the four subfile locations G1, G2), G3, and G4 of register file 12 for each write WA, WB.

Write controller 16 also outputs a divide-by-four (÷4) clock signal (6,QMHz/4)'fr on data control line 19, which advances write address counter 20. The clock signal to the write address counter 20 is a 4-divided clock because the write data input to the register file 12 is continuous, and the counter 20 is automatically advanced by one write address WA, WB, i.e., the register file Advance one for each four consecutive 8-bit words written to 12.

The multiplexed data output of clock isolator circuit 10 can be used directly or can be outputted to any suitable data processing means, such as signal processing circuit 42 as shown in FIG. .

Clock isolator controller 24 is operated by a divided-by-four reference clock signal, which is provided to clock isolator controller 24 on input line 22.

The reference clock 6.75/4MH2 signal clocks both the read enable and write enable signals generated by clock isolator controller 24. The reference clock 22 determines the read address RA, RB sequence rate which is slightly faster than the write address WA, WB sequence rate. The transfer of a 32-bit word from register file 12 occurs in approximately the same time period that four consecutive 8-bit words are input to register file 12. The read enable and write enable signals cause the transfer of data from register file 12 to memory element 14 of signal processing circuit 42 (FIG. 2) as described below.

The read enable signal generated by clock isolator controller 24 is applied to input GR of register file 12 via data control line 26 to register register file 12.
Multiplexed and stabilized tape data is read from successive individual memory addresses of file 12.

The read enable signal generated by counter isolator controller 24 also causes read address counter 304-1 to advance by read address RA, RB for each n 32-bit word output from register file 12. Clock isolator controller 24 also generates a write enable signal, which is provided to circuitry 42 via data control line 28 to cause signal processing circuitry 42 to perform a write sequence.

The stabilized tape data output f' of the clock Φ EyeFray 2 circuit 1o is routed from the successive individual data addresses of the memory element 12 n and simultaneously the successive individual memory addresses of the memory element 14 of the signal processing circuit 42. written to.

In the preferred embodiment, write data input to register file 12 is continuous and uninterrupted. If address interference occurs, interference decoder 32 provides an inhibit signal to clock isolator controller 24, which register file 1
The read enable signal to 2 is prohibited. This inhibit signal prevents the read address counter 30 from advancing to the removal of the interference condition. Therefore, all data addresses of memory element 12 are read continuously. The data output rate must be faster than the data input rate so that read addresses are inhibited to prevent unwanted address interference. This is the register file 12 caused by the inhibit signal of the interference decoder 32.
This is because the cessation of data output results in intermittent data output having an effective data output rate that is reduced in the direction of (but not less than) the data input rate.

Clock isolator circuit 10 may be used to interface with a second circuit, such as signal processing circuit 42.

Data control line 28a from clock isolator circuit 10 is connected to one input of memory element 14 of signal processing circuit 42 to provide stabilized output data input to signal processing circuit 42. Data control line 28a is also connected to write address counter 4 of circuit 42.
Also connected to one input of 5. A data control output line 46 is connected from one output of counter 45 to one input of address selector 47.

Reference clock line 48 is connected to the input of read control element 49. A data control line 50 is connected from one output of the read control element 49 to one input of an address selector 470, which selector 47 selects the memory address input to the memory element 14 on the data control line 55 to the memory element 14. and select. The address selector 47 selects a write address for writing data to the memory 14.
To select a write address location from counter 45 or to read data from memory element 14, a read address location from read address counter 52 is selected. Data control line 60 is connected between the output of memory device 14 and the input of 32-bit to 8-bit converter 56. The operation of the preferred embodiment of clock isolator circuit 10 in conjunction with signal processing circuit 42 will now be described. The regulated data output of clock isolator circuit 10 is transferred to memory via data control line 9ai in synchronization with a write enable signal provided to memory element 12 of clock isolator circuit IO via data control line 28a-k. The signal is input to element 14. Data control line 28a also provides a write enable signal to write address counter 45.

Stabilized data is written to memory element 14 during the write sequence of the first half of a memory cycle, and this data is written to memory element 14 during the read sequence of the last half of a memory cycle. Read from. The regulated data input of clock isolator circuit 10 fully addresses all data addresses of memory element 14 during both write and read sequences to effectively utilize the entire storage capacity of memory element 14. enable. Signal processing circuit 42 identifies the start of each television line by an index pulse maintained in the input data by clock isolator circuit 10.

Address controller 47 controls the inputs and outputs of memory device 14 and the respective write and read address sequences of load address counter 45 and read address counter 52. Multiplexing or serialization of data is controlled by data control line 58;
This controls a 32 bit to 8 bit converter 56 from read control element 49. The regulated data output 57 of converter 56 is at a reference clock rate of 6.75 MHz. Conversion of data from tape speed to reference speed is accomplished by processing the data prior to the memory write sequence by clock isolator circuit 10.

The clock isolator circuit of the present invention is embodied by the preferred embodiment shown in FIG. The circuit in Figure 3 is the fourth
The timing diagrams in the figures are discussed below.

Interference decoder 32 includes PROM A, which has write address inputs WA, WB generated by write address counter 20 and read address counter A.
5 (30) n read address manual RA generated by
, RB. These WA, WB, RA, RB large input FROM A1 is used to write the FROM map (fifth
This map generates the appropriate Q output signal Al-1 which is applied to binary counter A2. Counter A2 is also clocked by the 6,75MH2 reference signal. King. This is inverted by inverter (INV) A7. The output generated by counter A2, i.e., t[-j3-, clocks the clock φ isolator controller 24.

The clock isolator controllers 24 are connected in series n
Flip-flop (F/F) A4 and third F/F
It has A3.

F/F A4 is clocked by the signal output of counter A2. F/F A4 is register file 12
A read enable signal applied to the memory element 14 and a write enable signal applied to the memory element 14 are generated.

F/F A4 advances read address counter A5 and generates a signal output A4-6 which is input to F/F A3 at D (A3-2).

Q output A3-6 of F/F A3 presets F/F A4. Q output A4-8 of F/F A4 is F/F
Clear A3.

The clock isolator circuit 10 is a synchronous binary frequency divider (÷
4) has a counter A23 which is clocked by a 6,75 MHz reference signal which is inverted by an inverter A7; The QA and QB outputs of the counter A23 are applied to the respective D inputs of a pair of parallel-connected F/FAs A24, which are also connected to the inverter A.
7 and clocked by a 75 MHz reference signal. The respective Q and Q outputs (A24-5, A24-8) of F/F A24 are respectively input to binary decoder A25 at A1 and B2. Binary decoder A25 provides four line outputs A25-6, A25-4, A25 to 32-bit to 8-bit converter 56 (FIG. 2).
-5 (Wl, W2) WB, WA) and also F/
Generates output A25-10 to FA-26. This F/F A-26 is also clocked by a 6.75 MHz reference clock which is inverted by inverter A7.

In operation, the FROM AI of the interference decoder 32 is the file write address Φ counter 2.
Receives successive write addresses (WA, WB) input from 0 and receives successive read addresses (RA%R) from file read address counter 30.
B) Receive input.

If FROMAI detects no interference, a low level Q output is provided to binary counter A2. This counter A2
sets the QD output A2-11'i to a low level. If an interference condition is detected, the Q output from PROM A1 goes high 9 and counter A2 generates a positive going transition at A2-11. A low to high transition at the QD output of counter A2 clocks F/F A4 to drive all Q outputs A4-9 to indicate an interference condition. If no interference condition exists, F/F A4's Q output A4-9 remains at a high level. When there is no interference, the high level output state of A4-9 is transferred to the positive going edge of Q output A26-6, Q output A4-5, allowing the data transfer sequence to continue.

In this data transfer sequence, the Q output A24-8 of F/F A24 becomes low level and the Q output of A4
Clearing the output to a low level will inhibit it. Q signal gravity A4-5 is split to provide a read enable signal that advances read address counter 30 and enables reading from memory element 12, and a write enable signal that causes writing to memory element 14. Ru.

Clock Isolator Circuit 0 and associated signal processing circuit 42 may be better understood with reference to timing diagrams 4A-4M.

The 6.7 MHz reference clock input 48 in FIG. 4A to the read control A element 49 is connected to the inverter A.
Inverted by 7. Thus, the negative edge of input 48 at time 1 produces a negative edge divided-by-two (÷2) QA ratio output in bin A23-14 (FIG. 4B) and a negative edge in bin A23-13 (FIG. 4B). (Figure) divided by 4 (÷4) of the negative edge
Binary counter A23 is clocked to generate the QB output. QA to D latch, ie F/F A24,
QB large input] Delayed by clock period nl sont'n
This produces respective Q and Q outputs A24-5 and A24-8 as shown in FIGS. 4D and 4E. 2
Bit binary decoder A25 receives Q and Q outputs A24-5, A24-s and provides four data control output lines A25 as shown in FIG. 4F (1), (2), (3), and (4). -6(Wl)
, A25-7 (W2), A25-4 (W3) and A25
-5 (W4), which are connected by line 58 (FIG. 2) to the input of a 32-bit to 8-bit converter 56. Data word Wl.

W2) W3, W 4 hason -'P n W l,
w2) are read out sequentially from multiplexer 56 for a period initiated by the negative edge occurring at time 3.5.7.9 for w3 and W4.

The data control line is the output A25-10 of decoder A25.
(Fig. 4G) is connected to the D input of F/FA26,
/F A clock input when A26 is clocked by the inverted reference clock output of inverter A7.
The Q output A26-6 of F/F A26 (Figure 4H) serves as a data transfer test pulse for the clock isolator controller 32 which clocks the clock isolator controller by providing it to F/F A4.
Clocking FA4.

If an interference condition occurs in the clock e isolator circuit lO, the FROM AI generates an inhibit signal, which is output from the Q output A
This causes a low level condition at l-1, which remains at a high level for the duration of the interference condition. FROM A1 of A1
This high level output at -1 is applied to the load input A2-9 of counter A2, which causes counter A2 to operate, and fourth, at time 10 in the figure, a low to high level transition occurs at QD output A2-11. to occur.

A high level QD small output at A2-11 is applied to F/FA4, clocking Q output A4-9 to a low level (Figure 4L). Q outputs A4-8 are driven high, releasing the clear state of F/F A3.

The low level state of A4-9 is the D input of F/FA4 A4-2
, the Q output A4-5 of F/F A4 remains at a low level and the Q output A4-6 remains at a high level. This is the Q output A26- of F/FA26 during interference condition.
It is produced by the next positive transition of 6 (Fig. 4H). Since the Q output A4-6 of the clock isolator controller 24 maintains a high level, the read address counter 30 (
A5) is not subject to clock transition and is therefore prevented from advancing.

When the Q output A26-5 of F/F A26 has a positive transition in time period 14 as shown in the fourth engineering diagram because the inhibited Q output A4-6 is at a high level, F /FA3 is clocked, causing Q output A3-6 to go low and Q output A4-9 to high (4th L).
) to remove the inhibited state of A4-9.

FIG. 4J shows a data transfer sequence to memory element 14 including a hypothetical transfer pulse 14a that occurs when an interruption occurs and file read address counter 30 (A5) stops incrementing.

Fourth, the figure shows the output A2-11 of counter A2, which is continuously low level in the absence of interference, has a transition to high level in terms of interference, and is continuous in periods of interference. It is at a high level.

The output of file read address counter 3° (A5) is the fourth serially connected 2-bit address word.
It is shown in Figure M. When there is data interference, circuit 4
There is no data transferred to 2 and written to n, and file read A5 (30) cannot proceed as shown by the dotted line intersection at time 14 in FIG. 4M.

Address interference is shown in Figure 5, where the interference decoder A
This is the first FROM map. FRO in Figure 5
M is such that there are two possible interference conditions for every address combination, namely 0.0 for a given write address WA, WB and two possible read addresses RA where interference occurs.

Encode so that RB occurs (same read address and previous read address). FRO in Figure 5
The M-map shows the interference of all possible read addresses RA, RB with all pledged addresses WA, WB.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a clock isolator circuit according to the present invention, FIG. 2 is a block diagram of a signal processing circuit configured by the clock isolator circuit of the present invention, and FIG. 3 is a block diagram of the clock isolator circuit of FIG. 1. circuit schematic,
4 is a timing diagram for the clock isolator read enable/write enable sequence for the clock isolator circuit of FIG. 3, and FIG. 5 is a FROM mat for the interference decoder of the clock isolator circuit. In the figure, 10 is a clock isolator circuit, 12 is a register file, 14 is a memory element, and 16 is a write controller.
30. 52 is a read address counter 32 is an interference decoder 47 is an address selector 49 is a read controller 56 is a 32-bit to 8-bit converter

Claims (28)

[Claims] (1) In a clock isolator circuit device that converts data input written at an unstable clock speed into data output read at a stable clock speed, (a) a memory element for storing data; (b) (c) means for writing said data inputs to said memory element at separate data addresses and at a first clock speed; and (c) a second clock at separate data addresses and faster than said first clock speed. (d) means for reading said data output from said memory element at a speed of said data; and means for inhibiting reading of data. (2) The writing means (b) described in claim 1 includes a writing effect control element that receives a data clock input and generates a first data control output, and this output is The above device, characterized in that it is applied to the memory element to write data. (3) The reading means (c) as set forth in claim 1 is adapted to receive a second clock input and to transfer data from the memory element to an external source. The device as described above, characterized in that it comprises a clock isolator controller for generating a readable signal applied to the device. (4) The comparing means (d) described in claim 1 includes (a) means for generating a write address; and (b)
and (c) means for generating a prohibition signal. When the output is received and the above-mentioned scheduled relationship becomes an address interference state, it works to generate a prohibition signal. The above-mentioned device is characterized in that it prohibits advance. (5) The device according to claim 4, wherein the address interference condition occurs when the write address is the same as or reaches the read address. (6) The writing means (b) described in claim 4 includes a write control element that receives a data clock input and generates first and second data control outputs, and the first The data control output causes data to be written, and the second data control output causes the write address generating means (a) to advance. (7) The reading means (c) as set forth in claim 4 receives the second clock signal and causes the memory element to transfer data from the memory element to an external source. The device as described above, characterized in that it comprises a clock isolator controller for generating the read enable signal given to it. (8) The write address generating means (a) as set forth in claim 4 includes a write address counter, which receives the output of one of the writing means described in (b) above and writes input data. The counter generates a write address output, which is applied to the memory to cause data storage and provides a write address for comparison. The above-mentioned device is characterized in that the above-mentioned prohibition means (c) is also applied at the same time in order to (9) The read address generating means (b) as set forth in claim 4 is a first address generator for the counter for providing a read enable signal to the read address counter.
first input means to the memory element for providing the read enable signal to the memory element; and connection means provided between the read address counter and the means for generating an inhibit signal. The read enable signal generated by the reading means of (c) above is applied to its first input to continuously advance the read address counter and generate the read address output, and to read the data. The above-mentioned method is also applied to a first input of the memory element to cause reading, and the read address output is applied to the prohibition signal generating means (c) for comparison. Device (10) In a clock isolator circuit device that converts data input written at an unstable clock speed into data output read out at a stable clock speed, (a) a memory element for storing data; ) means for writing data to said memory element at separate data addresses and at a first clock rate; (c) means for generating write addresses; and (d) means for writing data to said first memory element at separate data addresses and at a first clock rate; means for reading the data from the memory element at a second clock speed faster than the clock speed; (e) means for generating a read address; and (f) means for comparing the write address with the read address. receives address output from each write address generation means (c) and read address generation means (e), and prohibits reading of data from the memory element when these two addresses have a predetermined relationship. The above-mentioned device is characterized in that it is equipped with a working means. (11) The device described in claim 10, wherein the comparison means (f) above includes means for generating a prohibition signal. (12) The writing means (b) described in claim 10 is provided with a write control element for writing in four consecutive 8-bit positions, and this write control element is configured to write in four consecutive 8-bit positions. Apparatus as described above, characterized in that it includes means for providing a signal output to said write address generating means (c) so as to advance said write address generating means (c) by one address in response to input of data in two consecutive 8-bit data positions. (13) The device as claimed in claim 10, characterized in that four serially connected 8-bit words are stored in each individual data address. (14) As claimed in claim 10, the data input comprises a continuous stream of serially connected 8-bit words, which are multiplexed into two or more parallel 8-bit words, and at least one 16-bit word. The above-mentioned device is characterized in that it is output as a serial connection word. (15) The above device according to claim 10, characterized in that four 8-bit serial connection words are multiplexed into one 32-bit serial connection word. (16) Claim 10, wherein said data output is transferred for further processing by signal processing means, said signal processing means comprising a second memory element for storing said data output. The above device characterized by comprising: (17) The comparing means (f) described in claim 16 includes a clock isolator control element receiving a reference clock input, and this control element generates a read enable signal and a write enable signal. The read enable signal is applied to the memory element (a) to enable reading of the data output from that memory element, and the write enable signal is applied to the second memory element to enable reading of the data output from the memory element (a). Apparatus as described above, characterized in that it enables writing of said data output to said second memory element at a clock speed. (18) The output data of the memory element (a) as set forth in claim 17 is written in successive individual memory addresses, and the delay caused by the inhibition of the output data address is The above device is characterized in that writing of data to the next write address of the memory element No. 2 is not blocked. (19) The signal processing means according to claim 17 includes means for reading the second memory element data input from the second memory element continuously and without interruption. The above equipment (20) In a clock isolator circuit device that converts data input written at an unstable clock speed into data output read out at a stable clock speed, (a) a memory element for storing data; ) means for writing said data input to said memory element at separate data addresses and at a first clock rate; (c) means for generating write addresses; and (d) means for writing said data inputs to said memory element at separate data addresses and at a first clock rate; (e) means for generating a read address; and (f) comparing the write address with the read address. (g) means for generating a prohibition signal, and the respective address outputs from the write address generation means (c) and the read address generation means (e) are connected to the comparison means (f). The comparing means compares the incoming instantaneous write address with the respective read address, and the inhibiting signal generating means (g) generates an inhibiting signal when the scheduled relationship results in an address interference condition. The device as described above, characterized in that the prohibition signal is applied to the read address generating means until the address interference condition is removed. (21) Data input written to a clock isolator circuit at an unstable clock speed; data output read from said clock isolator circuit at a stable clock speed and forwarded to a signal processing circuit for further processing therewith; In a signal processing device having a combination of a clock isolator circuit and a signal processing circuit for converting the data into a signal, the clock isolator circuit is connected to a memory element for storing data, and the clock isolator circuit stores the data at a separate data address and at a first clock speed. means for writing input to said memory element;
means for reading the data output from the memory element at separate data addresses and at a second clock speed greater than the first clock speed; and for comparing the write address with the read address. , and means for inhibiting reading of data from the memory element when these two addresses have a predetermined relationship, and the signal processing circuit is configured to control the second memory element and the clock isolator circuit. first means for writing said data output to said second memory element; and second means for processing said data output of said clock isolator circuit written to said second memory element. The above device characterized by comprising: (22) In a method of converting data input written to a clock isolator circuit at an unstable clock speed into a data output read from said clock isolator circuit at a stable clock speed, (a) separate data (b) writing said data to said clock isolator circuit at a separate data address and at a first clock speed; and (b) writing said data to said clock isolator circuit at a separate data address and at a second clock speed faster than said first clock speed. (c) Comparing the write address with the read address and inhibiting reading of data from the clock isolator circuit when these two addresses have a predetermined relationship. The above method, characterized in that the method comprises: (23) The step (a) described in claim 22 includes clocking the data input speed, and providing the output to the clock isolator circuit to write data to the circuit. The above-mentioned device is characterized in that it includes causing the above device to perform (24) The step (b) described in claim 22 includes providing a second clock signal to the clock isolator circuit to generate a second clock signal, and providing the second clock signal to the clock isolator circuit. Apparatus as described above, comprising: providing a signal output to a memory element of the clock isolator circuit to effect transfer of data from the memory element to an external source. (25) The step (c) described in claim 22 includes generating a write address, generating a read address, and combining an incoming instantaneous write address with each instantaneous read address. and generating an inhibit signal that inhibits generation of a read address until the predetermined interfering address is removed. (26) The step of generating a write address as set forth in claim 25 includes providing the output from step (a) above to a write address counter to generate a write address for each successive data address to which input data is written. generating a write address output from the counter; applying the write address output of the counter to the memory element of the clock isolator circuit for storing data therein; The device as described above, characterized in that the means for generating the inhibit signal includes simultaneously applying the output of the write address of the counter and supplying the write address thereto for comparison. (27) The step of generating a read address according to claim 25 includes providing a read enable signal to a read address counter of the clock isolator circuit to advance the counter, and outputting a read address from the counter. generating the read address output of the counter, applying the read address output of the counter to the memory element to cause data to be read therefrom, and simultaneously applying the read address output of the counter to a means for generating an inhibit signal for comparison. the above device, further comprising: providing a read address thereto; (28) A method for converting a data input written to a clock isolator circuit at an unstable clock speed into a data output read from said clock isolator circuit at an unstable clock speed, comprising: (a) separate writing said data input to a memory element at a data address and at a first clock speed; (b) generating a write address; and (c) at a separate data address and at a faster than said first clock speed. reading said data output from said memory element at a faster second clock speed; (d) generating a read address; (e) comparing a write address with a respective read address; generating a prohibition signal when a scheduled relationship between addresses results in an address interference condition; (g) prohibiting the read address until the address interference condition is removed; Method