JPS6118868B2 - - Google Patents
Info
- Publication number
- JPS6118868B2 JPS6118868B2 JP10265777A JP10265777A JPS6118868B2 JP S6118868 B2 JPS6118868 B2 JP S6118868B2 JP 10265777 A JP10265777 A JP 10265777A JP 10265777 A JP10265777 A JP 10265777A JP S6118868 B2 JPS6118868 B2 JP S6118868B2
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- base
- semiconductor device
- manufacturing
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 230000003321 amplification Effects 0.000 claims description 6
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000005259 measurement Methods 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
Landscapes
- Bipolar Transistors (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】
この発明は半導体装置の製造方法にかゝり、と
くに半導体装置の製造における電流増幅率の制御
方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of controlling a current amplification factor in manufacturing a semiconductor device.
一例の半導体装置の製造方法を工程順に第1図
ないし第7図に示す。まず半導体基板1にベース
領域不純物がドーブされたCVD(Chemical
Vapor Deposition)膜2を被着する(第1図)。
次に熱処理を施してベース領域21が形成される
(第2図)ついで主面の酸化膜にエミツタパター
ンの開孔2aを設け(第3図)、前記CVD膜2と
異なるタイプの不純物がドーブされたCVD膜3
を被着する(第4図)。次に熱処理を施してエミ
ツタ領域31が形成される(第5図)。このとき
拡散時間を変えてhFEを所定の値ならしめる如く
コントロールする。たゞしPNP構造の半導体装置
ではベース領域Nタイプ不純物拡散と同時にhFE
コントロールすることもある。次いで絶縁膜表面
の安定化のための膜4を被着して(第6図)熱処
理を施し、ベースおよびエミツタの各電極導出用
開孔を施したのち電極材を被着形成し、ベース電
極22、エミツタ電極32を形成し半導体装置が
形成される(第7図)。 An example of a method for manufacturing a semiconductor device is shown in FIGS. 1 to 7 in order of steps. First, a semiconductor substrate 1 is doped with base region impurities by CVD (Chemical
Vapor Deposition) film 2 is deposited (Fig. 1).
Next, heat treatment is performed to form the base region 21 (FIG. 2). Then, emitter pattern openings 2a are formed in the oxide film on the main surface (FIG. 3), and a type of impurity different from that of the CVD film 2 is formed. Doped CVD film 3
(Figure 4). Next, a heat treatment is performed to form an emitter region 31 (FIG. 5). At this time, the diffusion time is changed to control h FE to a predetermined value. However, in a semiconductor device with a PNP structure, the base region N-type impurity diffusion and hFE
It can also be controlled. Next, a film 4 for stabilizing the surface of the insulating film is applied (Fig. 6), heat treatment is performed, and holes for leading out each electrode of the base and emitter are formed, and then an electrode material is deposited and the base electrode is formed. 22, an emitter electrode 32 is formed to form a semiconductor device (FIG. 7).
上記の如くなる半導体装置の製造において、エ
ミツタ領域形成時に電流増幅率を所定の管理幅に
収めこの工程終了以降の熱処理条件を全く同一に
施すも、半導体基板をペレツト化する前に電気特
性を測定すると電流増幅率hFEが極度にバラつ
く。このため所望のhFEの製品が得られず歩留低
下の原因となる。 In the manufacture of semiconductor devices such as those described above, although the current amplification factor is kept within a predetermined control range during the formation of the emitter region and the heat treatment conditions after this process are exactly the same, the electrical characteristics are measured before the semiconductor substrate is pelletized. As a result, the current amplification factor hFE varies greatly. For this reason, a product with the desired h FE cannot be obtained, resulting in a decrease in yield.
この発明は上記従来の欠点を除去するために半
導体装置の改良された製造方法を提供するもので
ある。 The present invention provides an improved method for manufacturing a semiconductor device in order to eliminate the above-mentioned conventional drawbacks.
この発明の半導体装置の製造方法はベース領域
形成後においてエミツタ領域形成前のベースシー
ト抵抗値を測定し、この測定値にもとづき電流増
幅率を設定しエミツタ拡散時間をコントロールし
てエミツタ領域を形成することを特徴とするもの
である。 The method of manufacturing a semiconductor device of the present invention measures the base sheet resistance value after forming the base region and before forming the emitter region, sets the current amplification factor based on this measured value, and controls the emitter diffusion time to form the emitter region. It is characterized by this.
以下に本発明の一実施例につき詳細に説明す
る。製造工程の概要は既に第1図ないし第7図に
よつて説明した如くであり、第5図に示されるよ
うに、エミツタ領域を形成したのちに特性安定化
のための高温処理と電極金属アニール工程を施す
とエミツタ形成時のhFEは変動する。この状態の
一例は第8図によつて示される。すなわち、PNP
構造のトランジスタを夫々のベースシート抵抗ρ
Sの分布によつて205Ω/cm、230Ω/cm、270Ω/cm
の三種類に区分し以下夫々#1,#2,#3と称
する。上記の各々にエミツタ領域を形成した状態
のエミツタIB(IC=50mAとする)を測定する
と第9図aに示す如く、#1,#2,#3の間に
は差が認められない。すなわちほとんど同じ値と
いえる。しかして特性安定化の高温処理と電極金
属のアニール処理を経ると第9図bに示す如きエ
ミツタIB(IC=100mA)の分布を示す。上記
は要するにベースシート抵抗ρSとIBの工程によ
るシフトによるものであり、さらに精密に調査し
て第10図に示す如く#1、#2、#3の間にベ
ースシート抵抗ρSが高いほど工程シフトが大き
いことが明確となつた。第9図bの如くなれば要
求されるhFEのレンジが図示の「θ」にたいし、
#1は60%、#2は33%、#3は0%と大差を示
す。 An embodiment of the present invention will be described in detail below. The outline of the manufacturing process has already been explained with reference to Figures 1 to 7, and as shown in Figure 5, after forming the emitter region, high temperature treatment and electrode metal annealing are performed to stabilize the characteristics. Depending on the process, the h FE at the time of emitter formation varies. An example of this state is shown in FIG. That is, PNP
Structure of transistors with respective base sheet resistance ρ
205Ω/cm, 230Ω/cm, 270Ω/cm depending on S distribution
They are divided into three types and are hereinafter referred to as #1, #2, and #3, respectively. When the emitter I B (assuming I C = 50 mA) is measured with emitter regions formed in each of the above, no difference is observed between #1, #2, and #3, as shown in Figure 9a. . In other words, it can be said that the values are almost the same. After high temperature treatment for stabilizing the characteristics and annealing treatment of the electrode metal, the emitter I B (I C =100 mA) has a distribution as shown in FIG. 9b. The above is basically due to a shift in the base sheet resistance ρ S and I B due to the process, and a more precise investigation revealed that the base sheet resistance ρ S is high between #1, #2, and #3 as shown in Figure 10. It became clear that the larger the process shift, the greater the process shift. If it becomes as shown in Fig. 9b, the required range of h FE is relative to “θ” shown in the figure.
#1 shows a large difference: 60%, #2 33%, and #3 0%.
上記から最終的のhFEを一定にするためにベー
スρSに合わせてhFEをコントロールすればよい
との結論に至る。そして所望のhFEを備える半導
体装置が得られるという顕著な利点を有する。 From the above, it is concluded that h FE should be controlled in accordance with the base ρ S in order to keep the final h FE constant. This method has the remarkable advantage that a semiconductor device having a desired h FE can be obtained.
第1図から第7図までは半導体装置の製造方法
を工程順に示すいずれも断面図、第8図はウエハ
のベースρSの分布を示す図、第9図a,bは半
導体素子のIBの分布を示す図、第10図はベー
スρSとhFEの相関を示す図である。なお図中同
一符号は同一または相当部分をそれぞれ示すもの
とする。
21……ベース領域、22……ベース電極、3
1……エミツタ領域、32……エミツタ電極、ρ
S……ベースシート抵抗値、hFE……電流増幅
率。
Figures 1 to 7 are cross-sectional views showing the manufacturing method of a semiconductor device in the order of steps, Figure 8 is a diagram showing the distribution of the base ρ S of the wafer, and Figures 9 a and b are diagrams showing the I B of the semiconductor element. FIG. 10 is a diagram showing the correlation between the base ρ S and h FE . Note that the same reference numerals in the figures indicate the same or corresponding parts, respectively. 21...Base region, 22...Base electrode, 3
1... Emitter region, 32... Emitter electrode, ρ
S ...Base sheet resistance value, hFE ...Current amplification factor.
Claims (1)
後においてエミツタ領域形成前のベースシート抵
抗値を測定し、この測定値に基づき電流増幅率を
設定しエミツタ拡散時間をコントロールしてエミ
ツタ領域を形成することを特徴とする半導体装置
の製造方法。1. In manufacturing semiconductor devices, the base sheet resistance value is measured after the base region is formed and before the emitter region is formed, and the emitter region is formed by setting the current amplification factor based on this measurement value and controlling the emitter diffusion time. A method for manufacturing a featured semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10265777A JPS5437477A (en) | 1977-08-29 | 1977-08-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10265777A JPS5437477A (en) | 1977-08-29 | 1977-08-29 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5437477A JPS5437477A (en) | 1979-03-19 |
JPS6118868B2 true JPS6118868B2 (en) | 1986-05-14 |
Family
ID=14333292
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10265777A Granted JPS5437477A (en) | 1977-08-29 | 1977-08-29 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5437477A (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5989429A (en) * | 1982-11-15 | 1984-05-23 | Mitsubishi Electric Corp | Manufacture for semiconductor device |
JPH0752750B2 (en) * | 1985-11-08 | 1995-06-05 | 松下電子工業株式会社 | Method for manufacturing semiconductor device |
-
1977
- 1977-08-29 JP JP10265777A patent/JPS5437477A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5437477A (en) | 1979-03-19 |
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