JPS6118866B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a bipolar transistor parasitic to a complementary field effect transistor (hereinafter abbreviated as C/MOS).
The present invention relates to a semiconductor device that eliminates the drawbacks caused by. Various C/MOS circuits have been known in the past, and typical examples thereof will be explained with reference to FIGS. 1 and 2. This inverter circuit is composed of a p-channel MOS Trθ ₁ and an N-channel MOS Trθ _2. The source electrode of θ ₁ is connected to the positive power supply V _DD , and the drain electrode of θ ₁ is commonly connected to the drain electrode of θ ₂ . At the output end, the source electrode of θ ₂ is connected to the negative power supply V _SS . Further, the gate electrodes of θ ₁ and θ ₂ are both connected to the input terminal to form an inverter. FIG. 2 is a cross-sectional side view of this circuit formed on a semiconductor wafer. In this example, a so-called P-well layer 2 made of P-conductivity type impurities with a concentration of about 2× ^{10 16 atoms} /cm ³ is formed on an N-conductivity type substrate 1 with a concentration of about 1×10 15 atoms/cm ³ . , a P channel MOS Tr is formed on the N conductivity type substrate outside this P-well layer 2.
Diffuse regions 3 and 4 (eg, 10 ¹⁹ atoms/cm ³ ).
On the other hand, there is also an N-channel MOS in the P-well layer 2.
N conductivity type impurities are added to the N regions 5 and 6 which become Tr at 10 ²⁰ at
Diffuses about oms/ ^cm3 . Furthermore, P- and N-type diffusion regions 7 and 8 are formed in the P-well region 2 and the rest of the semiconductor substrate 1 to be connected to a power source. Following this, approximately
A thin layer of silicon oxide with a thickness of 1500 Å is deposited, holes are opened in the necessary areas, and a circuit is connected using a conductor such as Al. If necessary, a C/MOS semiconductor element can be obtained by providing a protective film on the substrate. This process is schematic and is provided as an example. A C/MOS circuit with such a structure has P
Since the threshold voltages Vth of the channel MOS Tr and the N-channel MOS Tr have opposite polarities, they operate completely opposite to the input voltage, and their operating power is very small. For example, when _VDD is +5V and _VSS is grounded (GND), if +5V is supplied to the input In, θ
₂ is conductive (ON), _θ1 is non-conductive (OFF), and no direct current flows between V _DD and V _SS . Conversely, if OV is supplied to the input, θ ₂ will turn OFF and θ ₁ will turn OFF.
It becomes ON, and similarly, no DC current flows between V _DD and V _SS . Therefore, C/MOS circuits generally consume almost no operating power, and in the pulse transient region of input information, θ ₁ θ
₂ are both turned on, and only an instantaneous transient current flows, a leakage current that occurs in the PN junction, and a current to charge and discharge the load capacity at the output. Therefore, it can be said that the power of a C/MOS circuit is generally extremely small. However, in such a C/MOS circuit system, when noise is added to the output or input by impulse, a large DC current (several tens of mA to several hundred mA) flows between V _DD and V _SS .
A) flows, and even after the noise is removed, a phenomenon has occurred in which the current continues to be maintained steadily. this
The polarity of the impulse can be positive or negative, and to eliminate this phenomenon, it is necessary to lower V _DD below a certain voltage or turn off the power to the circuit system. The present invention provides a novel semiconductor device that eliminates the above-mentioned drawbacks. That is, it was completed based on the fact that it was discovered that a specific thyristor circuit is constructed in a semiconductor device having a C/MOS structure. FIG. 3 is a cross-sectional side view showing this thyristor circuit formed in a C/MOS circuit, and FIG. 4 is an equivalent circuit diagram thereof. This is multiple bipolar
It is made up of transistors, and once thyristor operation occurs, the power is often enormous. To explain this thyristor circuit with reference to FIG. 3, in the P-well region 11 formed in the N-type semiconductor substrate 10, parasitic bipolar transistors Tr ₂ and Tr ₄ are formed along the thickness direction of the semiconductor substrate.
In addition, in the semiconductor substrate 10 outside the P-well region 11, there are parasitic transistors Tr 1 and Tr ₁ in the direction perpendicular to the thickness direction of the semiconductor substrate.
In addition to forming Tr ₃ , the thyristor circuit is constituted by the P-well region 11 and the resistor held by the N-type semiconductor substrate 10. In addition, N ⁺ regions 12, 13, which constitute the source and drain necessary for C/MOS,
P ⁺ regions 14 and 15, a P ⁺ region 16 and an N ⁺ region 17 which serve as contact regions are formed, and a guard ring layer 18 is further formed. In the following explanation, α is the current amplification rate generally defined as a bipolar transistor term, β is the current amplification rate defined as α/1-α, I is the current, e is the signal attached to I, and b is the emitter. is the base, C is the collector, and the numbers mean each transistor and resistor. As shown by the solid arrow in Figure 4, when positive impulse noise is added to the output, the current α ₃ × Iin changes to RP−
The flow bypasses the well area and its voltage drop is
When Vbe reaches ₂ , current Ib ₂ flows through the base of Tr ₂ . Ib ₂ α ₃ Iin (RP−Well≫rbe ₂ ) (1) If the collector current of Tr ₂ is Ic ₂ , then Ic ₂ = β ₂ Ib ₂ = β ₂ α ₃ Iin (2) Similarly, Ic ₂ is the drive current So when the voltage drop across _RNSub becomes Vbe ₁ , the base current of Tr ₁
Ib ₁ flows and Tr ₁ becomes ON state. Ib ₁ = Ic ₂ (R _NSub 〓rbe ₁ ) (3) Ic ₁ = β ₁ Ib ₁ = β ₁ β ₂ α ₃ Iin (4) Next, even if external noise is removed, V _DD −
In order for the current to be maintained between GND, that is, between Tr ₁ and Tr ₂ , the following condition should be satisfied: Ib ₂ ≦Ic ₁ (5). That is, α ₃ Iinβ ₁ β ₂ α ₃ Iin ∴1≦β ₁ β ₂ (6) Also, when the condition 1<β ₁ β ₂ is satisfied, the base current in the next cycle is calculated from the base current Ib ₂ ' in one cycle.
Since _Ib2 '' becomes large, when the current flowing through the system increases by repeating the thyristor, β starts to decrease after reaching βmax, so it does not diverge infinitely.In other words, in a steady state, the above-mentioned abnormality does not occur. It is thought that the current will settle down when the following two conditions are met at the same time: Ib ₂ (n-1) = Ib ₂ (n), β ₁ (n)・β(n) ≧ 1 Also, the dimensions of the previous Tr Although the size is not the main factor in the likelihood of the abnormal current flowing, we will consider it based on the above equation.The current amplification rate was measured using the size of the transistor size (more precisely, the drain area) as a parameter. However, the current value when the abnormal current subsides is
There is a correlation with the size of the transistor, and the larger the drain area of the transistor, the larger the abnormal current, and the smaller the abnormal current.
The value of Tr becomes smaller. Also, even if negative noise is added to the output, at the same time as positive noise, Ib ₁ α ₄ Iin (R _NSub 〓rbe ₁ ) (7) Ic ₁ = β ₁ Ib ₁ = β ₁ α ₄ Iin Ib ₂ = Ic ₁ ( RP−Well≫rbe ₂ ) Ic ₂ = β ₂ Ib ₂ = β ₁ β ₂ α ₄ The conditions for maintaining the Iin system current are Ib ₁ ≦Ic ₂ 1≦β ₁ β ₂ (8) . From the description so far, the abnormal current due to the operation of the thyristor circuit is calculated by dividing the β product of the lateral Tr and vertical Tr by 1.
I found that it would be better to make it smaller. However, the inventors have found that the abnormal current can be prevented even if the β product, which is this condition, is 1 or more. As a result of tracking this phenomenon, we found that there is a correlation between the way the contact hole is formed and the abnormal phenomenon described above. By the way, in the circuit constituting the C/MOS inverter, the power supplies V _DD and V _SS are set so that V _DD is at the same potential as the N-type semiconductor substrate, and V _SS is at the same potential as the P-well region. In order to bring the N-type semiconductor substrate or the P-well region to the same potential, N ⁺ P ⁺ regions are formed to connect the sources of the P-channel Tr and the N-channel Tr to the power source. Therefore, the current C/
When an external noise trigger signal is applied to the thyristor circuit shown in FIG. 4 in the MOS circuit, a current will necessarily flow through the power supply circuit before forming the bipolar transistor that forms part of the thyristor circuit. Therefore, based on this current, the product of the resistance of the N-type semiconductor substrate and the P-well region and this current becomes a bipolar transistor only when the base-emitter threshold voltage Vth required for operating as a bipolar transistor is reached. It operates as a thyristor circuit. If lateral Tr
If the current does not reach Vth, even if a certain amount of current flows instantaneously, the phenomenon of holding and continuing to flow will not occur. Therefore, in order to further reduce Vth when the current is constant, the problem is how much the resistance between the semiconductor substrate and the P-well region can be reduced. For this purpose, P ⁺ N ⁺ to make it the same potential as the power supply.
It is important to shorten the paths of the contact holes for connecting the power supply lines to the diffusion layer to the N-type semiconductor substrate and the P-well region, respectively. Here, if you change the way the contact holes are made, the lateral Tr and vertical Tr will cause abnormal current.
Table 1 shows the results of investigating the β product of Tr.

[Table] In this table, going from E to A
Since RNsub and RPWell (P-Well region resistance) tend to increase, the likelihood of abnormal currents occurring is in the order of A→E, with E being the least likely to occur.
FIG. 5 shows how to make this contact hole. Here, if A is contacted only through the 8μ port, B is the transistor θ ₁ with the pattern shown in Figure 5.
If contact is made on the bottom side, and if the transistor θ is ₂ , contact is made on the top side, C is made on the top and bottom sides of B and 1/2 of the left and right sides, E is on the top and bottom side. Contacts were made surrounding the MOS transistors on the left and right sides. Also, contact holes A to E and abnormal current starting voltage V _DD Min
As shown in FIG. 6, the results of an experiment investigating the relationship between the abnormal current starting voltage V _DD MiN vary depending on the contact hole positions A to E. In other words, the probability of abnormal current occurring is A<B<C<D<E, which indicates that the occurrence of abnormal current is controlled by the way the contact hole is formed.
It can be seen from FIG. 6 that V _DD MIN increases as the Nsub resistance is added to the contact hole resistance. Furthermore, by deepening xj in the P-well region, the current amplification rate β
Even if the contact hole is made smaller, the contact hole is A,
It is not effective for B and C, but it is effective for D and E. However, it was found that when determining D and E, the β product of both Tr was ≧1. Next, the characteristics when the contact hole is formed as D is explained with reference to FIG. This is taken with the horizontal axis as the base width (W _L ) of the parasitic lateral Tr, the vertical axis as the abnormal current value and abnormal current starting voltage V _DD MiN, and the slumping time (time of thermal process to lower xj) as a parameter. It is a diagram. Here, the base width of the lateral Tr is the width between the P ⁺ regions 14 and 15 and the P-well region 1.
It means a distance of 1. Also, the base width of the Vertical Tr corresponds to the semiconductor substrate 10 and the N ⁺ regions 12 and 13, and is equal to the value obtained by subtracting the depth of each diffusion region from the depth xj of the P-well region (in the thickness direction of the semiconductor substrate). Become. In FIG. 7, the solid line indicates when the P-well region was slumped for 20 hours, the dashed line indicates when slumped for 40 hours, and the broken line indicates when slumped for 60 hours. As seen in Figure 7, W _L = 50μ
In this case, there is an abnormal current, but when W _L = 70μ, no abnormal current occurs at all. Both of these are Lateral Tr.
Although the β product of the Vertical Tr is >1, this means that the base width of 50 μm can be considered as a critical condition for the contact hole formation method D. This is because when W _L =50μ or more, as can be seen from FIG. 7, the β product is >1 for all W _v , but no abnormal current occurs. In other words, W _L = 50μ
The slumping time of P-Well is 20 hours (W _v ~
52.4μ) is considered to be a necessary condition. here
From Figure 8, which shows the relationship between the base width W _v of the Vertical Tr and β, and Figure 9, which shows the relationship between the base width W _L of the Lateral Tr, and β, the base width W _v = 52.4.
Determining β of μ, W _L = 50 μ, β _v = 2.0×10 ² ,
β _L = 2.4×10 ^-2 and β product is 2.0×10 ² ×2.4×10 ^-2
= 4.8, which is greater than 1. Base width W _L of these Lateral Tr and Vertical Tr
The relationship with the base width (PWell diffusion depth xj) is shown in Figure 10. In other words, if the contact hole is not taken into consideration, latch-lap will occur if the β product is not less than 1, but if the contact hole is located at D or E as shown in Figure 5, Even if the β product is 4.8, the latch-up phenomenon can be prevented even if the β product is 8.1 if E is taken properly. This shows that the value of the left side 1 of the above-mentioned inequality 1≦β ₁ β ₂ can change depending on how the contact hole is formed. Here, as an experimental formula, we obtain the current amplification rate β = Kexp (-aW) (10) and also adopt δ as the method of forming the contact hole to express the conditions under which abnormal current does not occur.
An empirical formula showing the relationship between the base width of the lateral Tr and the base width of the vertical Tr was obtained. Note that in equation (10), k and a are the corollary W, which means the base width of the parasitic bipolar Tr. W _L > 1/mInk _L kv/δ-n/mW _v (11) Here, W _L and W _v are Lateral Tr and Vvrtical Tr
The base width of K _L Kv is the Lateral Tr in equation (10) and
The k (coefficient), n and m of the Vertical Tr are expressed in equation (10).
It shows a (coefficient) of Lateral Tr and Vertical Tr. If the contact hole is determined to satisfy the above experimental formula, even if the β product of the parasitic bipolar transistor is greater than 1, this operation can be contained and abnormal current caused by the thyristor circuit can be prevented. In this way, β of Lateral Tr ₁ and Vertical Tr ₂
Even if the product is 1 or more, the contact hole may be formed so as to satisfy δ in the above experimental formula. In other words, even if the β product of Lateral Tr ₁ and Vertical Tr ₂ is 1 or more, the operation of both Trs can be contained by making the sources of the P-channel MOS Tr and N-channel MOS Tr and the semiconductor substrate the same potential. I can do it. In other words, the contact hole should be formed depending on the distance to the collector of both types of Tr, that is, P for Lateral Tr ₁ .
-The distance to the Well region, and in Vertical Tr ₂ to the semiconductor substrate, that is, the value obtained by subtracting the xj of the drain and source diffusion layers created in this region from the xj of the P-well region, is reduced, and this parasitic bipolar The threshold voltage between the base and emitter of the Tr is
All you have to do is take care to keep it at around 0.5V. Incidentally, the contact hole naturally has the role of transmitting charges from V _DD and GND, that is, the power source, to both MOS type transistors, but it also has the role of transmitting the charge from the power supply to both MOS type transistors, and the contact hole also has the role of transmitting the charge from the power supply to both MOS type transistors, and the contact hole also has the role of transmitting the charge from the power source to both MOS type transistors, but also the contact hole has the role of transmitting the charge from the power source By controlling the path to the substrate and limiting the threshold voltage between the base and emitter of the parasitic bipolar transistor,
It becomes possible to block the operation of the Tr. There are two types of parasitic bipolar transistors: lateral transistors and vertical transistors, and as mentioned above, the abnormal current generated by the operation of the thyristor circuit is cycled repeatedly by transistors ₁ and ₂ . From this point of view, there is an idea that it is sufficient to control either one of the Tr ₁ and Tr ₂ . However, it should be noted that there is no problem in using the above-mentioned means in combination to block the operation of both or one of Tr ₁ and Tr ₂ . Specific pattern layouts are shown in FIGS. 11 to 26, and the dashed lines in the figures indicate contact holes. In Figures 11 to 26, 11th, 12th, 1st
Figures 7, 18, and 21 show the case where the contact regions 16 and 17 are adjacent to each other throughout the source regions of MOS Trθ ₁ and θ ₂ , and the others are MOS Trθ
₁ and θ ₂ are adjacent to each other in part of the source region. Further, FIGS. 11, 17, and 21 show the contact regions 16 and 17 and their respective MOS Trθ
₁ and θ ₂ are interconnected through the same contact region. Furthermore, FIGS. 11, 12, 17, 18, and 21 show cases in which the contact region is formed to surround the MOSTr. Further, FIGS. 11 to 26 show a case where at least a portion of the first contact region and the second contact region are formed adjacent to each other. In this way, the present invention can solve both types of parasitic bipolar transistors.
Even if the β product of This can prevent abnormal currents. As described above, the present invention has extremely great practical effects.

[Brief explanation of the drawing]

Figure 1 is a conventional C/MOS circuit diagram, Figure 2 is a cross-sectional view of the circuit in Figure 1 created on a semiconductor substrate, and Figure 3 is a cross-sectional view of the circuit in Figure 1 created on a semiconductor substrate.
4 is an equivalent circuit diagram of a thyristor circuit formed in a C/MOS circuit element, and FIG. 5 is a plan view of a semiconductor device showing the positions of contact holes. Figure 6 is a diagram showing the relationship between the ease of occurrence of abnormal current and the position of the contact hole, with the contact hole position in Figure 5 taken as the horizontal axis and the abnormal current generation voltage and Vth as the vertical axis.
The figure shows the relationship between the base width of the lateral transistor on the horizontal axis and the abnormal current starting current on the vertical axis.
The figure shows the relationship between the base width of the Vertical Tr and the current amplification rate, Figure 9 shows the relationship between the base width of the Lateral Tr and the current amplification rate, and Figure 10 shows the relationship between the base width of the Lateral Tr and the current amplification rate.
11 to 26 are plan views showing the pattern layout applied to the present application. 10... Semiconductor substrate, 11... Diffusion region, Tr ₁
~Tr ₄ ... Parasitic bipolar Tr.

Claims (1)

[Scope of Claims] 1. An impurity region of a second conductivity type is formed in a semiconductor substrate of a first conductivity type, and a first contact connects the semiconductor substrate and a first power source to the semiconductor substrate outside the impurity region. a first MOS type transistor having a channel of a second conductivity type and a second contact region connecting the impurity region and a second power source to the impurity region; 2. A semiconductor device forming a second MOS transistor, wherein at least a portion of the first contact region and the second contact region are formed adjacent to each other. 2. The semiconductor device according to claim 1, wherein the first contact region is formed to surround the first MOS transistor. 3. The semiconductor device according to claim 1, wherein the second contact region is formed to surround the second MOS transistor.