JPS6118756B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a musical tone generating device that digitally synthesizes a plurality of reference waveforms to generate a musical tone. In electronic musical instruments such as electronic organs, electronic pianos, and synthesizers, creating various musical sound waveforms corresponding to musical tones is an important element in order to obtain musical tones with timbre. There are various ways to create this musical sound waveform. For example, each sine wave from the fundamental wave to the desired order of harmonics, which are related to overtones, is sequentially divided into multiple storage devices using digital signals representing the amplitudes. The sine waves of a desired order are stored in memory, and are selectively and simultaneously read out according to a musical tone designation, and are synthesized to obtain a musical sound waveform of a predetermined shape. In addition, a one-cycle musical sound waveform of a specific shape is digitally fixedly stored in a waveform storage device, and this musical sound waveform is read out using a clock signal of a frequency corresponding to the key. , square wave, and sawtooth wave are memorized in advance, and when playing,
There is a method that selects one reference waveform and uses it as a musical sound waveform. However, with the above method, it is not possible to arbitrarily create musical sound waveforms with a large number of different tones, let alone natural instruments, and there is also a limit to the types of musical sound waveforms, so it is not possible for the performer to arbitrarily create musical tones of his/her preference. I couldn't take it out. In view of the above points, it is an object of the present invention to provide a tone waveform device that generates a plurality of reference waveforms through digital arithmetic processing and synthesizes them to obtain a tone waveform. An embodiment of the electronic musical instrument according to the present invention will be described below with reference to the drawings. FIG. 1 shows the overall schematic circuit configuration, and 1 is the reference clock signal output from the pulse generator 2 (in this example, the frequency base is 1 μm).
This is a control signal generation circuit that generates and supplies various control signals, which will be described in detail later, to control the entire circuit configuration based on a frequency of 1,000 KHz. 3 is a group of external performance operation keys, in this case 84 keys corresponding to a piano keyboard. One end of these performance operation keys is connected in common and a predetermined potential VD is always set, and the other end is an independent performance operation key that includes means for generating a timing signal for sequentially scanning and selecting each of the performance operation keys. The input detection circuit 4 is coupled to the input detection circuit 4 of FIG. That is, this input detection circuit 4 receives 8 μs from the various control signal generation circuit 1.
Count the periodic signal and this 8μs periodic signal to 1
The timing signal is generated periodically according to the count value of the scale-octave counter 5 for obtaining two-tone scale data and seven-octave octave data,
It also has a key input circuit that reliably obtains individual single-shot operation key input signals for each performance operation key, especially when a plurality of performance operation keys are pressed simultaneously during performance. The output signal of the final count value of the scale-octave counter 5 is supplied to a keyless control circuit 7 which is supplied with an operation signal from a sustain instruction switch 6 and the timing signal of the performance operation key from the input detection circuit 4, which will be described in detail later. It is also applied to the input detection circuit 4. This keyless control circuit 7 detects that a performance operation key has not been operated for a predetermined period of time or more, and outputs a key presence signal (keyless inverted signal) and a new key input detection circuit 4 from the key input detection circuit 4. The key presence signal is the various control signal generation circuit 1
The signal is also supplied to various control circuits 8, which will be described later, as a synchronization control signal for the performance operation keys. Here, as will be explained in detail later, numeral 9 is a 24-bit octave specified data memory consisting of three 8-bit series shift registers arranged in parallel, and numeral 10 is a 40-bit data memory consisting of five 8-bit series shift registers arranged in parallel. Octave bit memory for creating an octave reference clock; 11 is memory for pitch clock number control consisting of one 8-bit serial shift register (hereinafter referred to as Fa memory); 12 is four 8-bit serial shift registers. The scale specification data memory 13 consists of 32 bits arranged in parallel, and 13 addresses the number of steps in one cycle period for each cycle in the repetition cycle of a musical tone consisting of 48 bits, which is made up of six 8-bit series shift registers arranged in parallel. 14 is an 8-bit serial shift register 1.
A period control memory (hereinafter referred to as Fb memory) that takes the phase period between the musical tone cycle and the period associated with the period change command described later. 15 has four 8-bit series shift registers arranged in parallel. Envelope memory that digitally stores successive changes in the volume envelope value consisting of 32 bits, 16 consisting of one 8-bit serial shift register, and synchronization that synchronizes the clock signal for the volume envelope with the musical tone cycle. Memory (hereinafter referred to as Fc memory), 17 is an 8-bit serial shift register 1
An active memory (hereinafter referred to as Fd memory), which stores whether or not the line memory of the volume envelope memory 15 is in operation;
This memory (hereinafter referred to as Fe memory) consists of one bit series shift register and stores whether the volume envelope is in an attack state or a release state. These memories 9, 10, 11, 12, 1
3, 14, 15, 16, 17, 18 are all 1
Shift up sequentially with a μs periodic signal, and 1 in 8 μs.
8 line memories K0, K1, K2, K3, K4, K5, K6, K
7, and therefore, up to eight types of scale designation data, octave designation data, tone waveform, and volume envelope can be set independently for each line memory. For example, even if you operate up to 8 performance keys at the same time,
All performance operation keys can be input, and all memories 9, 10, 11, 12, 13, 14, 1
Line memories 5, 16, 17, and 18 are made to correspond to the performance operation keys in order. The scale data of the scale-octave counter 5 is input as 4-bit parallel data to the scale specification data memory 12 via the correction scale data creation circuit 19, and the octave data is input to the adder 21 along with the correction octave value from the correction octave data creation circuit 20. is supplied, and the 3-bit parallel data from this adder 21 is input to the octave designation data memory 9. The correction scale data creation circuit 19 and the correction octave data creation circuit 20
is controlled by a combination of various octaves from the ensemble octave instruction key 22, and in a state where there is no ensemble instruction, a duet instruction state, and a quartet instruction state, the regular octave (referred to as one octave) +2, +3, +4 octaves are set for the scale data, and especially in the case of +3 octave setting, the corrected scale data creation circuit 19 adds +7 to the scale data.
Then, corrections are made to the regular scale and octave data. The correction octave data generation circuit 20 also receives K0, K1, K2, K3, which will be described later from the various control signal generation circuit 1.
A timing signal for specifying the line memory is supplied, and the timing signals K0 and K are output from the output according to the specified state of the octave combination.
1, K2, and K3 to the various control circuits 8,
Memory 9, 10, 11, 12, 13, 15, 1
6 and 17 will be controlled. Further, the duet octave instruction key 22 is supplied to the duet control circuit 23, and when a duet or quartet is commanded here, the command signal is applied to the various control signal generation circuit 1 and the designated line memory for the memories 9 to 18 is input. The timing is controlled so that a plurality of line memories are designated for a single performance operation key in the case of a duet command, and four line memories are designated in the case of a quartet command. The musical tone control circuit 24 includes envelope attack time indicating switches M1-M2, M1-M2, M for each musical tone, .
1-M2, M1-M2, release time indication switch N1-N2, N1-N2, N
1-N2, N1-N2, period time indication switch O1-O2, O1-O2, O1
-O2, O1-O2, rise difference indication switch P, P, P, P, waveform indication switch Q1-Q2-Q3, Q1-Q2-Q
3, Q1-Q2-Q3, Q1-Q2
-Q3, vibrato instruction switch R, R,
R, R, octave engine indicator switch S
, S, S, S, phase difference indicating switch T
1-T2, T1-T2, T1-T2,
T1-T2, and overlapping slight difference instruction switch U1-U2, U1-U2, U1-U
It is set by a selective combination instruction in the musical tone control instruction key group 25 having 2, U1-U2. This musical tone control instruction key group 25 includes K0', K1', K2',
A K3' signal is provided. Moreover, the musical tone control circuit 24
Various time setting signals from a time measurement circuit 26 that counts 8 μs periodic signals are applied to create various periodic clock signals. That is, the musical tone control circuit 24
From here, there is a rising clock signal φs used to determine the rise time difference, an attack "0" signal that does not specify an attack, an attack clock signal φ _A for determining the attack time, and a release clock signal φ _R for determining the release time. , a periodic clock signal φ _T used to determine the period time, a delay indication or no signal in the case of a duet, a fixed or floating, rectangular, sawtooth, or triangular waveform indication signal that determines the musical waveform, an octave change indication signal, and a vibrato change. It outputs a -1/64 instruction signal, a +1/64 instruction signal, and a phase difference instruction signal to give to the various control circuits 8. The octave designation data memory 9 is an adder 2.
The octave designation data starting from 1st is stored circularly in each line memory, and the 3-bit octave designation data output from the last line memory is stored in the addition control circuit 27 corresponding to each of the 7 octaves from 1st to 7th. It is decoded and supplied to the adder 28 as different addition commands for each octave. That is, +1 for the first octave designation, +2 for the second octave designation, +4 for the third octave, and +4 for the fourth octave designation.
+8 for octave, + for 5th octave specification
16, 6th and 7th octave designations are supplied as 0 addition commands. This adder 28 adds the octave addition values of each line memory of the octave bit memory 10 and each corresponding line memory of the octave designation data memory 9 every cycle (8 μs time), and inputs the addition result to the octave bit memory. The signal is supplied to the side leading line memory for cyclic storage, and a carry signal accompanying this addition is output. That is, the addition control circuit 27
The output of is connected to the adder 28 in such a way that the higher the specified octave, the larger the added value, and therefore,
The higher the octave, the faster the output cycle of the carry signal from the adder 28 becomes.
An octave reference clock frequency signal corresponding to each octave designation data set in the octave designation data memory 9 and serving as a reference for the octave is obtained. Further, the addition control circuit 27 performs an octave shift up operation that increases by +1 (double the octave) with respect to the regular octave stored and set in the octave designation memory 9, in response to the octave change instruction signal from the musical tone control circuit 24. Contains circuits. The scale designation data stored in the scale designation data memory 12 is cyclically stored in the first line memory on the input side, and the 4-bit output from the last line memory is supplied to the scale decoder 29, where 12
The signals are supplied to a scale clock selection circuit 30, which will be described later, through 12 output lines corresponding to the scales. Each line memory of the address memory 13 stores an address step count value for one cycle of a musical tone. In this embodiment, one cycle period of a musical tone is set to 64 steps, and is expressed in decimal numbers from 0 to 63 (2).
In base numbers, it is expressed as a count value state of 6 bits "000000" to "111111"). The 6-bit parallel address step count value sequentially output from the last line memory of the address memory 13 passes through the address step number detection circuit 31 and the step number detection matrix circuit 32, and is transferred to the adder 33. At 33,
A pitch clock frequency signal, which will be described in detail later, corresponding to the pitch data stored in the scale specification data memory 12 and the octave specification data memory 9 described above is added, and the added output value is stored in the address memory 1.
The data is circulated and stored in the first line memory of No.3. This pitch clock frequency signal is created based on the aforementioned octave reference clock frequency signal, which is the frequency of the carry signal output from the adder 28. That is, this tone pitch clock frequency signal is used to pause control the number of addition clocks of the octave reference clock frequency signal to be added to the adder 33, so that the adjacent tone frequency ratio is in a relationship of 12√2. This allows the period time of one cycle (64 steps) of a musical tone to be varied in accordance with the specified octave and pitch data based on scale data. The step number detection matrix circuit 32 generates a clock signal every 1 step, every 2 steps, every 4 steps, every 8 steps, every 16 steps, and every 32 steps in one cycle of a musical tone. Each output state of each clock signal is determined by the matrix circuit 34 for creating the number of paused clocks, so that the scale frequency ratio is 12√2.
The signals are supplied to 12 output lines corresponding to scales that are combined as described below so that the relationship is as follows. Therefore, one of the 12 output lines of the pause clock number generation matrix circuit 34 is selected by the scale clock selection circuit 30 in accordance with the specified scale of the scale data 29, and its output signal is sent to the clock number control circuit 35. will be applied to
Under the control of the Fa memory 11, the clock number control circuit 35 controls to stop the carry signal, that is, the octave reference oclock signal output from the adder 28, and controls the aforementioned pitch clock frequency signal applied to the adder 33. It's something you get. The address step count value detection circuit 31 detects the start address "0", "30", "0", or "32" of the step count value during one cycle (64 steps) of musical tone in each line memory of the address memory 13.
It detects "0" to "31" and the final address "63" and supplies the output of the middle 4 bits of the 6-bit parallel output to the comparator circuit 36. Thus, the start address "0" count value detection signal is given to the periodic circuit 37, and at this time, the tone control circuit 2
-1/64 instruction signal and +1/64 instruction signal outputted from 4, the -1/64 instruction signal is supplied to the step number detection matrix circuit 32, and the +1/64 instruction signal is supplied to the scale clock selection circuit 30. be done. In other words, the -1/64 instruction signal and +1/64 instruction signal produce a so-called vibrato that gives a subtle frequency change by adding -1 or +1 to the normal frequency during one musical tone cycle (64 steps). It is intended to be obtained. Further, the "0" or "30" count value detection signal, the "30" count value detection signal, and the "0" to "31" count value detection signals output from the address step count value detection circuit 31 are sent to the waveform control circuit 3.
8, the "63" count value detection signal is given to an addition/subtraction control circuit 39, which will be described later. Further, this "63" count value detection signal is sent to the various control circuits 8 as a control signal to the Fb memory 14 in order to take the cycle of one musical tone cycle with respect to the periodic clock instruction signal outputted from the musical tone control circuit 24. It is also given to The envelope memory 15 outputs the output of the adder 40 to which the attack clock signal φ _A or the release clock signal φ _R of a specified cycle time from the musical tone control circuit 24 is supplied as an addition signal via the addition/subtraction control circuit 39 to the top line. It is stored circularly in memory, in this case, "0" to "15"
A count storage state of (0000 to 1111) is obtained, and the count storage state is passed from the final line memory to a volume envelope value detection circuit 41 and is supplied to an addition value determination circuit 42, which will be described later. The volume envelope according to this embodiment is changed from "0" to "0" by the attack clock signal _φA as shown in FIG.
It consists of an attack state in which the count is sequentially added up to "15" and a release state in which the count is sequentially subtracted from "15" to "0" by the release clock signal φ _R. This counting state corresponds to each line of the envelope memory 15. Can be stored in each memory. That is, the detection signal of the maximum count value "15" in the attack state is detected by the volume envelope value detection circuit 41 and outputted to the adjustment control circuit 39.
When applied, a subtraction command is given to the adder 40, and a "1" signal is stored in the Fe memory 18, thereby setting the release state.
Therefore, in the release state, the maximum count value "15" is subtracted from the maximum count value "15" until the count value "0" is detected by the volume envelope value detection circuit 41 by the release clock signal φ _R. Further, the Fc memory 16 is connected to the address step value detection circuit in order to synchronize the timing of addition or subtraction of the volume envelope attack clock signal φ _A and release clock signal φ _R in the adder 40 with one cycle of musical tone. It is controlled by the "63" count value detection signal of No. 31. The Fd memory 17 stores a "1" signal corresponding to the active line memory of the volume envelope memory 15, and in particular receives a delay instruction signal and a rising clock signal φs from the musical tone control circuit 24, as will be described in detail later. It is controlled by The output of the last line memory of the volume envelope memory 15 is also supplied to the comparison circuit 36. That is, in this comparison circuit 36, four bits in the address memory 13 and four bits in the envelope memory 15 are used.
A comparison is made with the bit output, and a match detection signal and a first and second half match pre-match detection signal are output, respectively, and applied to the waveform control circuit 38, which outputs a "30" detection signal and a "0" detection signal. , match detection signal,
The first and second half match pre-match detection signals are outputted and supplied to the addition control circuit 43, respectively. Addition control circuit 43
A fixed command signal for designating a musical sound waveform, a rectangular wave finger command signal, and a triangular wave command signal are also supplied from the musical tone control circuit 24. That is, the musical sound waveform according to this embodiment is as shown in FIG. 3, as a basic musical sound waveform.
There are three types of waveforms: a sawtooth waveform, a rectangular waveform, and a triangular waveform. Among these waveforms, the type of floating wave or fixed wave can be specified for the sawtooth waveform and the rectangular waveform. This floating wave is a waveform in which the address step value at the rising edge of the waveform is not constant, so-called amplitude pulse width is expanded or shortened, and the fixed wave is a so-called amplitude waveform in which the address step value at the falling edge of the waveform is constant (30 steps in this case). This refers to a waveform in which the pulse width is constant and the end portion is cut based on the volume control value of the volume envelope memory 15. Note that in the case of a triangular waveform, it is fixed. Therefore, the addition control circuit 43 outputs a fixed command signal, a floating command signal when there is no fixed command signal, a rectangular wave command signal, a triangular wave command signal, and a sawtooth wave command signal when both the rectangular wave command signal and the triangular wave command signal are absent. The waveform control circuit 3
A matrix circuit is formed to obtain combinations of the various detection signals from 8 and the above-mentioned various detection signals, and from its output, the E command signal and 1 command signal are sent to the addition value determining circuit 42, and the (-) command signal is output. The signal is supplied to an adder 44 which is a waveform counting circuit. The waveform control circuit 38 and the addition control circuit 43 are supplied with a command signal for the seventh octave designated in the octave designation data memory 9 from the addition control circuit 27. The addition value determining circuit 42 adds the volume envelope value of the volume envelope memory 15 in synchronization with the command signal from the addition control circuit 43 based on the musical waveform and the pitch clock frequency signal output from the clock number control circuit 35. 44. Therefore, adder 44
If we take a simple look at the musical sound waveform that is controlled for one line memory output from the
→ c → b → a As the volume gradually increases, the musical waveform also changes relatively greatly, and in the release state, a
As the volume gradually decreases from →b→c→d, the musical sound waveform also changes relatively small. Of course, such changes in musical sound waveforms are performed for each line memory. Then, the output of the adder 44 is circulated again as an addition value to the adder 44 in synchronization with the pitch clock frequency signal via the output control circuit 45, and the output of the output control circuit 45 is
The high-pitched musical tone is emitted from a speaker 48 via a conversion circuit 46 and an amplifier 47. Next, the embodiment described in FIG. 1 will be described in detail using the specific circuit configuration shown in FIG. Incidentally, FIG. 4 shows the connection state shown in FIG. 5. In FIG. 4A, the reference clock signal B with a period of 1 μs as shown in FIG. 6a outputted from the pulse generator 2 is a binary counter consisting of 3 bits.
1-1, and sequentially from each bit stage, as shown in Figure 6 b, c, d, the Ka signal of 2 μs period, 4 μs
It is generated by using the Kb signal with a cycle of s and the Kc signal with a cycle of 8 μs as a clock signal. These Ka, Kb, Kc signals and the ,, signals via the inverters 1-2, 1-3, 1-4 are applied to the matrix circuit 1-5 of the AND array, and are applied to the matrix circuit 1-5. From 1-5, Kd as shown in Figure 6 e, Kb signal as shown in f, K as shown in g to j.
0', K1', K2', and K3' signals are taken out. 4-bit hexadecimal scale counter with binary counting 5-
1 counts this c signal and outputs it as scale data as shown in Table 1 corresponding to B, C, C ⁺ . . . A, A ⁺ of the 12-tone scale as shown in Figure 7b, and
The outputs of weight bits 1, 2, and 8 are supplied to an AND gate 5-2.

【table】

[Table] The falling signal of the output signal as shown in FIG. 7c output from the AND gate 5-2 is
1 and clears the octave counter 5-3.
is given as a counting step signal. The octave counter 5-3 is a 3-bit hexadecimal binary counter, and the output of each bit stage is given to the AND gate 5-4, and the 8th one output from the AND gate 5-4 is
The signal in figure c is "1" in the octave counter 5-3.
Therefore, each bit output of the octave counter 5-4 outputs octave data as shown in Table 2 corresponding to seven octaves as shown in FIG. 8B.

[Table] The output signal of the AND gate 5-4 is supplied to the AND gate 5-5 together with the output signal of the AND gate 5-2.
Scale shown in octave counter 5-1, 5-3
Obtain an output signal corresponding to the final count value "84".
The output signal from the AND gate 5-5 is the input signal of the 84-bit shift register 4-1 of the input detection circuit 4 in FIG. 4B (see FIG. 9c).
Then, this input signal is used as the read pulse signal Kc in Fig. 9a and the write pulse signal c in Fig. 9b.
By performing a shift operation in synchronization with
Timing signals t1, . . . , t8 for sequentially scanning and selecting each of the performance operation keys as shown in FIG.
Generate 4. That is, the external performance operation key group 3 in FIG. 4B has 84 performance operation keys, in this case 84 pitch designation keys corresponding to 7 octaves of B0, C1, . . . , A7, A7 ⁺ keys. The selection of each key can be extracted from a matrix circuit 4-2 constituting an AND gate that is sequentially scanned by the timing signals t1, . . . , t84 of the shift register 4-1. Table 3 shows the data relationship between the timing signals t1, . . . , t84, the scale counter 5-1 of the performance operation keys, and the octave counter 5-3.

【table】

[Table] Each gate output of this matrix circuit 4-2 is shifted via an OR gate output line 4-3 in synchronization with a read pulse signal Kc and a write pulse signal c, and is transferred to an 84-bit shift register 4-3.
4 and one input terminal of AND game 4-5. A signal obtained by inverting the signal from the output terminal of the shift register 4-4 by an inverter 4-6 is applied to the other input terminal of the AND gate 4-5. A one-shot new key presence signal (width of 8 μs) is generated for each performance operation key pressed. Therefore, as can be seen from Table 4, the one-shot signal for this operation timing, which is configured to be particularly suitable for chordal performances by multiple simultaneous or time-dispersed operations of the performance operation keys, is the first shot signal for one operation. It can only be obtained through operating cycles.

[Table] The rising signal of the output of the OR gate 4-3 of the input detection circuit 4 in FIG. 4B is sent to the S-R flip-flop 7-2 via the keyless control circuit 7-1 in FIG. 4A for 8 μs. It is supplied to the reset input terminal and also to the 3-bit binary counter 7-3 as a clear signal. This counter 7-
3 counts the number of output signals from the AND gate 5-4, and the output of the third bit is S.
-R is coupled to the set input terminal of flip-flop 7-2. In other words, the state in which the counter 7-3 is not given a clear signal is approximately (12 x 7 x 4) x 8 = 2688
The output signal can only be obtained when the duration lasts for μs.
In other words, a so-called no-key state in which the performance operation key is not operated within 2688 μs is detected. Therefore, the side output key presence signal of the S-R flip-flop 7-2 is output, and the OR gate 7-4 is output together with the operation signal from the sustain instruction switch 6.
is supplied to Furthermore, the output of the OR gate 7-4 is an AND gate to which the Kd signal from the AND gate 1-5 is coupled via the OR gate 7-5, the AND gate 1-6 of the various control signal generation circuit 1, and the inverter 1-7. 1-8 and to the input of OR gate 8-1 in FIG. 4C. Also, the new key presence signal output from AND gate 4-5 in FIG. 4B is output from AND gate 1-9 in FIG. 4A.
to AND gate 1 via inverter 1-1
-6, AND gate 1-8, OR gate 7-5,
8-1 input. That is, ORGATE 7
-5 is a case where the S-R flip-flop 7-2 is in the set state (no key) and the sustain instruction switch 6 is in the non-instruction state, and when the new key is activated by the first new performance operation key after that state. The signal inhibits the output signal for a period of 8 μs, and otherwise the output signal is controlled to exist. In FIG. 4A, 1-11 is an 8-bit shift register, and 1-12 is a 4-bit shift register, which are synchronized with the read pulse signal B with a period of 1 μs and the write pulse signal inverted by the inverter 1-13. Shift operation is performed. The input end of the shift register 1-11 is connected to an OR gate 1-14, and the output end is connected to the input ends of the AND gates 1-6 and 1-9. or gate 1
The output of the AND gate 1-6, the OR gate output 1-15 (to be described later), and the AND gate 1-8 are coupled to the input of -14. That is, AND gate 1-8 outputs the Kd signal in the keyless state and inputs it to the shift register 1-11, and in the keyed state, it is output through AND gate 1-6 and OR gate 1-14. Circular shift is now possible. The output of the AND gate 1-9 is taken out as a K0 signal and coupled to the input of the shift register 1-12.
The outputs of each bit stage are K1, K2, K3, K4, respectively.
The signal is applied to a matrix circuit 1-16 forming an AND gate. This matrix circuit 1-1
Further, in the inverter 6, a duet command signal, a quartet command signal, and these double command signals, which will be described later, are sent to the inverter 1-6.
17 and 1-18 are also applied, so that the matrix circuit 1-16 receives the K1 signal when there is no duet command signal and quartet command signal, and when only the duet command signal exists. K for
If only the quartet command signal exists, the K4 signal is outputted and the OR gate output 1-
15. In other words, the shift registers 1-11, 1-12 and the surrounding games
The group 3 controls the designation of each line memory of the memories 9 to 18 described above for the key operated by the performance operation key 3. Now, when there is no command for duo or quartet, the sustain instruction switch 6 is not operated, and the flip-flop 7-2 is in the set state (keyless state), the AND gate 1-8 is opened as shown in FIG. 10S.
is ready to open, therefore, AND gate 1
The Kd signal of FIG.
1 and are sequentially shifted up as shown in FIG. 10 f to m. In this state, when the first new key presence signal is output from the AND gate 4-5 as shown in FIG. The final bit stage P8 of shift register 1-11 such as
The output signal from is output as a K0 signal (1 μs width). The output signal K0 from the AND gate 1-9 is given to the input of the shift register 1-12, and after a 1 μs delay, the K1 signal from the first stage bit is input to the shift register 1-11 via the OR gates 1-15 and 1-14. is applied, but in Fig. 10f
As can be seen from, at this input point, line memory K
It is input one bit later than the input timing signal of the original Kd signal (broken line in Figure 10) that specifies 0, and in synchronization with the input timing signal of K1 that specifies the next line memory K1. , this input timing signal of K1 is the shift register 1-
11, AND gate 1-6, OR gate 1-14
It will be stored cyclically through . Then, in the second new key present signal shown in FIG.
1 is inputted with a timing signal to specify the line memory K2. Therefore, up to eight line memories K0 to K7 can be specified sequentially, and this specification state is shown in FIG.
This is an example of operating two consecutive performance keys. In addition, in the case of a duet designation, two line memories K0 and K1, K2 and K3, K4 and K5, and K6 are assigned to one performance operation key as shown in Figure 12.
and K7 can now be specified respectively to take out the K0 signal and K1 signal, and in addition, in the case of quartet specification, the first
As shown in FIG. 3, it is controlled so that the K0, K1, K2, and K3 signals can be specified in four line memories, K0 to K3 and K4 to K7, for one performance key. The K0 signal output from the AND gate 1-9 in FIG. 4A is applied to the a1, a2, a3, a4 switch terminals of the double octave instruction key group 22 in FIG. 4C from the first stage bit of the shift register 1-12. The output K1 signals are b1, b2, b3, b
4 switch terminals, k2 signal is c1, c2, c
3, C4 switch terminal, K3 signal is d1, d
2, d3, and d4 switch terminals, respectively.
Then, the operation signals of switches a1, b1, c1, d1 are input to the OR gate 20-1.
2, b2, c2, d2 operation signals are OR gate 2
0-2 input, switch a3, b3, c3, d
The operation signal No. 3 is supplied to the input of the OR gate 20-3, and the operation signal of the switches a4, b4, c4, d4 is supplied to the input of the OR gate 20-4, respectively. From 4 onwards, octave "1" (regular octave), octave "+2", octave "+3", octave "+"
4" command signal will be taken out. Moreover, the operation signals of switches b1, b2, b3, b4 are input to the OR gate 22-5, and the operation signals of switches c1, c2, c
The operation signals of switches d1, d2, d3, and d4 are supplied to the input of the OR gate 22-7, and the output of the OR gate 22-5 is supplied to the input of the AND gate 22-8.
One input terminal of , and each output of OR gates 22-6 and 22-7 are both supplied to OR gate 22-9.
Also, the output of the OR gate 22-9 is connected to the inverter 22.
-10 to the other input terminal of the AND gate 22-8. That is, the duo command signal is taken out from the output of the OR gate 22-9, and the quartet command signal is taken out from the output of the AND gate 22-8. In addition, normally switch a1,
Either a2, a3, or a4 is set. Said or gate 20-1, 20-2, 20-
The output signal from 3, 20-4 is the OR gate 20-
Also, the OR gate 20-2 is supplied to the OR gate 20-12, the OR gate 20-4 is supplied to the OR gate 20-13, and the output of the OR gate 20-13 is supplied to the OR gate via AND gates 20-14 and 20-15. 20-12 and 20-13. Furthermore, the OR gate 20-3 is the AND gate 19-1 to 19-4 of the corrected scale data creation circuit 19.
It is also supplied to one input terminal of AND gates 19-6 to 19-9 via inverter 19-5. The scale data from the scale counter 5-1 in FIG. 4A passes through the matrix circuit 19-10 having the AND function of the corrected scale data creation circuit 19 in FIG. 4C, and is directly sent to the AND gates 19-6 to 19-9 to the other input terminal of each of the inverters 19-11, 19
-12, 19-13, and 19-14 to the matrix circuit 19-10. Further, the output of the 1st and 2nd weight bits of the scale counter 5-1 is supplied to the other input terminal of the AND gate 19-2 by inverting the output of the exclusive OR gate 19-15 by an inverter 19-16. An inverter 19- is connected to the other input terminal of the AND gate 19-1.
Eleven output signals are provided. AND gate output line 19-1 of matrix circuit 19-10
7, 19-18, 19-19 are OR-combined and given to the AND gate 20-25 as a +4 octave command signal, and also to the inverter 19-20.
The signal inverted by the AND gate 20-14
and one input terminal of AND gate 19-21. The other input terminal of this AND gate 19-21 is coupled with an output signal obtained by inverting the signal led to the gate output line 19-22 of the matrix circuit 19-10 by an inverter 19-23. The output of 21 is coupled to the other input terminal of the AND gate 19-4. Furthermore, the AND gate output line 19 of the matrix circuit 19-10 is connected to the other input terminal of the AND gate 19-3.
The OR-combined outputs of -22, 19-24, and 19-25 are combined. That is, this corrected scale data creation circuit 19 receives + from the OR gate 20-3.
This device performs +7 (3 times) correction on the regular scale data given from the scale counter 5-1 when a triple command signal is given, and is constructed to obtain code conversion as shown in Table 5.

[Table] After all, and gate 19-6, 19-7, 19
-8, 19-9 has regular scale data, and gates 19-1, 19-2, 19-3, 19-
From 4 onwards, the corrected scale data is selectively transmitted to OR gates 19-26, 19-27, 19-28, 19- in response to the "+3" command signal from OR gate 20-3.
29. Therefore, the octave data from the octave counter 5-3 in FIG. 4A is transmitted to the OR gates 20-12, 20-
Octave designation data is output from the output of the adder 21 along with the output of the adder 13, and the AND gates 8-2, 8-3, and 8-4,
The data is supplied as 3-bit parallel data to the octave designation data memory 9 via OR gates 8-5, 8-6, 8-7 and AND gates 8-8, 8-9, 8-10. On the other hand, the 4th C
OR gate 19-26, 19-27 in the diagram,
The scale designation data outputted from 19-28 and 19-29 is synchronized with the output signal of OR gate 20-11 and sent to AND gates 8-11 and 8- in FIG. 4D.
12, 8-13, 8-14, or gate 8-1
5, 8-16, 8-17, 8-18 and AND gates 8-19, 8-20, 8-21, 8-22 to the scale designation data memory 12 as 4-bit parallel data. The output of the OR gate 20-3 in FIG. 4C is also applied to the OR gate 8-1. Also, this or gate 20
The output signal obtained by inverting the output of -3 by the inverter 20-16 is sent to the AND gate 8-23 in Fig. 4D.
~8-35, AND gate 8- in Figure 4F
It is supplied to one input terminal of 36 to 8-49 as a gate inhibit signal. Furthermore, the output signal of the OR gate 7-5 in FIG. 4A is output from the AND gates 8-50 to 8-55 in FIG. 4D and the AND gate 8 in FIG. 4F.
-56 to 8-59, or gate 8-60 to 8-6
1 is supplied as a gate control signal to one input terminal of the AND gates 8-62 to 8-68 and the AND gate 8-48. That is, the or gate 7-5
As shown in FIG. 14, when the sustain finger instruction switch 6 is in the non-indication state and the flip-flop 7-2
In the set state (keyless state), the 14th
When the new key presence signal is output from the AND gate 4-5 as shown in Figure a, during that time (8 μs time), the AND gates 8-50 to 8-55 and the fourth
AND gates 8-56 to 8-59 in diagram F,
Gate outputs of AND gates 8-62 to 8-68 and AND gate 8-48 are prohibited, and each memory 1
This controls the state in which all stored contents of 0, 11, 13, 15, 16, and 17 are cleared. On the other hand, the OR gate 8-1 receives the new key presence signal as shown in FIG. 14e, and the OR gate 2 in FIG.
Since the K0 signal is output from 0-1, this 1 μs
The period is ANDGATE 8-8 to 8-10 and 8-1
9 to 8-22 have gates open, octave designation data memory 9, scale designation data memory 12
New octave designation data and scale designation data are respectively written and stored in the K0 line memory. The output of the OR gate 20-11 is inverted by the inverter 20-16, and the signal is applied as a gate prohibition signal to the AND gates 8-23 to 8-25 and 8-32 to 8-35, so that it is not stored previously. The contents of the K00 line memory are cleared. However, if the sustain instruction switch 6 in FIG. 4A is operated, the contents of each memory once stored will not be cleared, but the flip-flop 7-2 in FIG. 4A will be in the set state. If nine or more performance operation keys are operated in the key presence state, the ninth performance operation is stored in the first line memory K0 of the octave specification data memory 9 and the scale specification data memory 12. Octave specification data corresponding to the key,
The scale specification data will be stored, and the previously stored contents will be cleared. The following sequentially K1, K2...
Data corresponding to new performance operation keys will be stored in the line memory. Here, the creation of the pitch clock frequency signal will be explained with reference to FIGS. 4D and 4F. This pitch clock frequency signal is created based on the octave designation data and scale designation data set in the octave designation data memory 9 and scale designation data memory 12, respectively. The 3-bit octave designation data set in the octave designation data memory 9 is decoded by the decoder 27-1 every time it is output from the last line memory, and is sequentially octave 1, 2, 3, 4, 5, 6, etc.
An output signal is generated on one of the 7 outputs. The first to fifth octaves are directly applied, and the sixth and seventh octaves are applied to a 1-bit shift up circuit 27-3 via an OR gate 27-2. This 1-bit shift up circuit 27-3 operates only when there is an octave change command, which will be described later, and normally no shift operation is performed. Therefore, each output of the decoder 27-1 is applied to the adder 28-1 via the 1-bit shift up circuit 27-3, and an addition operation is performed with the stored contents of the corresponding line memory of the octave bit memory 10. That is, the storage contents of the last line memory of the octave bit memory 10 are added with the addition numbers shown in Table 6 corresponding to the decoder 27-1 every cycle (8 μs), and the addition result is stored at the beginning. AND gates 8-26 to 8-3 in line memory
0 and 8-48 to 8-52.

[Table] Therefore, the generation of the carry signal from the adder 28-1 differs depending on the designated octave, and as shown in Table 6, from the 1st octave to the 5th octave, every 32 cycles and 16 cycles. every 8
Obtained every cycle, every 4 cycles, every 2 cycles. If this is further expressed in terms of period Tfb and frequency, it will be as shown in Table 6. Also, as can be seen from Table 6, the output of the decoder 27-1 corresponding to the 6th octave and the 7th octave is the OR gate 27.
-2 and is applied to 8 without passing through the adder 28-1.
It is directly supplied to the OR gate 28-2 together with the carry signal from the adder 28-1 as a carry signal every μs (one cycle). That is, the output signal from this OR gate 28-1 becomes the octave reference clock frequency signal. On the other hand, each bit output of the scale designation data outputted from the last line memory of the scale designation data memory 12 is supplied to the scale decoder 29, which outputs one of the 12 scales corresponding to each scale. Each output line is supplied to a scale clock selection circuit 30. The octave reference clock frequency signals for the carry signals shown in Table 6 corresponding to each of the seven octaves are sent from the OR gate 28-2 to the AND gate 35-1 through the AND gates 35-1 and 35-2 and the inverter 35-3. It is applied to one input terminal of 4. Then, each time the octave reference clock frequency signal is output from the AND gate 35-1, the adder 3 in FIG.
+1 will be added to 3. The address memory 13 in FIG. 4F has eight line memories that can store 64 step count values in 6 bits, and each line memory stores the number of steps in one cycle of the musical sound waveform shown in FIG. That's what happens. The 6-bit output of the last line memory of the address memory 13 is directly connected to the matrix circuit 31-7 of the address step count value detection circuit 31 having an AND gate function and the step number detection circuit 31-7 through the inverters 31-1 to 31-6. The signal is supplied to the matrix circuit 32. This matrix circuit 32 has six output lines a1 to a.
6 and is incorporated as an AND gate function,
The output line is applied to the pause clock number generation matrix circuit 34, where the scale decoder 29
The AND gate 28-2 for each scale specified by
The number of pauses in the octave reference clock frequency signal output from the octave reference clock frequency signal is determined. That is,
The AND gate 35-1 is controlled so as to obtain a frequency signal corresponding to a musical scale between 64 step count memories in one line memory of the address memory 13. Here, the matrix circuit 32,
The basic operating principle of the pause clock number generation matrix circuit 34 will be explained. The step number detection matrix circuit 32 in FIG. 4F has 32 shots on the output line a1, 16 shots on the a2, and a
8 shots on 3, 4 shots on a4, 2 shots on a5, a6
The circuit is constructed so that one clock signal is outputted, and FIG. 15 shows the principle explanation thereof. That is, in Figure 15, now,
Considering only one line memory of the address memory 13, and assuming that the counting pulses shown in FIG. 15a are counted and the counting memory state as shown in FIG. 15b is obtained from the 6-bit output of the address memory, the step number detection matrix circuit As many clock signals as shown in FIG. 15c are obtained on the 32 output lines a1 to a6 during one cycle (64 steps). By combining the output lines a1 to a6 of the step number detection matrix circuit 32, the rest clock number matrix circuit 34 determines the number of rest clocks for each scale. That is, now the reference frequency from pulse generator 2 is _B
(=1000KHz), the period will be as follows. T _B = 1/ _B = 1/1000KHz = 1μs Therefore, a = _B /8μs = 1000KHz/8μs = 125KHz Ta = 1/a = 1/125KHz = 8μs However, a: Frequency of one shift cycle of address memory 13 Ta : The period is a. Also, if the number of steps in one cycle of the musical sound waveform is n (=64 steps), then Tx = Tb (n + a) = Tb (64 + a) a = Tx / Tb - 64 where Tb is the period of the octave reference clock frequency (OR gate 28 -2 output) Tx: Period of each scale a: Correction value (number of rest clocks) ∴Fx=1/Tx Fx: Scale frequency. Also, the frequency ratio between each scale in each octave is in the relationship of 12√2, so it is only necessary to find the correction value for one octave, and in the end, the number of rest clocks for each scale (correction value α) is the 16th Based on this, the number of rest clocks corresponding to the musical scale is set to the 12 output lines X1 to X12 of the matrix circuit 34 for creating the number of rest clocks in FIG. 4D, as shown in FIG. 15d. This can be selected and set using a matrix circuit having an OR gate function. In FIG. 16, Fx1 to Fx6 are scale frequencies according to this circuit configuration, and the actual frequency is the actual scale frequency. That is,
Corresponding to the scale decoder 29, a selection circuit 30 selects one of the output lines X1 to X12 to supply the number of pause clocks to the OR output line 30-1. The number of pause clocks corresponding to this scale is AND gate 35-5, inverter 35
-6 to the AND gate 35-1 as a gate output prohibition signal. Further, the output signal of the last line memory of the Fa memory 11 for controlling the number of tone pitch clocks mentioned above is applied to the AND gate 35-5 via an inverter 35-7. The output signal of this Fa memory 11 is the AND gate 35
-4 is also directly supplied. The outputs of these AND gates 35-2 and 35-4 are the OR gates 35-
8, via AND gate 8-31, 8-53
The signal is supplied to the first line memory of the Fa memory 11 as a control signal. AND gates 37-1, 37 in Figure 4F
The "0" count value detection signal output from the last line memory of the address memory 13 is applied to one input terminal of -2, and the +1/64 instruction signal which gives the vibrato in FIG. 4E is applied to the other input terminal. , −1/64
An instruction signal is provided. That is, AND gate 37
-1 is connected to the OR output line 30-1 of the scale clock selection circuit 30 in FIG. 4D, and the output of the AND gate 37-2 is connected to the OR gate 37-3.
The step number detection matrix circuit 3
The AND gate 37-1 unconditionally supplies one clock more than the normal scale frequency to the "0" detection state of the AND gate step, and slightly lowers the frequency. On the other hand, the AND gate 37-2 unconditionally removes one more clock than the normal scale frequency and slightly slows down the frequency, so as to apply vibrato. The pitch clock frequency signal output from the AND gate 35-1 created in this way is +1 at the adder 33 with respect to the line memory of the address memory 13.
The outputs S1 to S4 are added to the AND gate 8.
-36 to 8-41 and 8-56 to 8-61 and are stored in the first line memory in a circular manner. Of course, such control is performed for each corresponding line memory of each memory. The "30" step count value detection signal in the matrix circuit 31-7 of the address step count value detection circuit 31 in FIG.
The "0" and "32" step count value detection signals are input to one input terminal of the AND gate 8-1, and the "0" and "32" step count value detection signals are input to one input terminal of the AND gate 38-2. The signal inverted by -3 is supplied to the first input terminal of AND gate 38-4. A coincidence detection signal from the comparator circuit 36 is input to the second input terminal of the AND gate 38-4.
Comparator circuit 3 is connected to one input terminal of 8-5 and 38-6.
The front/half match pre-match detection signal from 6 is supplied. And these AND gates 38-1, 38-2,
The other input terminals of the OR gates 38-4 and 38-5 are supplied with the output signal of the inverter 31-6 and the seventh octave output signal from the decoder 27-1 in FIG. 4D. The output of OR gate 38-7 is inverted by inverter 38-8, and the output of OR gate 38-7 is coupled to the other input terminal of AND gate 38-6. That is, AND gates 38-1, 38-2, 38-4, 38-5, 38
-6 outputs respectively "30" detection signal and "0"
A detection signal, a detection signal for the first and second halves of the coincidence detection signal, and a pre-coincidence detection signal are outputted and supplied to the addition control circuit 43. K counted by the binary counter 1-1 in FIG. 4A and obtained from the matrix circuit 1-5.
The 0', K1', K2', and K3' signals are supplied to the tone control instruction key group 25 in FIG. 4E. The musical tone control instruction key 25 includes switches M and N for envelope time instruction, switch 0 for period time instruction, rise difference instruction switch P, waveform instruction switch Q, vibrato instruction switch R, octave engine instruction switch S, phase difference instruction switch. T, and a duet slight difference indicating switch U, which allows each of the four musical tones to be specified independently, and the four musical tones are represented by , ,. Attack time instruction switches M1 and M2 for musical tones
are connected to the OR gates 25-1 and 25-2, respectively, release time instruction switches N1 and N2 are connected to the OR gates 25-3 and 25-4, respectively, and the following O1 and O
2, P, Q1, Q2, Q3, R, S
, T1, T2, UI1, U2 are OR gates 25-5, 25-6, 25-7, 25 in order, respectively.
-8,25-9,25-10,25-11,25
-12, 25-13, 25-14, 25-15,
25-16, and similarly switches M1, M2, N2, O1, O for musical tones.
2, P, Q1, Q2, Q3, R, S
, T1, T2, U1, and U2 are connected in order to the OR gates 25-1 to 25-16, respectively. Furthermore, for musical tones, switch M1, M
2, N1, ...U1, U2 for musical tones, switch M1, M2, ...U1, U
2 is or gate 25-1 to 25-16 in order respectively.
is supplied to the input of And or gate 2
5-1 and 25-2 are supplied to the decoder 24-1 to obtain decoder outputs as shown in Table 7. OR gates 25-3 and 25-4 are applied to the decoder 24-2, and outputs of the decoder as shown in Table 8 are provided, and OR gates 25-5 and 25-6 are applied to the decoder 24-3. The decoder output as shown in Table 9 is obtained.

【table】

【table】

[Table] The "0" output of the decoder 24-1 is taken out as an attack "0" signal, the "1" output, and the "2" output.
The output and "3" output are respectively AND gates 24-4,
Decoder 2 is connected to one input terminal of 24-5 and 24-6.
4-2 "0" output, "1" output, "2" output,
"3" output is AND gate 24-7, 24- respectively
Also, at one input end of 8, 24-9, 24-10,
"0" output, "1" output of decoder 24-3,
"2" output and "3" output are each AND gate 24-
11, 24-12, 24-13, and 24-14. 26 is the time measurement circuit 18
Consists of a binary counter consisting of 8μ bits.
It counts s periodic signals. In the figure, the numbers shown at each stage of the binary counter 26 indicate approximate cycle times associated with binary counting (partially different from actual measured values). 24-15-2
4-21 is a delayed flip-flop (DFF).
), a "1" signal is always given to the D terminal, and a 2ms and 2ms signal of a binary counter is given to the C terminal, respectively.
16ms, 32ms, 64ms, 128ms, 256
ms, the output of the bit stage corresponding to the measurement time of 512 ms is supplied, and these DFFs are further reset by the output from the first stage corresponding to the measurement time of 16 ms. Therefore, DFF24-1
An 8 μs one-shot clock signal is now output from the Q side outputs of 5 to 24-21.
DFF24-57 is taken out as a rising clock signal φs. The Q side output of the DFF24-16 is connected to the other input terminal of the AND gate 24-4.
DFF24-17 goes to AND gate 24-5,
DFF24-18 is AND gate 24-6 and 24
-7, DFF24-19 is AND gate 24-
To 8, DFF24-20 is AND gate 24-
9, DFF24-21 is AND gate 24-10
is supplied to the other input terminal of each of the two input terminals. Furthermore, the other input terminals of the AND gates 24-11 to 24-14 are connected to binary counters 256ms, 512ms, 1s,
The outputs of the bit stages corresponding to the measurement time of 2 seconds are applied respectively. Therefore, AND gate 24-4
The outputs of 24-6 to 24-6 are supplied to the OR gate 24-22 to obtain the attack clock signal _φA corresponding to the output of the decoder 24-1 specified by the attack time instruction switch M, and the AND gate 24-2
The outputs of 4-7 to 24-10 are OR gate 24-2
The release clock signal φ _R corresponding to the output of the decoder 24-2, which is supplied to the decoder 24-2 and specified by the release time instruction switch N, is applied to the AND gate 24-1.
The outputs of the clocks 1 to 24-14 are supplied to an OR gate 24-24 to obtain a periodic clock signal _.phi.T corresponding to the output of the decoder 24-3 specified by the periodic time designation switch 0. The periods of these attack clock signal φ _A , release clock φ _R , and periodic clock signal φ _T correspond to the decoder output.
The results are as shown in Table 8 and Table 9. The OR gate 25-7 has a delay time t at the rise of the volume envelope of the adjacent line memory.
The signal is output in accordance with the instruction for the presence or absence of a rise difference when operating the rise difference presence/absence instruction switch P, which indicates whether or not to provide the rise difference.When there is no instruction, an output signal is generated from the inverters 24-25. or gate 25
-8, 25-9, 25-10 are output in response to the command of the waveform instruction switch Q, and the outputs of the OR gates 25-9, 25-10 and their outputs are further connected to the inverters 24-26, 24-27. The inverted output is supplied to a waveform command matrix circuit 24-28 which obtains three types of waveform commands, from which sawtooth wave, triangular wave, and square wave command signals are generated as shown in Table 10. That is, the waveform command signal is output with the relationship shown in Table 10.

[Table] The outputs of the OR gates 25-11 and 25-12 are respectively supplied to one input terminal of AND gates 24-29 to 24-30, and the output from the Fb memory 14 in FIG. 4F is supplied to the other input terminal. is supplied.
The output of AND gates 24-29 is OR gate 24
-31 as the vibrato command signal of the -1/64 command signal and the AND gate 37 in FIG.
−2 is given. From the AND gates 24-30, the 4th D signal is output as an octave change signal.
It is supplied as a +1 command signal to the 1-bit shift up circuit 27-3 in the figure. Further, the outputs of the OR gates 25-13 and 25-14 are selected and set as phase difference command signals, and the outputs of the OR gates 25-13 and 25-14 are selectively set as phase difference command signals.
The output of 13 is the OR gate 8-6 in Figure 4F.
1, 8-69 to one input end, OR gate 25-
The output of 14 is also the OR gate 8-60, 8-7
0 is supplied to one input terminal of the OR gate 8-
The outputs of 61 and 8-69 are coupled to the inputs of AND gate 8-71, and the outputs of OR gates 8-60 and 8-70 are coupled to the input of AND gate 8-72. And gate 8-71 is address memory 13
32-bit weight of and gate 8-72
also performs 16-bit weight memory write control. Also, and gate 8-40, 8-
The outputs of 41 are OR gates 8-70 and 8-69, respectively.
are supplied to each input of the . That is, the phase difference instruction switch T in FIG. 4E gives a phase control command as shown in Table 11.

[Table] According to this phase difference command, it is possible to change the phase with respect to the regular musical waveform cycle for each line memory, and it becomes possible to cause a waveform change and change the tone color. Furthermore, the overlapping slight difference indication switch U is operated to give a slight difference change to the regular frequency for each line memory, and the -1/64 indication signal and +1/64 indication signal cannot be applied at the same time. do not have. The output of this OR gate 25-15 is sent as a +1/64 instruction signal to the AND gate 37-1 in FIG. 4F, and also to the OR gate 25-16.
The output is -1/64 instruction signal as OR gate 24-
31 to the AND gate 37-2. That is, in the case of a duet or a quartet, a plurality of line memories are used for one key operation of the performance operation key group 8, two for a duet, four for a quartet, and each line memory K0 ,K4,K1,
For K5, K2, K6, K3, K7, correspondence settings for musical tones,,,,, etc., slight difference changes by commanding the slight difference in ensemble, octave combinations by the ensemble octave instruction key, and the presence/absence of rise difference instruction key P
It is possible to specify the rise delay t by . When the rise difference presence/absence indicating switch P is not operated, the no rise difference signal from the inverter 24-25 is output from the AND gate 8-7 in FIG. 4F.
3, and this AND gate 8-7
3 is the new key presence signal from AND gate 4-5 in Figure 4B, and OR gate 2 in Figure 4C.
Output signals from 0-11 are also applied. Therefore, when one key of the performance operation key group 3 is operated, the AND gate 8-73 switches the OR gate 8-74 in the timing order of the operation key.
A "1" signal is sequentially written into each line memory of the Fd memory 17 via the FD memory 17. Of course, duet,
When there is a quartet command, multiple line memories are specified in response to one key operation. The "1" signal written in the Fd memory 17 is stored in circulation via the OR gate 39-1, the AND gate 8-48, and the OR gate 8-74, and is used to instruct the envelope memory 15 to which line memory is in operation. Become. On the other hand, when the rise difference instruction switch P is operated, a delay instruction signal is applied to the AND gate 8-75 in FIG.
Output of 3 is prohibited. This and gate 8-7
5 further includes AND gate 4-5 in Figure 4B.
The new key presence signal from , and the K0 signal output from AND gate 1-9 in FIG. 4A are also applied. The rise difference presence/absence indicating switch P is used to obtain the rise time difference t in the case of a duet or quartet command. Therefore, when the performance operation key is operated, this AND gate 8-75 outputs only 1 μs corresponding to the first line memory K0 by the K0 signal, and "1" is sent to the Fd memory 17 via the OR gate 8-74. Signals are written and stored circularly as well. And this Fd memory 1
The "1" signal written in 7 is applied to a delay circuit 39-2 which delays by 1 μs from the last line memory, and its output is given to an AND gate 39-3. Fd memory 17 in AND gate 39-3
A signal obtained by inverting the output signal from the last line memory of 39-4 by an inverter 39-4 and the 3-bit output of the octave designation data memory 9 in FIG. A rising clock signal φs from the DFF 24-15 in the figure is applied. This AND gate 39-3 outputs the rising clock signal φs when there is a "1" signal in the K0 line memory of the Fd memory 17 and there is no "1" signal in the next line memory K1, and the OR gate 39-6 outputs the rising clock signal φs. It is supplied as a +1 addition signal to the adder 40 via the signal. In this case, the line memory K1 of the envelope memory 15 does not open the gate of the AND gate 39-7, which will be described later, because the "1" signal has not yet been written in the corresponding line memory K1 of the Fd memory 17. The line memory K1 of the memory 15 does not store the counted value of the envelope value. That is, in this state, the line memory K1 of the envelope memory 15 is used to store the count value of the output of the adder 40 that counts the rising clock signal .phi.s in order to determine the rising time difference t. Then, when the adder 40 continuously adds the rising clock signal every cycle (8 μs) and outputs a carry signal, the carry signal is sent to the OR gate 39-1.
The signal is written to the line memory K1 as a "1" signal via the line memory K1. That is, the time until the carry signal is output from the adder 40 is the rise delay time t of the envelope of the line memory K1 next to the line memory K0, and in this case, the delay time t is approximately 30 ms. be. In this way, in the case of a duet command, when the rise difference presence instruction switch P indicates the presence of a rise difference, the "1" signal is not immediately written into each line memory of the Fd memory 17, but is delayed. It is written after time t. In particular, in the case of a quartet command, data is sequentially written to the line memory K1 of the Fd memory 17 after t time, to K2 after 2t time, and to K3 after 3t time with a delay of t time. . In this way, the active line memory for the envelope memory 15 is written into the Fd memory 17, and the output of this Fd memory 17 is further applied to the AND gates 39-7, 39-8 and the addition determining circuit 42, which will be described later. It is also supplied to the AND gate 42-1. On the other hand, OR gate 24-2 in Figure 4E
The attack clock signal φ _A and the release clock signal φ _R output from the 4th F
It is supplied to one input terminal of AND gates 8-76 and 8-77 in the figure. The AND gate 8-76 is further provided with a signal obtained by inverting the attack "0" signal in FIG.
OR gate 3 to which the output of Fe memory 18 is supplied
An output signal obtained by inverting the output signal of 9-9 by an inverter 8-79 is also supplied, and therefore, this AND gate 8-76 determines the attack time when the envelope is in the attack state shown in FIG. 2 and the attack is not "0". When necessary, the attack clock signal φ
It outputs _A. Also, and gate 8-
The output signal of the OR gate 39-9 is supplied to the other input terminal of 77, and therefore,
This AND gate 8-77 comes to output a release clock signal φ _R in the released state shown in FIG. The outputs of these AND gates 8-76 and 8-77 are passed through OR gate 8-80.
It is input to the OR gate 39-10 together with the output of the last line memory of the Fc memory 16. And the output of this OR gate 39-10 is AND gate 3
It is applied to one input terminal of 9-11 and 39-12. The other input terminal of the AND gate 39-11 is applied with a count detection signal of "63", which is the final address step value of the musical tone waveform detected by the address step count value detection circuit 31, and the AND gate 39-1
2, this “63” count value detection signal is sent to the inverter 3.
An inverted signal is applied at 9-13. The output of the AND gate 39-12 is the AND gate 8-47,
The signal is fed back to the Fc memory 16 via 8-67. That is, the attack clock signal φ _A and the release clock signal φ _R are synchronized with the final address step value of the musical waveform and are outputted only to the line memory designated to be stored in the Fd memory 17 via the AND gate 39-7. . The Fe memory 18 stores the attack state or release state of the envelope shown in FIG. 2, and "0" is written and stored in the attack state and "1" is in the release state. Initially, the envelope is not in the attack state. "0" is written. The output of the Fe memory 18 is sent to the AND gates 39-8 and 39-15 via the OR gate 39-9 and the inverter 39-14.
Therefore, in the attack state, the attack clock signal φ _A output from the AND gate 39-7 is supplied to the adder 40 as a +1 addition signal via the AND gate 39-15 and the OR gate 39-6. This adder 40 has a maximum of "15"
It can be obtained up to the count value (binary number "1111"),
The bit addition output is AND gate 8-43~8
-46 and 8-63 to 8-66 and are stored in the envelope memory 15 in a circular manner. The 4-bit output of the envelope memory 15 is sent to the addition value determination circuit 42 via the envelope value detection circuit 41.
and to the corresponding inputs of adder 40 and applied to comparative circuit 36. Further, the 4-bit output of the envelope memory 15 is coupled to inverters 41-1 to 41-4 of the envelope value detection circuit 41, and the envelope value detection circuit 41 detects the maximum count value "15" and the count value "0". It becomes like this. Therefore, when the envelope value reaches the maximum count value "15" in the attack state in which the attack clock signal φ _A is added, the detection signal is passed through the OR gate 39-9, AND gate 8-49, and AND gate 8-68 to Fe. At the same time as writing the “1” signal in the release state to the memory 18, the inverter 39
The output of -4 is in the "0" state, and the AND gate 3
The attack clock signal _φA output from 9-15 is prohibited. By writing "1" into the Fe memory 18, the (1) command signal is supplied to the adder 40, and at the same time, the release clock signal _φR is output from the AND gate 8-77.
This release clock signal _φB is further applied to OR gates 8-80, 39-10 and AND gate 39-1.
1, is supplied to the adder 40 via AND gates 39-7, 39-16, and OR gate 39-6, and the envelope of FIG. 2 is placed in a released state where it is subtracted from the maximum count value "15". This AND gate 39-16 enters an output prohibited state due to the output of the inverter 39-17 due to the "0" counting state in the released state. The attack "0" command signal shown in FIG. 4E is also applied to the AND gate 39-8. Since the attack "0" command signal does not require an attack state, the adder 40 is directly designated to the maximum count value "15" by the output of the AND gate 39-8, and immediately placed in the release state. Here, the tone waveform will be explained using FIG. 3 again. The comparison circuit 36 compares the 4-bit output value of the envelope memory 15 with the address memory 1.
The first half 0 to 31 and the second half 32 to 6 of the match detection signal and address step number 64 are compared with the outputs of the 4 bits in 3, that is, the 2, 4, 8, and 16 wait bits.
The first and second half pre-match detection signals are output before the output of the match detection signal No. 3. That is, as can be seen from the comparison table in Table 12, each time the output envelope value of the envelope memory 15 changes, the match detection state and The front/half matching pre-detection state changes, and the waveform state in FIG. 3 also changes from d to a direction in the attack state and from a to d direction in the release state, including the volume value.

【table】

[Table] Therefore, the waveform instruction switch Q in Fig. 4E
The fixed command signal, triangular wave command signal, and rectangular wave command signal of the musical waveform specified by the waveform change switch U are respectively applied to AND gates 43-1 to 43-3 in the addition control circuit 43 in FIG. 4F. is supplied to one input terminal of This and gate 43
An output signal obtained by inverting the command signal of the seventh octave of the decoder 27-1 in FIG. 4D by an inverter 43-4 is applied to the other input terminals of -1 to 43-3. The outputs of AND gates 43-1 to 43-3 and their outputs are connected to inverters 43-5 to 43-
It is supplied to the waveform determination matrix circuit 43-8 together with the inverted output at step 7. Therefore, the five types of waveforms shown in FIG. 3 are obtained by specifying the combination selection of the waveform determining matrix circuit 43-8. That is, the waveform determination matrix circuit 43-
8 is based on Table 13.

[Table] As can be seen from Table 13, for example, if a sawtooth floating waveform is specified, the address memory 13
When the address step count stored value of the line memory is in the first half of "0" to "31" and the first and second half match detection signals of the comparison circuit 36 are outputted, a +1 signal is output for each step, and if they match, a -E command signal is output. It is sufficient to immediately subtract the counted value. By selectively ORing the five output lines of this matrix circuit 43-8, an "E" signal is sent to line 43-9, and an "E" signal is sent to line 43-9.
"1" signal on -10, "-" on line 43-11
Make sure to take out the command signal. However, this “E” refers to the AND gate 38 of the waveform control circuit 38.
This shows the envelope values of the envelope memory 15 when outputting -1, 38-2, and 38-4. The "E" signal is applied to the AND gates 42-2 to 42-9 of the addition value determining circuit 42, and the "1"
The signal is supplied to an AND gate 42-10, and (1) the command signal is supplied to an adder 44, which is an output waveform counting circuit in FIG. 4G, and a 4-bit binary up-down counter 45-1. AND GATE 42-2
42-6 is a pitch clock outputted from the AND gate 35-1 in FIG. 4D via the AND gate 42-1 which indicates the active line memory of the envelope memory 15 from the Fd memory 17. The frequency signals are combined. Further, the 4-bit parallel output of the envelope memory 15 is coupled to each of the AND gates 42-2 to 42-5. The outputs of the AND gates 42-2 to 42-5 are B1, B2, and B2 of the adder 44 in FIG. 4G.
It is supplied to the input terminals of B3 and B4, respectively. Furthermore, the fourth
Since the command signal of the seventh octave output from the decoder 27-1 in Figure D prohibits the output of the AND gates 43-1, 43-2, and 43-3 of the addition control circuit 43, Only a floating waveform of a sawtooth waveform can be obtained. Here, the setting of the known time will be explained. Fourth
The output of the Fd memory 14 in Figure F is supplied to one input terminal of exclusive OR gates 8-81, 8-82, and the other input terminal of exclusive OR gate 8-82 is supplied as shown in Figure 4E. A periodic clock signal φ _T is supplied. The output of the exclusive OR gate 8-82 is sent to the exclusive OR gate 8 through an AND gate 8-83 to which the final address "63" count value detection signal from the address step count value detection circuit 31 is applied. -81, and the output of the exclusive OR gate 8-81 is coupled to the input side of the Fb memory 14 via AND gates 8-42 and 8-62. That is, vibrato command,
Octave engine command, periodic clock signal φ _T
The final address step value of the tone waveform in the address memory 13 is changed in synchronization with the count value detection signal of "63" for the rectangular wave. That is, the output of the AND gates 8-83 changes according to the "63" count value detection signal in response to the change of the periodic clock signal φ _T from the "0" signal state to the "1" signal state, and the output of the AND gate 8-83 changes to the line memory of the Fb memory 14. The writing state changes. The output of the adder 44 in FIG. 4G is fed back to the corresponding input terminal of the adder 44 via the latch circuit 45-1.
The outputs of the D/A conversion circuit 46 are 1, 2, 4, 8,
16, 32, 64, 128, and 256 bits are applied to the weight input terminal. The adder 44 is counted up and down depending on the presence or absence of the "-" command signal in FIG. 4F. In addition, the above (1) command signal and adder 4
The carry signal from 4 is given to exclusive OR gate 45-2, and further to inverter 45-2.
3 to the input of AND gate 45-4. This AND gate 45-4 receives the tone pitch clock frequency signal output from the AND gate 35-1 in FIG. It is outputted in synchronization with , and applied to the latch circuit 45-1. Then, the analog output signal of the D/A conversion circuit 46 is passed through an amplifier 47 and is outputted to a speaker 48 as a high-pitched musical tone. Next, the operation of the musical tone generator in the electronic musical instrument based on the above embodiment will be explained. Assume that the sustain instruction switch 6 in FIG. 4A is not operated and is in a non-instruction state. Note that this circuit is cleared to the initial state when the power is turned on. In this non-instruction state, multiple keys of the performance operation keys 3 in FIG. 4B are operated simultaneously (even if they are operated simultaneously, individual key inputs are electronically detected sequentially using timing signals with different phases), or arpeggio performance, etc. Suppose that it is manipulated as a chord performance by time-dispersive manipulation. For example, G1,A
Assuming that the four performance operation keys corresponding to 1, C2, and D2 are used to play a chord, each key corresponds to an 84-bit shift register 4-1, as can be seen from Table 3.
Timing signals output from t ₉ , t ₁₁ , t ₁₄ , t ₁₆
The signals are sequentially taken out to the OR gate output line 4-3 in synchronization with . First, G1 to OR gate output 4-3
Assuming that the timing signal _t9 corresponding to the key is output, the timing _t9 is the shift register 4-
As shown in Table 4, this AND gate 4-5 outputs a one-shot signal of 8 μs width as a new key presence signal as shown in FIG. 10c. It is supplied to the AND gates 1-9 of the various control signal generation circuit 1 in FIG. 4B. On the other hand, shift register 1-
11 is the first output from AND gates 1-5.
As shown in Figure 0e, the Kd signal is connected to the AND gate 1-
8, is input via OR gates 1-14, and this Kd signal is shifted and output from its output _P8 . Therefore, as can be seen from the explanation shown in FIG. 11, from the AND gate _1-9 , the Kd signal shown in FIG. K0 of 1 μs width like n
It is first output as a signal. That is, an output signal synchronized with the Kd signal output from the AND gate 1-9 is sent to the octave designation data memory 9,
In the scale specification data memory 12 and Fig. 4F
The reference first line memory K0 of the Fd memory 17 is designated as a timing input. Here, the switch _a1 of the ensemble octave designation key 22 in FIG. 4C is in the on state and the other switches are in the off state. Assume that there is no so-called duet designation or octave combination designation, and that the octave is in a normal octave state. Therefore, the output signal from the AND gate 1-9 is transmitted to the OR gate 20-1 and the OR gate 20-1 of the correction data octave creation circuit 20 in FIG. 4C.
1 to the OR gate 8-1, the octave designation data input gates 8-2 to 8-4 of the octave designation data memory 9 in FIG. 4D, and the scale designation data input gate 8- of the scale designation data memory 12.
11 to 8-14. Further, the output signal from the OR gate 8-1 in FIG. 4C is transmitted to the input control gates 8-8 to 8-10 and 8-19 to the octave and scale designation data memories 9 and 12 in FIG. 4D. 8-22. Therefore, G ₁ when the output signal synchronized with the Kd signal output from the AND gate 1-9 in FIG. 4A is generated.
The respective data "100" and "0001" of the octave counter 5-3 and the scale counter 5-1 in FIG. 4A, which correspond to the key, are used as pitch information in the adder 21 and corrected scale data creation circuit in FIG. 4C, respectively. 19 will be supplied. In this case, since there is no duet octave specification and no correction is performed in the correction octave creation circuit 20 and the correction scale creation circuit 19,
The octave "100" from the octave counter 5-3 is directly passed through the adder 21 to the 4th D.
AND gates 8-2 to 8-4, OR gates 8-5 to 8-7, and gates 8-9 to 8- in the figure
10 to the first line memory K0 of the octave designation data memory 9, and is input to the scale counter 5.
The scale data "0001" from -1 is as it is and the AND gate 19-6 of the corrected scale data creation circuit 19.
19-9, AND gates 8-11 to 8-1 in FIG. 4D via OR gates 19-26 to 19-29
8-14, OR gates 8-15 to 8-18, and AND gates 8-19 to 8-22. Also, the AND gate 1-9 in FIG. 4A
As a result, the K1 signal of the shift register 1-12 is transmitted to the shift register 1-11 through the OR gate output 1-15 and the OR gate 1-14 as shown in FIG.
is input. In this case, the new key presence signal disables the AND gates 1-6 via the inverter 1-10, so the output P of the shift register 1-11
There is no feedback of the Kd signal from 8, so the 1st
As shown in FIG. 0, a timing signal synchronized with the next designation of the second line memory K1, which is delayed by 1 μs from the designation timing of the first line memory K0, is input and cyclically held. Further, the timing signal at t9 outputted from the OR gate 4-3 by the operation of the G1 key of the performance operation key 3 in FIG. 4B is delayed by 8 μs through the delay circuit 7-1 in FIG. 4A and then output to the key. Absence detection counter 7-3
Clear the S-R flip-flop 7-
Reset 2. Therefore, a key presence signal is output from the side output of this flip-flop 7-2.
Through the OR gate 7-4, the octave bit memory 10, Fa memory 11, and the fourth bit memory in FIG.
Address memory 13 and Fb memory 1 in diagram F
4, envelope memory 15, Fc memory 16,
AND gate 8-5 for input control of Fe memory 18
0~8-59, 8-62~8-68, 8-71~
8-72 and the AND gate 8-48 for circulation control of the Fd memory 17 in FIG.
Memories 10, 11, 13, 15, 16, 17 respectively
is considered to be in a circulatory state. Next, a new key presence signal corresponding to the A1 key of the performance operation keys 3 is output to the AND gate 4- as shown in FIG.
5, the AND gate 1-9 in FIG. 4A outputs 1μ for designating the second line memory K1, which is cyclically held in the shift register 1-11.
A timing signal with a width of s is output as a K0 signal, and in synchronization with this, the octave data "100" and the scale data "0101" of the octave counter 5-3 and the scale counter 5-1 in FIG. 4A are input to the A1 key. The corresponding pitch information is similarly written to the second line memory _K1 of the octave designation memory 9 and scale designation data memory 12, respectively. Thereafter, by the same operation, octave specification data memory 9 and scale specification data memory 1 corresponding to the C2 key and D2 key are
Octave data “010” and scale data “1000” are stored in line memory K2 of line memory K2.
Octave data ``010'' and scale data ``1100'' are sequentially written to 3 as pitch information. On the other hand, the input timing signals of the line memories K0 to K3 are input to the AND gate 1 in FIG. 4A.
This input timing signal is also supplied to the input control AND gate 8-73 of the Fd memory 17 in FIG. 4F each time it is generated in response to the output signal from the Fd memory 17. Also, the musical tone control designation key 25 in FIG. 4E is the attack time instruction switch M1, M1, M1, M
1. Release time indication switch N1, N
1, N1, N1, waveform instruction switch Q2,
Assume that only Q3, Q2, and Q3 are designated to be in the on state. That is, line memory K0 is K
The line memory K1 corresponds to the musical tone by the K1' signal, and is controlled by the attack clock signal φ _A (16ms), the release clock signal φs _R (0.1 s), and a floating sawtooth shape. Then, the attack clock signal φ _A (16ms)
It is controlled by a release clock signal φ _R (0.1/s) and a floating triangular waveform. The line memory K2 corresponds to musical tones by the K2 signal, and is controlled by the attack clock φs _A (16ms), release clock signal _φR (0.1s), and a floating sawtooth waveform.
Line memory K3 corresponds to musical tones by K3' signal, and attack clock signal _φA
(16ms), release clock signal φ _R (0.1s) and a floating triangular waveform. Note that musical tones,,, are stored in line memories K4, K5, respectively.
K6 and K7 are also sequentially associated with K0', K1', K2' and K4' signals. Therefore, since the AND gate 8-73 is also supplied with the output from the inverter 24-25 in FIG. 4E, the AND gate 4-73 in FIG.
1μ output from the OR gate 20-11 in FIG. 4C every time a new key presence signal is output from 5.
The input timing signal of s width is input to the Fd memory 17.
The signals are sequentially written into the line memories K0, K1, K2, and K3 as "1" signals. Therefore, the octave designation data "100" corresponding to the G1 key written first in the first line memory K0 of the octave designation data memory 9 in FIG. 4D is the first octave command every cycle (8 μs). "1" of decoder 27-1 as a signal
Generated from output. Therefore, as shown in Table 6, this octave command signal lasts for one cycle (8μ
s) will be given to the adder 28-1 as a +1 addition command, and from this adder 28-1
A carry signal is output every Tfb1 (256 μs). The octave reference clock frequency signal (frequency 3906.25Hz) which is a carry signal output from the adder 28-1 is based on the scale designation data "0001" written in the first line memory K0 of the scale designation data memory 12. shown in the figure
The pitch clock frequency signal Fx1 (48.828) Hz is now output from the AND gate 35-1, and +1 is added to the adder 33 in FIG. 4G. Therefore, the address memory 13 in FIG.
In the first line memory K0, the addition result added by the adder 33 based on this pitch clock frequency signal (Fx1) is stored as address steps of one cycle (64 steps) of a sequential musical waveform. Similarly, in the second line memory K1 of the octave designation data memory 9, the first octave command signal corresponding to the A1 key is transmitted to the third and fourth line memories K1.
In 2 and K3, the second octave command signals corresponding to the C2 and D2 keys are extracted every 8 μs from the corresponding outputs of the decoder 27-1, and the carry signals corresponding to the respective octave commands are obtained as shown in Table 6. is output from the adder 28-1 as an octave reference clock frequency signal. Furthermore, the octave reference clock frequency signals corresponding to the octave designation data of the line memories K1, K2, and K3 outputted from the adder 28-1 are sent to each line memory K of the scale designation data memory 12.
As can be seen from FIG. 16, the pitch clock frequency signal is applied to the A1 key from the AND gate 35-1 of the clock number control circuit 35 in FIG. Against Fx
1 (55.018) Hz, Fx2 for C2 key
(65.651) Hz, Fx2 (73.703) for D2 key
It will be obtained like Hz. The added values are sequentially stored in the adder 33 in FIG. 4G corresponding to each of the line memories K1, K2, and K3 of the address memory 13 based on the respective pitch clock frequency signals. The address step values of the musical sound waveforms stored in each line memory K0, K1, K2, K3 of the address memory 13 in this way are applied to the count value detection circuit 31, and are sent to the inverter 31-6 via the OR gate 38-7. From the output to the first half of the musical waveform (0 to 31
Step) The AND gate 38-5 to which the detection signal is supplied outputs the first half pre-match detection signal of the comparator circuit 36, and outputs the detection signal before the first half of the comparison circuit 36 to the matrix circuit 4 of the addition control circuit 43.
Apply to 3-8. On the other hand, the waveform instruction switch Q2 corresponding to the line memory K0 in FIG. 4E
is a floating musical waveform instruction state of a sawtooth wave, so the inverters 43-5 and 4 of the addition control circuit 43
3-6 and 43-7 are in the "1" output state. Therefore, a +1 signal is output from the output of the matrix circuit 43-8 when the AND gate 38-5 outputs, and a "1" signal is supplied from the OR gate output line 43-10 to the AND gate 42-6. When the coincidence detection signal is output from the AND gate 38-4, the -E signal is generated from the output of the matrix circuit 43-8, the "E" signal is sent to the OR gate output line 43-9, and the "E" signal is sent to the OR gate output line 43-11.
(1) A command signal will be output. E signal is AND gate 42-2 to 42-5, (1) command signal is 4th G
This is given to the adder 44 in the figure as a subtraction command. Therefore, as can be seen from the explanation of FIG. 3 and Table 12, address memory 13 and envelope memory 1
5 is added by +1 in the adder 44 in synchronization with the output of the AND gate 42-1 before the coincidence detection signal is output from the comparison circuit 36, and the addition result value at that point is subtracted by 1 according to the coincidence detection signal. As a result, a floating musical sound waveform of a sawtooth wave including a volume value can be extracted. Furthermore, since the musical waveform instruction switch Q3 corresponding to the line memory K1 is in the floating triangular waveform instruction state, a +1 signal is output from the matrix circuit 43-8 of the addition control circuit 43, and a "1" signal is output from the OR output line 43. -10 is supplied to the AND gate 42-6. When a match signal is output from the comparison circuit 36, no signal is output from the matrix circuit 43-8.
When the address memory 13 reaches 30 steps, a -1 command signal is output from the matrix circuit 43-8, a "1" signal is output from the OR output line 43-10, and a (1) signal is output from the OR output line 43-11.
A command signal is output. Therefore, as can be seen from the waveform state of the triangular wave in FIG. 3, until a match signal is output from the comparison circuit 36, a "1" signal is output from the AND gate 42-6, and +1 is added by the adder 444, and the match signal is output. Therefore, the counting state is maintained up to 30 steps. After that, and gate 42-
6 outputs a "1" signal, but since the (1) command signal is applied to the adder 44, it is subtracted. Furthermore, the waveform of the line memory K2 is changed by the tone waveform instruction switch Q2 in a floating sawtooth state in the same way as the line memory K0 mentioned above, and
As for the line memory K3, the waveform is changed in the floating triangular wave instruction state by the tone waveform instruction switch Q3 in the same way as the line memory K1 described above, and the volume value is also included. Memory 9 ~ like this
18 are controlled based on musical waveforms, envelopes, and pitches that are independently designated for each line. In this case, multiple performance operation keys G1, A
1, C2, and D2 are operated simultaneously to specify four line memories, and a high-pitched tone as a so-called chord is generated by synthesizing the high-pitched tones of the respective line memories. Even if you release the key by operating the performance operation key, the pitch tones for the specified line memory will continue according to the envelope from the attack state to the end of the release state, that is, the volume attenuation curve becomes zero. occurrence is maintained. However, if nine or more consecutive key operations are performed while the flip-flop 7-2 in FIG. The line memory is erased in the order in which it was input, and the contents corresponding to the 9th and later operated scale and octave specification data are stored, so the envelope will not attack new operation keys. We will start from the state. and,
After playing a chord by simultaneously or time-distributed operation of multiple performance operation keys, the performance operation keys are approximately 2688.
If μs is not operated, counter 7 in Figure 4A
An output signal is generated from -3 and flip-flop 7
-2 is set, the keyless detection state is set, but even in this keyless detection state, the generation of high-pitched tones does not stop immediately;
Until the volume attenuation line at which the envelope ends becomes zero, the generation of high-pitched sounds for the corresponding line memory is maintained and a smooth high-pitched sound is obtained. Therefore, if the release clock signal φ _R that determines the release state of the envelope is designated as a clock with a long period, the generation of the high pitch tone will also be sustained for a long time. And each line memory K0,
K4, K1, K5, K2, K6, K3, and K7 are associated with the K0', K1', K2', and K3' signals, respectively, and the attack clock φ _A , release clock signal φ _R , and waveform instructions are independent of each other. Each line memory can be set independently, such as period time indication switch 0, rise difference indication switch P, vibrato indication switch R, octave engine indication switch S, phase difference indication switch,
It can be controlled by the double octave indication switch U, and it is also possible to give changes of +2, +3, +4 to the regular octave by using the double octave indication key 22. You can create various kinds of musical tones. In this way, multiple waveform selection instruction switches are provided,
Since the reference waveforms selected by each switch are digitally synthesized, musical tones with various changes can be obtained. In this case, a maximum of 81 musical tones can be obtained. It should be noted that the memories 9 to 18 can be constructed using RAM (random access memory), and the number of line memories does not have to be eight, but can be arbitrarily provided.
Furthermore, the performance operation key 3, the sustain instruction switch 6, the duet octave instruction key 22, and the musical tone control instruction key 25 may be configured with touch switches or the like.
Further, the sustain switch 6, the double octave instruction key 22, and the musical tone control instruction key 25 can be configured as mechanically or electronically lockable keys. The above-mentioned musical sound waveform may also be a waveform other than a triangular, rectangular, or sawtooth waveform. Furthermore, in the embodiment described above, the number of line memories is eight, K0 to K7, K0 and K4, K1 and K5, K2 and K6, The line memories of K3 and K7 each contain attack, release, cycle, rise difference, waveform, vibrato, octave,
Four instruction switches were used for each command so that the commands for phase difference, double difference, and double octave would be the same, but of course these switch can independently give instructions for each line memory. Similarly, eight indicating switches may be used. or,
Four types of phase difference have been described: 0°, 90°, 180°, and 270°, but 45°, 135°, 225°, etc. may also be added, and the point is that they can be used as appropriate. . Furthermore, it goes without saying that the number of reference waveforms, their types, and the shape of the waveforms are not limited to the embodiments and can be changed as appropriate. In addition, the specific circuit configuration is not limited to the embodiment and can be changed without departing from the gist of the present invention. As described in detail above, the present invention generates reference waveforms such as triangular waves, rectangular waves, and tortoise waves through digital arithmetic processing in a plurality of time-division processing channels. Since different reference waveforms are obtained by performing various digital arithmetic operations and digitally synthesized to obtain a musical sound waveform for one performance operation key, a waveform memory that stores waveforms of a predetermined shape in advance is required. It has the advantage that musical sound waveforms can be obtained without the use of multiple reference waveforms, and musical tones with various tones can be obtained by variously changing the combination of multiple reference waveforms. Another advantage is that a musical tone generator can be realized with a simple circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of an electronic musical instrument according to the present invention, FIG. 2 is a diagram explaining the envelope according to FIG. 1, FIG. 3 is a diagram explaining the musical sound waveform according to FIG. B, C, D, E, F, G are specific circuit configuration diagrams in Figure 1, Figure 5 is a connection explanatory diagram in Figure 4, and Figure 6 is a diagram of various control signal generation circuits in Figure 4A. The reference time chart, Figure 7 is the 4th one.
Figure 8 is a time chart related to the scale counter in Figure A, Figure 8 is a time chart associated with the octave counter in Figure 4A, and Figure 9 is a time chart associated with the performance operation key input detection circuit in Figure 4B. 10 is a time chart related to key inputs related to the various control signal generation circuits in FIG. 4A, FIG. 11 is an explanatory diagram related to the line memory in the various control signal generation circuits in FIG. 4A, and FIG.
The figure shows 2 in the various control signal generation circuits in Figure 4A.
FIG. 13 is an explanatory diagram for a quartet; FIG. 14 is a time chart related to the input of the performance operation keys in FIG. 4A;
FIG. 15 is an explanatory diagram related to the control of the number of pause clocks in FIG. 4D, and FIG. 16 is a diagram explaining the pitch clock frequency related to FIG. 4D. 1... Various control signal generation circuits, 3... Performance operation key group, 4... Performance operation key input detection circuit, 5
... Scale, octave counter, 7 ... Keyless control circuit, 8 ... Various control circuits, 9 ... Octave specification data memory, 10 ... Octave bit memory, 11 ... Fa memory, 12 ... Scale specification data memory , 13...address memory, 14...
...Fb memory, 15...Envelope memory, 1
6...Fc memory, 17...Fd memory, 18...
Fe memory, 26... Time measurement circuit, 28... Adder, 29... Decoder, 30... Selection circuit, 3
1...Address step count value detection circuit, 32...
...step number detection matrix circuit, 33...adder, 34...pause clock number creation matrix circuit, 35...clock number control circuit, 39...adjustment control circuit, 40...adder, 41...envelope value detection circuit, 42... Addition value determining circuit, 44
... Adder, 45 ... Output control circuit, 46 ...
D/A conversion circuit, 47...Amplifier, 48...Speaker, M, N...Envelope time instruction switch, O...Period time instruction switch, P...Rise difference presence/absence instruction switch, Q...Waveform instruction switch,
R...Vibrato instruction switch, S...Octave change instruction switch, T...Phase difference instruction switch, U...Tet fine difference instruction switch, 25-1~
25-16...Or gate, a1~a4,b1~
b4, c1 to c4, d1 to d4...Double instruction switch, 20-1 to 20-4...OR gate.

Claims (1)

[Scope of Claims] 1. A keyboard having a plurality of performance operation keys, and a reference waveform information generating means having a plurality of time-sharing processing channels and generating reference waveform information through digital calculation processing in each time-sharing processing channel. According to the operation of the performance operation keys of the keyboard, one performance operation key is assigned to at least two of the time-sharing processing channels, and digital calculation processing of different modes is performed in the at least two of the assigned time-sharing processing channels. and a control means for generating different reference waveform information by digitally synthesizing the different reference waveform information generated from the reference waveform information generating means and outputting the synthesized musical sound waveform information for the operated performance operation key. A musical tone generating device characterized by comprising: digital synthesis means. 2. The musical tone generating device according to claim 1, wherein the control means includes a changing means for changing the number of the time-sharing processing channels to which the one performance operation key is assigned. 3. The reference waveform information generating means includes an address counting circuit that counts one cycle in multiple steps, and a waveform information generating circuit that digitally generates staircase waveform information based on the output of this address counting circuit, and 3. The musical tone generating device according to claim 1, wherein the counting circuit and the waveform information generating circuit perform time-sharing operations using the plurality of time-sharing processing channels.