JPS61187467A - Image sensor - Google Patents

Image sensor

Info

Publication number
JPS61187467A
JPS61187467A JP60026929A JP2692985A JPS61187467A JP S61187467 A JPS61187467 A JP S61187467A JP 60026929 A JP60026929 A JP 60026929A JP 2692985 A JP2692985 A JP 2692985A JP S61187467 A JPS61187467 A JP S61187467A
Authority
JP
Japan
Prior art keywords
output
circuit
bit digital
inputted
receiving element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60026929A
Other languages
Japanese (ja)
Inventor
Shigeru Matsukawa
茂 松川
Shingi Yokobori
横堀 進義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP60026929A priority Critical patent/JPS61187467A/en
Publication of JPS61187467A publication Critical patent/JPS61187467A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To use a defective line image sensor in the same way as a nondefective sensor by discriminating a defective photodetector depending on the difference from output levels of adjacent photodetectors and using an output of the adjacent photodetector in place of the output of the defective photodetector to apply interpolation. CONSTITUTION:A output of a photodetector array 1 is inputted sequentially to an A/D converting circuit 2 synchronously with a reference clock, converted into an N-bit digital signal and stored in a latch circuit 3 by using a latch clock signal 32. The N-bit digital output of the latch circuit 3 is inputted to one input terminal 72 of an absolute value subtraction circuit 7, and an N-bit digital output of the photodetector array before on reference clock time stored in the latch circuit 6 is inputted to an input terminal 71. The absolute value is compared with an N-bit digital setting value of a setting device by a comparator circuit 8 and when the absolute difference is larger than the setting value, the signal inputted to the input terminal 51 is selected in the two N-bit digital signals inputted to the selection circuit 5. The selected signal is inputted to a latch circuit 6, stored by using a latch clock signal 62 and an image sensor output is obtained.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はラインイメージセンサを構成する受光素子の欠
陥を補正するセンサ補間機能を備えたイメージセンサに
関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image sensor having a sensor interpolation function for correcting defects in light receiving elements constituting a line image sensor.

従来の技術 一般にラインイメージセンナを使用する場合、ラインセ
ンサを構成する各受光素子の感度のバラツキの為にシェ
ーディング、画素間出力のバラツキ、ピーク値の変動等
の現象が発生し、これに対してはいくつかの前処理の方
法が考案されている(例えば画像電子学会誌第13巻第
2号)。
Conventional technology Generally, when using a line image sensor, phenomena such as shading, variation in output between pixels, and fluctuation in peak value occur due to variations in sensitivity of each light receiving element that makes up the line sensor. Several pre-processing methods have been devised (for example, Journal of the Institute of Image Electronics Engineers, Vol. 13, No. 2).

しかしラインイメージセンサの受光素子に欠陥があシそ
の受光素子から信号が全く出力されない場合には前処理
では対処せず出荷検査工程に於いて不良品と見なして選
別を行なっているのが現状である。一方、ラインイメー
ジセ/すを構成する受光素子数は高分解能化等により増
大化しており、その為に受光素子の欠陥によるラインイ
メージセンナの不良率は高く歩留りが悪い状態にあシそ
の結果コスト高にもなっていた。
However, if there is a defect in the light-receiving element of a line image sensor and no signal is output from the light-receiving element, the current situation is that it is not dealt with in pre-processing and is treated as a defective product in the shipping inspection process and is sorted out. be. On the other hand, the number of light-receiving elements that make up a line image sensor is increasing due to higher resolution, etc., and as a result, the defective rate of line image sensors due to defects in the light-receiving elements is high, resulting in poor yields and resulting costs. It was also high.

発明が解決しようとする問題点 この様に従来の方法ではたとえ1つの受光素子に欠陥が
ある様な軽度の不良品でも不合格としていた。本発明は
かかる点に鑑みてなされたもので、軽度の欠陥を持つ不
良品を良品と同等に使用可能せしめる為のセンサ補間機
能を備えたイメージセンサを提供することを目的として
いる。
Problems to be Solved by the Invention As described above, in the conventional method, even a mildly defective product, such as one having a defect in one light-receiving element, was rejected. The present invention has been made in view of the above, and an object of the present invention is to provide an image sensor equipped with a sensor interpolation function that allows defective products with minor defects to be used in the same way as good products.

問題点を解決するだめの手段 本発明は上記問題点を解決する為、各受光素子の出力信
号を隣接する受光素子の出力信号と比較し、その出力レ
ベルの差よシ欠陥のある受光素子を判別し、その結果受
光素子に欠陥があれば出力信号を隣接する受光素子の出
力信号で補間するものである。
Means for Solving the Problems In order to solve the above problems, the present invention compares the output signal of each light-receiving element with the output signal of an adjacent light-receiving element, and detects a defective light-receiving element based on the difference in output level. As a result, if there is a defect in the light receiving element, the output signal is interpolated with the output signal of the adjacent light receiving element.

作  用 高分解能のラインイメージセンナでは受光素子間の距離
が短かく、またラインイメージセンサ上に像を形成する
光学系のMTF特性により隣接する受光素子間において
入力される光量が急激に変fヒすることはなく、もしも
出力が急激に変化する場合にはその受光素子には欠陥が
あると判断できる。また欠陥のある受光素子の出力は上
記理由により隣接する受光素子の出力によシ補間するこ
とができる。本発明は上記理由により欠陥のある受光素
子を隣接する受光素子の出力レベルの差よシ判別し、そ
の欠陥のある受光素子の出力釦式わって隣接する受光素
子の出力を用いて補間することによシ欠陥のあるライン
イメージセンサも良品と同様に使用することができるも
のである。
In a high-resolution line image sensor, the distance between the light-receiving elements is short, and due to the MTF characteristics of the optical system that forms an image on the line image sensor, the amount of light input between adjacent light-receiving elements changes rapidly. If the output changes rapidly, it can be determined that the light receiving element is defective. Further, the output of a defective light receiving element can be interpolated with the output of an adjacent light receiving element for the above reason. For the above reasons, the present invention identifies a defective light receiving element based on the difference in output level between adjacent light receiving elements, and performs interpolation using the output button type of the defective light receiving element using the output of the adjacent light receiving element. A line image sensor with a defect can also be used in the same way as a good product.

実施例 第1図は本発明のイメージセンサの一実施例を示すブロ
ック図である。第1図において、1は受光素子アレイで
あって各受光素子の信号を出力するだめのクロック信号
入力端子11を有する。2はA/D変換回路であって受
光素子アレイからのアナログ信号の入力端子21 、 
A / D変換開始信号入力端子22を有する。3はラ
ッチ回路であってA/D変換回路からのNビットデジタ
ル信号の入力端子31.ラッチクロック信号入力端子3
2を有する。4はイメージセンサ回路のタイミング信号
を発生するタイミング発生回路であって基準クロック信
号入力端子41を有する。5は選択回路であって2つの
Nビットデジタル信号の入力端子51,52、またそれ
らの2つのNビットデジタル信号のうちどちらかを選択
する選択信号入力端子63を有する。6は選択回路5か
らのNビットデジタル信号を記憶するラッチ回路であっ
てNビットデジタル信号入力端子61.ラッチクロック
信号入力端子e2を有する。7は絶対値出力形式の減算
回路であって2つのNビットデジタル信号入力端子71
.72を有する。8は比較回路であって2つのNビット
デジタル信号入力端子81゜82を有する。9は設定器
であって任意のNビットデジタル値を設定することがで
きる。
Embodiment FIG. 1 is a block diagram showing an embodiment of the image sensor of the present invention. In FIG. 1, reference numeral 1 denotes a light-receiving element array, which has a clock signal input terminal 11 for outputting a signal from each light-receiving element. 2 is an A/D conversion circuit, which has an input terminal 21 for analog signals from the light receiving element array;
It has an A/D conversion start signal input terminal 22. 3 is a latch circuit, and has an input terminal 31.3 for receiving an N-bit digital signal from an A/D conversion circuit. Latch clock signal input terminal 3
It has 2. A timing generation circuit 4 generates a timing signal for the image sensor circuit, and has a reference clock signal input terminal 41. Reference numeral 5 denotes a selection circuit having input terminals 51 and 52 for two N-bit digital signals, and a selection signal input terminal 63 for selecting one of the two N-bit digital signals. 6 is a latch circuit that stores the N-bit digital signal from the selection circuit 5, and has an N-bit digital signal input terminal 61. It has a latch clock signal input terminal e2. 7 is an absolute value output type subtraction circuit, which has two N-bit digital signal input terminals 71;
.. It has 72. 8 is a comparison circuit having two N-bit digital signal input terminals 81 and 82. Reference numeral 9 is a setting device which can set any N-bit digital value.

受光素子アレイの各受光素子の出力は基準クロ7りに同
期して遂次A/D変換回路2に入力され、Nビットのデ
ジタル信号に変換された後ラッチクロック信号32によ
りラッチ回路3に記憶される。
The output of each light-receiving element in the light-receiving element array is sequentially input to the A/D conversion circuit 2 in synchronization with the reference clock 7, and after being converted into an N-bit digital signal, it is stored in the latch circuit 3 by the latch clock signal 32. be done.

ラッチ回路3のNビットデジタル出力は絶対値減算回路
7の1つの入力端子72に入力され、一方ランチ回路6
に記憶されている1基準クロック時間前の受光素子アレ
イのNビットデジタル出力は入力端子71に入力される
。その絶対差は比較回路8の入力端子81に入力され、
入力端子82に入力されている設定器9のNビットのデ
ジタル設定値と比較され絶対差が設定値より大きい場合
には1を出力し、選択回路5に入力されている2つのN
ビットデジタル信号のうちラッチ回路6から入力端子6
1に入力されているNビットデジタル信号を選択する。
The N-bit digital output of the latch circuit 3 is input to one input terminal 72 of the absolute value subtraction circuit 7, while the launch circuit 6
The N-bit digital output of the light receiving element array stored one reference clock time ago is input to the input terminal 71. The absolute difference is input to the input terminal 81 of the comparator circuit 8,
It is compared with the N-bit digital setting value of the setting device 9 input to the input terminal 82, and if the absolute difference is larger than the setting value, it outputs 1, and the two N bits input to the selection circuit 5
Out of the bit digital signal, from the latch circuit 6 to the input terminal 6
Select the N-bit digital signal input to 1.

選択されたNビットデジタル信号はラッチ回路6に入力
され、ラッチクロック信号62で記憶されイメージセン
ナ出力となる。
The selected N-bit digital signal is input to the latch circuit 6, stored as a latch clock signal 62, and becomes the image sensor output.

この様にして受光素子の出力を隣接する受光素子と比較
して設定値以上のレベル差があれば隣接する受光素子の
出力で補間する機能を備えたイメージセンサを実現でき
る。
In this way, it is possible to realize an image sensor having a function of comparing the output of a light receiving element with an adjacent light receiving element and interpolating with the output of the adjacent light receiving element if there is a level difference greater than a set value.

発明の詳細 な説明してきた様に、本発明によれば簡単な回路構成の
補間回路を設けることにより欠陥のある受光素子を持つ
ラインイメージセンナも使用することができ実用的にき
わめて有用である。
As described in detail, according to the present invention, by providing an interpolation circuit with a simple circuit configuration, it is possible to use even a line image sensor having a defective light-receiving element, which is extremely useful in practice.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の一実施例におけるイメージセンサのブロッ
ク図である。 1・・・・・・受光素子アレイ、2・・・・・・A/D
変換回路、3・・・・・・ラッチ回路、4・・・・・・
タイミング発生回路、6・・・・・・選択回路、6・・
・・・・ラッチ回路、7・・・・・・絶対値域算回路、
8・・・・・・比較回路、9・・・・・・設定器。
The figure is a block diagram of an image sensor in one embodiment of the present invention. 1... Light receiving element array, 2... A/D
Conversion circuit, 3...Latch circuit, 4...
Timing generation circuit, 6... Selection circuit, 6...
... Latch circuit, 7 ... Absolute value range calculation circuit,
8... Comparison circuit, 9... Setting device.

Claims (1)

【特許請求の範囲】[Claims] 受光素子アレイと、上記受光素子アレイから基準クロッ
クに同期して出力される信号を保持する手段と、各受光
素子の出力を隣接する受光素子の出力と比較し、出力レ
ベルの差が予め設定された値より大きいかどうかを判断
する手段と、上記判断する手段の結果により上記各受光
素子の出力信号を上記隣接する受光素子の出力信号で補
間する手段とを備えたことを特徴とするイメージセンサ
a light-receiving element array; a means for holding a signal output from the light-receiving element array in synchronization with a reference clock; the output of each light-receiving element is compared with the output of an adjacent light-receiving element, and a difference in output level is set in advance. and means for interpolating the output signal of each of the light-receiving elements with the output signal of the adjacent light-receiving element based on the result of the determination means. .
JP60026929A 1985-02-14 1985-02-14 Image sensor Pending JPS61187467A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60026929A JPS61187467A (en) 1985-02-14 1985-02-14 Image sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60026929A JPS61187467A (en) 1985-02-14 1985-02-14 Image sensor

Publications (1)

Publication Number Publication Date
JPS61187467A true JPS61187467A (en) 1986-08-21

Family

ID=12206852

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60026929A Pending JPS61187467A (en) 1985-02-14 1985-02-14 Image sensor

Country Status (1)

Country Link
JP (1) JPS61187467A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01240984A (en) * 1988-03-15 1989-09-26 Tetsu Kin Digital image processor
JPH04239886A (en) * 1991-01-24 1992-08-27 Matsushita Electric Ind Co Ltd Picture noise removing device
JP2007088616A (en) * 2005-09-20 2007-04-05 Seiko Epson Corp Image reader and original holder thereof
JP2007143131A (en) * 2005-10-26 2007-06-07 Nvidia Corp Method and device for image signal processing
US9756222B2 (en) 2013-06-26 2017-09-05 Nvidia Corporation Method and system for performing white balancing operations on captured images
US9798698B2 (en) 2012-08-13 2017-10-24 Nvidia Corporation System and method for multi-color dilu preconditioner
US9826208B2 (en) 2013-06-26 2017-11-21 Nvidia Corporation Method and system for generating weights for use in white balancing an image

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5394719A (en) * 1977-01-31 1978-08-19 Nec Corp Removing system for defective picture element of photoelectric conversion pickup unit
JPS59223062A (en) * 1983-06-01 1984-12-14 Canon Inc Picture processing device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5394719A (en) * 1977-01-31 1978-08-19 Nec Corp Removing system for defective picture element of photoelectric conversion pickup unit
JPS59223062A (en) * 1983-06-01 1984-12-14 Canon Inc Picture processing device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01240984A (en) * 1988-03-15 1989-09-26 Tetsu Kin Digital image processor
JPH04239886A (en) * 1991-01-24 1992-08-27 Matsushita Electric Ind Co Ltd Picture noise removing device
JP2007088616A (en) * 2005-09-20 2007-04-05 Seiko Epson Corp Image reader and original holder thereof
JP2007143131A (en) * 2005-10-26 2007-06-07 Nvidia Corp Method and device for image signal processing
US9798698B2 (en) 2012-08-13 2017-10-24 Nvidia Corporation System and method for multi-color dilu preconditioner
US9756222B2 (en) 2013-06-26 2017-09-05 Nvidia Corporation Method and system for performing white balancing operations on captured images
US9826208B2 (en) 2013-06-26 2017-11-21 Nvidia Corporation Method and system for generating weights for use in white balancing an image

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