JPS61187190A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve a function with a simple function by switching an address signal fed externally to access a memory cell section at random to send the signal to an address decoder of the said memory cell section. CONSTITUTION:A write signal P1, a read signal P2 and a random access write/ read signal P3 are inputted to discriminate the priority of each input and a control signal is fed to an address switching circuit 5, which changes over the output of a write address counter 2, the output of a read address counter 3 and the random access signal P3 by using a control signal from the control circuit 4 and one set of address signals among them is outputted. The output signal of the circuit 5 is inputted to a row decoder 6 and a column decoder 7 to select the row and the column of a memory cell section 1 to access the memory cell at the cross point. In case of the write, a write data input signal P5 is written in the selection memory cell through a data input/output circuit 8. In case of the read, the storage information of the selection memory cell is outputted through the input/output circuit 8 as a data output signal P6.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor memory in which data is written and read in an orderly manner, such as a buffer memory used for data transfer between computers.

(Prior Art) As a conventional semiconductor memory of this type, there is one called a first-in, first-out memory (FIFO). As shown in Figure 2, when the shift registers R, O-R, and n are connected in parallel and input data is written to registers R and 0, the data previously stored in registers El and OK is written to register 1 in advance. Control money registers RO-) to be transferred in parallel 1. The first stored data is read from registers R and n.

(Problems to be Solved by the Invention) In the conventional semiconductor memory described above, the register RO
The data written to the output cannot be read unless each register is sequentially transferred up to I%n, and the data read from the output cannot be read again because it will be a destructive read, and the degree of integration will not increase. There is a problem in that it is not possible to read or rewrite (modify data) the data in the middle of -Rn.

The object of the present invention is to solve these problems and provide a semiconductor memory IJ in which the function of reading or rewriting stored data can be realized with a simple structure.

(Means for Solving the Problems) The semiconductor memory of the present invention includes a memory cell section and outputs a value obtained by counting write signals for writing data in the memory cell section in address order as a total write address signal. write address counter.

a read address counter that outputs a value obtained by counting read signals for reading data in the memory cell section in address order as a read address signal; a write address signal from the write address counter and a read address from the read address column; and a switching circuit that switches an address signal applied from the outside for randomly accessing the memory cell section and sends it to the address decoder of the memory cell section.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of the main parts of a semiconductor memory according to the present invention. Reference numeral 1 denotes a memory cell section, which uses memory cells used in general semiconductor random access memories as storage elements. 2
and 3 are a write address counter and a read address counter, where the write address counter 2 inputs the write signal P1 applied to the write terminal and outputs the write address, and the read address counter 3 inputs the read signal P2t applied to the read terminal - human power. and output the read address. This write/read address counter 2゜3 receives a write signal P1 or a read signal P2 every time it is input.
Increments or decrements the write address or read address to be output. P3 is an external address input signal and is input to the address input terminal. 4 is a control circuit that manually determines the priority of each input including a write signal PI, a read signal P2, and a write/read signal P3t for random access, and sends a control signal to the address switching circuit 5. The address switching circuit 5 is the output of the write address counter 2, and the output of the read address counter 3.
The output of the address signal P3 and the switching (multiplex) of the address P3 for random access are performed by a control signal from the control circuit 4, and one set of address signals among them are all output. The output signal of the address switching circuit 5 is input to the row decoder 6 and the column decoder 7, and the output signal is input to the memory cell 510.
One row and one column are selected, and the memory cell at the intersection of the selected row and column is accessed. P5 is the write data input signal.
P6 is a read data output signal, and in the case of writing, the write-in data P5 is written into the selected memory cell through the entire data input/output circuit 8. In the case of reading, the stored information of the selected memory cell is outputted as read data P6 through the input/output circuit 8.

The data sequentially stored in the memory cell W151 by the write signal P1 can be sequentially read out at any time by the read signal P2, and since this is not a destructive read, there is a means for resetting the output of the read address counter 3 ( (not shown), re-reading is possible. By applying the random access address P3 and the random access write/read signal P4t-, it is possible to read and rewrite any part of the stored data.

In addition, a write/read address counter 2.3 is adopted to select addresses for writing and reading as a FIFO, and an address signal from the write/read address counter 2.3 and an address signal P3 for random access are used. Switching is performed by a simple switching circuit, and a FIFO function and arbitrary address access can be realized with a simple configuration.

(Effects of the Invention) As described above, according to the present invention, the write address signal generated from the write address counter by counting all the write signals for writing data in the order of addresses in the memory cell section, and the data in the memory cell section. By providing a read address signal generated from a read address counter by counting read signals for reading data in address order, and a switching circuit that switches address authenticity for random access and uses it as a memory cell address, first-in, first-out is achieved. A highly functional semiconductor memory with a simple configuration that can be used as a buffer memory for data transfer between co/peater, etc., as well as read and rewrite data from any location as needed. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a simple embodiment of the present invention, and FIG. 2 is a schematic diagram of a conventional semiconductor memory. RO~Kn...Shift register, 1...
・Memory cell e12...Write address counter, 3...Read address counter, 4...
...Control circuit, 5...Switching circuit, 6...
...Row decoder, 7...Column decoder,
8... Data input/output circuit, Pl... Write signal, P2... Read signal, P3...
...External address signal, P4...Write/read signal for random access, P5...Write data input signal, P6...Read data output signal. Kaya 1 system first out ￥2 extra

Claims (1)

[Claims] a memory cell section; a write address counter that outputs a value obtained by counting write signals for writing data in the memory cell section in address order as a write address signal; and a read signal for reading data in the memory cell section in address order. a read address counter that outputs a counted value as a read address signal, a write address signal from the write address counter, a read address signal from the read address counter, and an external input signal for randomly accessing the memory cell section. 1. A semiconductor memory comprising: a switching circuit for switching an address signal to be sent to an address decoder of the memory cell section.