JPS61185933A - Silicon wafer substrate - Google Patents

Silicon wafer substrate

Info

Publication number
JPS61185933A
JPS61185933A JP60025733A JP2573385A JPS61185933A JP S61185933 A JPS61185933 A JP S61185933A JP 60025733 A JP60025733 A JP 60025733A JP 2573385 A JP2573385 A JP 2573385A JP S61185933 A JPS61185933 A JP S61185933A
Authority
JP
Japan
Prior art keywords
silicon wafer
wafer substrate
reinforcing ribs
substrate
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60025733A
Other languages
Japanese (ja)
Other versions
JPH0626176B2 (en
Inventor
Shiyousuke Hagiwara
萩原　▲しょう▼介
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sord Computer Corp
Original Assignee
Sord Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sord Computer Corp filed Critical Sord Computer Corp
Priority to JP60025733A priority Critical patent/JPH0626176B2/en
Publication of JPS61185933A publication Critical patent/JPS61185933A/en
Publication of JPH0626176B2 publication Critical patent/JPH0626176B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate

Abstract

PURPOSE:To reduce the thermal capacity of silicon chip while preventing any warp or distortion from occuring by a method wherein a silicon wafer substrate is arranged with irregular grid type reinforcing ribs. CONSTITUTION:Within a silicon wafer substrate 1 arranged with grid type protective films 3 on the other side, reinforcing ribs 1a are formed by means of etching the substrate 1 utilizing anode electrolytic grinding process leaving the silicon wafer part arranged with the grid type protective films 3 only. Through these procedures, any warp or distortion of the silicon wafer substrate 1 may be reinforced by means of arranging the other side of silicon wafer substrate 1 with irregular grip type reinforcing ribs 1a etched utilizing the anode electrolytic grinding process.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、シリコン・ウェハー基板の改良に関し、特に
、超高速ＬＳＩシリコン・ウェハーにおけるシリコン・
チップの熱容量を少なくしたシリコン・ウェハー基板に
関する。Detailed Description of the Invention (Field of Industrial Application) The present invention relates to the improvement of silicon wafer substrates, and in particular to the improvement of silicon wafers in ultra-high-speed LSI silicon wafers.
This invention relates to a silicon wafer substrate with a reduced chip heat capacity.

（従来技術及び問題点） シリコン・ウェ′バーの厚みは通常３インチウェハ　−
　のｌ古、仝−１＋　Ａ　　ｆ’ｌ　　ｎ　　ｕ　　、
Ａ−ζ　１）　１）　ｕ＋ｓＰＬ　　ｎ　　　　ｇ　　
Ｉンチ又は８インチのウェハーのように直径が大になる
に伴なって、シリコン・ウェハーの反り、歪みなどが生
じ、これらを防ぐためシリコン・ウェハーの厚みを大に
していた。他方、ＬＳＩにおいては、１μｍルールで高
密度となり、待に超高速ＬＳＩの場合は単位面積当たり
の発熱量も大となり、シリコン・ウェハーの発熱効率の
低下を招いていた。(Prior art and problems) The thickness of silicon wafer is usually 3 inches -
1 old, 仝-1+ A f'l n u,
A-ζ 1) 1) u+sPL n g
As the diameter of the silicon wafer increases, such as inch or eight inch wafers, warping and distortion occur in the silicon wafer, and to prevent this, the thickness of the silicon wafer has been increased. On the other hand, in the case of LSIs, the 1 μm rule requires high density, and in the case of ultra-high-speed LSIs, the amount of heat generated per unit area also increases, leading to a decrease in the heat generation efficiency of silicon wafers.

（発明の目的） 本発明は、このような問題を解消するものであり、シリ
コン・ウェハーを超高速ＬＳＩとする際に、シリコン・
チップの発熱量を少なくするシリコン・ウェハー基板を
提供することを目的とする。(Objective of the Invention) The present invention solves these problems, and when making a silicon wafer into an ultra-high-speed LSI.
The purpose of the present invention is to provide a silicon wafer substrate that reduces the amount of heat generated by chips.

（発明の概要） 本発明の構成を概括すると、本発明は、シリコン・ウェ
ハー基板の一面にはエピタキシャル層を、該シリコン・
ウェハー基板の他面には格子状の保：ａ膜を配設して電
解研磨法によりエツチング処理することに上り門凸の格
子状から成る補強リブを具備するシリコン・ウェハー基
板であり、厚さ１μｍ〜１０μ…のシリコン・ウエノ）
−の強度を補強する特徴を有する。(Summary of the Invention) To summarize the structure of the present invention, the present invention provides an epitaxial layer on one surface of a silicon wafer substrate.
A silicon wafer substrate is provided with a lattice-shaped protective film on the other side, and is etched by electrolytic polishing to provide reinforcing ribs in the form of a lattice with raised gates. 1μm~10μ… silicone urethane)
- It has the characteristic of reinforcing the strength of

（発明の実施例） 本発明の構成及び実施例を図面に基づいて説明する。Ｐ
ｔＩＪ１図は、本発明に係るシリコン・ウエノ１一基板
の断面図であり、ｎ４シリコン・ウェハー基板１の一面
に１μＩ１１〜１０μ輸のｎ　エピタキシャル層２を配
設した状態を示す面である。(Embodiments of the Invention) The configuration and embodiments of the present invention will be described based on the drawings. P
Figure tIJ1 is a cross-sectional view of a silicon wafer substrate 1 according to the present invention, showing a state in which an n 2 epitaxial layer 2 of 1 μI11 to 10 μm is disposed on one surface of the n4 silicon wafer substrate 1.

第２図は、＋１＋シリコン・ウニへ−基板１の他面にＫ
ＯＨ水溶液などに対するＳｉＯ２またはＳｉ。Figure 2 shows +1 + silicon sea urchin - K on the other side of substrate 1.
SiO2 or Si for OH aqueous solution etc.

Ｎ４などの格子状の保護膜３をＣＶＤ法（Ｃｈｅｍｉｃ
ａｌ　Ｖ　ａｐｏｒ　Ｄ　ｅｐｏｓｉｔｉｏｎ：気相ｒ
＆長法）により配設しｒこ状態を示す図である。A lattice-like protective film 3 made of N4 or the like is formed using the CVD method (Chemical
al V apor D eposition: gas phase r
FIG.

第３図は、本発明に係るシリコン・ウエノ１一基板の拡
大断面図であり、シリコン・ウェハー基板１の他面に格
子状の保護膜３を配設したシリコン・ウェハー基板１を
陽極電解研磨法を用いてエツチングを行なうことにより
、格子状の保ｉ！膜３を配設したシリコン・ウェハ一部
分のみを残存し、補強リブ１ａを形成する。FIG. 3 is an enlarged cross-sectional view of the silicon wafer substrate 1 according to the present invention, in which the silicon wafer substrate 1 with a lattice-shaped protective film 3 disposed on the other surface of the silicon wafer substrate 1 is anodic electrolytically polished. By performing etching using the method, a lattice-like preservation i! Only a portion of the silicon wafer on which the membrane 3 was disposed remains, forming reinforcing ribs 1a.

第４図に示すように、シリコン・ウェハー基板１の他面
に陽極電解研磨法によりエツチング処理された凹凸の格
子状の補強リブを配設することにより、シリコン・ウェ
ハー基板１の反りまたは歪みなどを補強することができ
る。As shown in FIG. 4, by providing reinforcing ribs in the form of a lattice of unevenness etched by anodic electropolishing on the other surface of the silicon wafer substrate 1, warping or distortion of the silicon wafer substrate 1 can be prevented. can be reinforced.

（発明の効果） 本発明は、以上の構成であるから、１μＴ＠〜１０μ論
の超薄型のシリコン・ウェハー基板における反りまたは
歪みを防止できるとともに、超高速ＬＳＩシリコン・ウ
ェハーにおけるシリコン・チップの熱容量を低下できる
効果を奏する。(Effects of the Invention) Since the present invention has the above configuration, it is possible to prevent warpage or distortion in ultra-thin silicon wafer substrates of 1μT@10μ theory, and to prevent warping or distortion of silicon chips in ultra-high-speed LSI silicon wafers. It has the effect of reducing heat capacity.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、ｔＩＳ２図および第３図は、本発明の構造を示
す断面図、第４図は、本発明の実施例を示す斜視図であ
る。 １・・・シリコン・ウェハー基板 １ａ・・・補強リブ ２・・・エピタキシャル層 ３・・・保護膜1, tIS2, and 3 are cross-sectional views showing the structure of the present invention, and FIG. 4 is a perspective view showing an embodiment of the present invention. 1... Silicon wafer substrate 1a... Reinforcement rib 2... Epitaxial layer 3... Protective film

Claims (1)

【特許請求の範囲】 　シリコン・ウェハー基板の一面にはエピタキシャル層
を、 該シリコン・ウェハー基板の他面には格子状の保護膜を
配設し、かつ、電解研磨法によりエッチング処理して成
る凹凸状の補強リブを具備したことを特徴とするシリコ
ン・ウェハー基板。[Claims] An epitaxial layer is provided on one side of a silicon wafer substrate, a lattice-shaped protective film is provided on the other side of the silicon wafer substrate, and the unevenness is formed by etching using an electrolytic polishing method. A silicon wafer substrate characterized by having reinforcing ribs.
JP60025733A 1985-02-13 1985-02-13 Silicon wafer-Substrate Expired - Lifetime JPH0626176B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60025733A JPH0626176B2 (en) 1985-02-13 1985-02-13 Silicon wafer-Substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60025733A JPH0626176B2 (en) 1985-02-13 1985-02-13 Silicon wafer-Substrate

Publications (2)

Publication Number Publication Date
JPS61185933A true JPS61185933A (en) 1986-08-19
JPH0626176B2 JPH0626176B2 (en) 1994-04-06

Family

ID=12174014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60025733A Expired - Lifetime JPH0626176B2 (en) 1985-02-13 1985-02-13 Silicon wafer-Substrate

Country Status (1)

Country Link
JP (1) JPH0626176B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02264217A (en) * 1989-04-05 1990-10-29 Matsushita Electric Ind Co Ltd Ferroelectric liquid crystal display device
JP2007317950A (en) * 2006-05-26 2007-12-06 Toyota Motor Corp Manufacturing method for semiconductor substrate, and the semiconductor substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02264217A (en) * 1989-04-05 1990-10-29 Matsushita Electric Ind Co Ltd Ferroelectric liquid crystal display device
JP2007317950A (en) * 2006-05-26 2007-12-06 Toyota Motor Corp Manufacturing method for semiconductor substrate, and the semiconductor substrate

Also Published As

Publication number Publication date
JPH0626176B2 (en) 1994-04-06

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