JPS61184917A - Phase detection circuit - Google Patents

Abstract

PURPOSE:To detect lead/lag of a phase of both the 1st and 2nd signals by inputting an output from an EX-OR gate to which the 1st and 2nd signals and an output from an FF circuit latching the level of the 2nd signal at the changing point of time of the 1st signal to a gate circuit and operating it. CONSTITUTION:Suppose that a reference signal Is and a measured signal Im whose phase is retarded by W1 than that of the signal Is are inputted. An output of the EX-OR gate 10 is at level (a). On the other hand, an output from a D-FF11 remains 'H' as shown in figure (b). Thus, a pulse signal whose level is 'H' during the period W1 only and 'L' for the remaining period W2 is led to a display circuit 15 from an AND gate 12 as shown in figure (c). On the other hand, the output of the gate 13 remains 'L' as shown in figure (d). Thus, it is informed by display circuits 15, 16 that the phase of the signal Im is delayed than that of the signal Is.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a phase detection circuit capable of detecting the phase of a complex signal and suitably implemented in, for example, a frequency counter.

BACKGROUND ART FIG. 4 is an electrical circuit diagram showing a typical prior art. A reference signal having a reference frequency is connected from input terminal Is to EX-
Applied to one input terminal of OR date 1. Also, the signal under test having the frequency under test is input from input terminal I- to EX
- given to the other input terminal of OR date 1. EX-
The output from OR date 1 is provided to the base of transistor Tri. The collector of the transistor Tri is connected to the power supply +Vac via a series circuit of a light emitting diode D1 and a resistor R1. The emitter of transistor Tri is grounded. If the reference signal and the signal under test are out of phase, the output from EX-OR date 1 will be at a high level and transistor Tri will be turned on. As a result, a current flows from the power supply +Vcc to the light emitting diode D1, so that the light emitting diode D1 lights up to indicate that the reference signal and the signal under test are out of phase.

Problems to be Solved by the Invention The above-mentioned prior art can only display when the reference signal and the signal under test are out of phase, and cannot display phase lead or lag.

An object of the present invention is to solve the above-mentioned technical problems and provide a phase detection circuit that has a simple circuit configuration and can detect a lead or lag in the phase of two signals.

Means for Solving the Problems The present invention provides an EX-OR date at which a first signal and a second signal whose phases are to be detected are input, and an EX-OR date of the second signal at the time when the first signal changes in a stepwise manner. AND of the output of the 7-lip 70-tub that latches the level, the EX-OR date, and the 7-lip 70-tub.
The phase detection circuit is characterized in that it includes a date for calculating conditions.

According to the present invention, the output from the EX-OR date into which the first signal and the second signal whose phases are to be detected are input, and the second signal at the time when the first signal changes stepwise.
It is possible to detect the lead or lag in the phase of the first and second signals by inputting and calculating the output from the 7-lip 707 that latches the signal level to a gate circuit that calculates an AND condition. becomes.

Example FIG. 1 is an electrical circuit diagram of an embodiment of the present invention.

A reference signal having a reference frequency is transmitted from input terminal Is to EX
- It is applied to one input terminal of the OR date 10 and also applied to the D input terminal of the D-7 lip 70 tube 11. Further, the signal to be measured having the frequency to be measured is applied from the input terminal Is to the other input terminal of the EX-OR date 10 and also to the T input terminal of the 7-lip 70-tube 11.

The output from EX-OR date 10 is AND date 12
is applied to one input terminal of A, and the other A
It is given to one input terminal of ND date 13. D-7
The output from the lip 70 tube 11 is given to the other input terminal of the AND date 12, and the NOT circuit 14
is applied to the other input terminal of AND date 13 via .

The output from AND date 12 is given to display circuit 15. This display circuit 15 includes a resistor R2 and a light emitting diode D.
It consists of a series circuit consisting of a transistor Tr2 and a transistor Tr2. The output from AND date 12 is given to the pace of transistor Tr2, and this transistor Tr2
The collector of the transistor Tr2 is connected to the cathode of the light emitting diode D2, and the emitter of the transistor Tr2 is grounded. Resistance R
One end of 2 is connected to the power supply +Vec. The output from AND date 13 is fed to display circuit 16. This display circuit 16 is composed of a series circuit including a resistor R3, a light emitting diode D3, and a transistor Tr3. The output from the AND date 13 is applied to the base of the transistor Tr3, the collector of the transistor Tr3 is connected to the cathode of the light emitting diode D3, and the emitter of the transistor Tr3 is grounded. One end of the resistor R3 is connected to the power supply +Vee.

2 and 3 are timing charts of the phase detection circuit according to the present invention. first! #2 Referring to Figure 2, the reference signal shown in Figure 2 (1) was input, and the signal under test shown in Figure 3 (2) whose phase was delayed by Wl from this reference signal was input. Assume a case. Konoto 1kE
The output from X-OR date 10 is shown in FIG. 3(3). In other words, EX-OR date 10 is the period W from the rising edge of the reference signal to the rising edge of the signal under test.
A pulse signal is derived that is at a high level for only 1 and is at a low level for the remaining period W2. On the other hand, the output from the D-7 lip 70 tube 11 remains at a high level as shown in FIG. 2(4). Therefore AND date 1
2, as shown in FIG. 2(5), a pulse signal that is at a high level for a period W1 and is at a low level for a remaining period W2 is delivered to the transistor Tr2. On the other hand, the output from the AND date 13 remains at a low level as shown in FIG. 2 (6). Therefore, the transistor Tr2 is turned on for a period W1, turned off for a period W2, and is repeatedly turned on and turned off in this manner. Therefore, the light emitting diode D2 is turned on for a period W1, turned off for a period W2, and blinks repeatedly. On the other hand, the light emitting diode D3 remains off because the transistor Tr3 remains cut off. By visually observing the blinking state of the light emitting diode D2, it is announced that the signal to be measured is delayed in phase with respect to the reference signal.

Note that the greater the phase difference between the signal under test and the reference signal, the longer the lighting period of the light emitting diode D2 becomes.

Next, a case where the signal under test leads the reference signal in phase will be explained. In other words, assume that the signal under test leads the reference signal in phase by Wl as shown in FIG. 3(2) with respect to the reference signal shown in FIG. 3(1). At this time, the output from EX-OR date 10 is at a high level for a period W1, as shown in FIG. 3(3), and is at a low level for a remaining period W2. On the other hand, the output from the D-7 lip 70 tube 11 is as shown in Figure 3 (4).
), it remains at low level after waiting for input of the signal under test. Therefore, the output from AND date 12 is
The output from AND date 13 remains at a low level as shown in FIG. 3(5), while the output from AND date 13 is at a high level for a period W1 and only for the remaining period W2, as shown in FIG. 3(6). A pulse signal having a characteristic of being at a low level is derived. Therefore, the transistor Tr2 remains cut off, so that the light emitting diode D2 remains off. On the other hand, the transistor Tr3 is conductive for the period W1 and disconnected for the remaining period W2, and this series of operations is repeated. Therefore, the light emitting diode D3 is turned on for the period W1 and turned off for the remaining period W2, and as this operation is repeated, the light emitting diode D3 is blinked. Therefore, by visually observing the blinking state of the light emitting diode D3, it is announced that the signal to be measured is ahead of the reference signal in phase. Note that, as described above, the larger the phase difference is, the longer the lighting period of the light emitting diode D3 becomes. Thus, in this example, 1.
two. ffi't fl (i [Ka1.E15.6Ka1.E1,.1.
It becomes possible to notify by the lighting state of D3. Note that the display means is a light emitting diode D2. Instead of the visual display means using D3, the notification may be made by audible means such as a buzzer, or an external peripheral device may be directly connected instead of the display means.

In this manner, in this embodiment, it is possible to detect the phases of two signals and also to detect and display the lead and lag of the phases.

Effects of the Invention As described above, according to the present invention, it is possible to detect the phase lead and lag between two signals with a simple circuit configuration.

[Brief explanation of drawings]

Figure 1 is an electrical circuit diagram of an embodiment of the present invention, Figure 2 is a timing chart when the signal under test is delayed in phase than the reference signal, and Figure 3 is the phase of the signal under test that is later than the reference signal. FIG. 4 is a typical prior art electrical circuit diagram. 10...EX-OR gate, 11...D-7 lip circuit, 15.16...display circuit, Is, Ia+...
・Input terminal

Claims (1)

[Claims] An EX-OR date into which a first signal and a second signal whose phases are to be detected are input, and a flip-flop that latches the level of the second signal at the time when the first signal changes in a stepwise manner. AND the output of EX-OR date and flip-flop
A phase detection circuit comprising: a date for calculating a condition;