JPS61184867A - Dram cell and making thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and in particular to dynamic read/write memories, ie, dynamic RAMs (hereinafter referred to as dRAMs).

[Prior art 1] The development of large-scale monolithic dRAMs poses many problems, one of the most important of which is that in order to increase the number of memory cells integrated on a single chip, The question is how to prevent the incidence of soft errors from increasing even when the dimensions are reduced. Large-scale dRAM uses silicon as its primary construction material, and each memory cell typically has a single MO3 field effect transistor whose source is connected to the capacitor, drain to the bit line, and gate to the word line. It is.

Such a memory cell operates such that when a charge is applied to the capacitor, it becomes a logic 1, and when it is not, it becomes a logic 310. In this case, the conventional method is to form the QA7 passator by an inversion layer separated from the upper electrode layer by a thin oxide layer and separated from the substrate by a depletion layer. However, in order to maintain stable circuit operation, the capacitor must have a sufficient S/N ratio.
It is necessary to set the capacitor to a large value that gives a high ratio, and for this purpose, the area occupied by the capacitor within the substrate must be increased. Furthermore, MOS like this
Capacitors are susceptible to electric charges generated in the substrate by alpha particles (5 MeV alpha particles can generate more than 200 hemtocoulombs (fC) of disaster electrons), noise that enters from the substrate, and the entire area of the capacitor. PN junction leakage across and MOSF in the cell
Easily affected by ET subthreshold leaks, etc.

The charge stored in one dRAM is normally 250 fC, so if the power supply voltage withstand voltage is 5 mm, the capacitance of the capacitor needs to be 50 fF, and the thickness of the dioxide layer for charge storage is 150 fC. In this case, approximately 20 microns square of capacitor area was required. In a memory cell using a conventional two-dimensional structure dRAM, this defines the minimum size of the cell.

One attempt to address these problems is the ``dynamic RAM cell in recrystallized polysilicon (4rE
EE Elec, Dev, Lctt, s.

(1983), which attempts to form all of the basic elements of the cell, including access transistors and charge storage capacitors, in a beam-recrystallized polysilicon layer deposited on an oxide layer on a silicon substrate. In this case, the bit line is included in the recrystallized polysilicon layer, and turning on the transistor causes charge to flow into the charge storage region. The charge storage region is made of recrystallized polysilicon with a high impurity content and surrounded by thermally grown oxide on the top, bottom and three sides. The charge storage capacity obtained in this way is approximately the same as that of a normal capacitor with an equivalent storage area, because the electrodes above and below the region are separated from the charge storage region in the recrystallized polysilicon by a thin oxide layer. It will be doubled. Moreover, this charge storage region is isolated by the underlying oxide from charges injected into the substrate from circuits around the region, and from charges penetrating into the substrate due to alpha particles and other radiation that causes soft errors. Become. Additionally, the presence of a thick oxide layer below the bit line and complete sidewall oxide isolation may reduce the capacitance of the bit line. However, even if the capacity is twice the normal capacity, it is impossible to make the area occupied by the cell capacitor sufficiently small.

Another attempt to miniaturize dRAM is to extend the capacitor plates into the interior of the substrate.

Such a capacitor is called a corrugated (wave-shaped) capacitor, and is described in [Corrugated capacitor cell for mega-pit dynamic MOS memory (CCC)] by H. Sunami et al.
)J (IEEEIEDM Tech, Diaes
t 806.1982) and Sunami et al.'s corrugated capacitor cell (CCC) J (41EEE Ele
c, Roev, Lett.

90.1983>, and also ■Ito et al.'s "On-chip voltage limiter followed by experimental IMbDRAMJ (19
84IEEE ISSCC Digest of Te
ch, Paper 282), etc.

This corrugated capacitor extends to a depth of 2.5 microns inside the silicon substrate and is fabricated using a CVD di-oxide silicon dioxide mask and a conventional carbon dioxide mask.
After forming the trench by reactive sputter etching using Cl4, wet etching is performed to remove scratches and dirt caused by dry etching. After forming the i-trench, a charge storage layer 81 consisting of three layers of silicon dioxide/silicon nitride/silicon dioxide is formed on the trench walls, and the trench is then filled with LPCVD polysilicon. . In the case of a three-layer, 7-micron cell with a capacitance of 60 fF, such a corrugated capacitor has a capacity ω more than seven times that of a normal cell.

A third attempt to reduce the footprint of a cell capacitor is similar to the method of forming trenches as described above, and is described, for example, by E. Arai [Submicron MO8VLSILSI Provis (IEEE IE
DM Tech, Digest 19.1983>Yani, Minegishi et al. [Submicron dynamic RAM using impurity-doped face trench capacitor cells]
IEEE IEDM Tech, Dig
est 319゜1983>, below, [Debrission Trench Capacitor Technology J for Megabit Class MO8DRAM (41EEE Elec
, Dev.

Lctt, 411.1983) etc., but
These all describe memory cells having a structure similar to that of a normal cell, except that the capacitor plate is formed on the trench wall of the substrate instead of being parallel to the substrate. Such trench capacitors can have a large capacitance per unit area of the substrate simply by using a deep trench, and meet the above 3 requirements.
According to the paper, it is produced as follows. That is, first, a trench having a width of 0.4 to 1.0 microns is formed in a silicon substrate having a crystal orientation of (100), a P type, and a resistivity of 4 to 5 ohms by an electron beam direct writing method.

It is then etched to a depth of 1-3 by reactive ion etching (RIE) with CBrF3 under a pressure of approximately 14 mmTorr.
After engraving a micron trench, an etching process is performed in a mixed solution of nitric acid, acetic acid, and hydrofluoric acid to remove scratches caused by the RIE process from the sidewalls of the trench. Next, PSG (phosphorus silicate glass) is deposited by CVD using a PH/5iH4102 gas system to diffuse phosphorus into the trench surface layer, and the PSG is etched away with hydrofluoric acid. Next, 150-5 on the trench surface.
000000 SiO2 is grown in dry oxygen or Si3N4 is deposited by CVD to a thickness of 5000, and finally the trenches are filled with LPCVD polysilicon.

In this way, the capacitance per unit area of the trench sidewall is comparable to the capacitance per unit area of a normal capacitor, and therefore, a capacitor with a large trench depth is
By increasing the charge storage area per unit area of the substrate, it is possible to reduce the substrate area of the cell.

On the other hand, it is a well-known technique to perform isolation using trenches, and its research has been widely conducted, for example, in Deep Trench Isolated CMOS Devices J (IEEE IED) by R.
EM 1ech, Digest 237.1982)
``Study on the problem of trench inversion in trench 0 MO8 technology J (41E
E E Elec, Dev.

Lett, 303.1983) and A. Hayasaka et al., “U-shaped groove isolation technique J for high-speed bipolar VLSI (IEEE IEDEMTech,
Digest 62, 1982), Goto et al., Isolation Techniques J for High Performance Bipolar Memories (IEEE IEDEMTech
, Digest 58, 1982> and Wang, Yamaguchi et al., “High-speed latch-up elimination 0.5 micron channel CMO8J using self-aligned T i Sl 2 deep trench isolation technology (IEEE
IEDEM Tech, Dioest 522
1983) and the direction of rcMO8 technology by S. Koyama et al.
Tech.

Digest 151, 1983 >, “Characterization and schematization of trench surface problems related to trench isolated type 0MO8 technology” by K. and Chava et al.
E IEDEM Tech, Digest 2
3゜1983) and others. The isolation trenches described therein are formed in a manner similar to that previously described for the production of trench-formed fully gated capacitors. i.e. patterning (typically done using an oxide mask), C3rF5C
It uses processing procedures such as RIE processing using C1, CCIH2, CC1402, etc., etching processing, thermal oxidation of the sidewall portion (accompanied by nitride layer formation by LPCVD method), and embedding with polysilicon. .

[Problems to be solved by the invention] However, using a trench capacitor reduces the dR
This does not completely solve the problem of miniaturizing AM cells (in either case, such as horizontally arranged FETs or almost vertically arranged trench capacitors),
At present, the area occupied by the cell on the substrate is still large.

[Means for Attempting to Solve the Problems] The present invention forms a cell transistor on the sidewall of a trench provided in a substrate in which a cell capacitor is formed, and the trench is located below the intersection of the word line and bit line of the array. The present invention provides a structure for a one-transistor dRAM cell located in a trench, and an array of such cells. By stacking the transistor above the capacitor in the trench, the cell area on the substrate is reduced. This is designed to minimize the amount of noise and increase the integration density of individual cells.

In one embodiment of the invention, the transistor gate I.
The regions are formed by polysilicon filled in the top of the trench, and the channels of the capacitor and i-transistor are formed in the polysilicon filled in the bottom of the trench and the sidewalls of the trench. Note that the signal charge is accumulated in the capacitor plate formed of the polysilicon and is isolated from the substrate, and the transistor is similarly isolated from the substrate material.

[Embodiment] FIG. 1A shows a one-transistor, one-capacitor cell connected to a bit line and a word line as an embodiment of the present invention, and its operation mode is as follows. That is, the capacitor 12 stores a charge representing one bit of information (for example, a state in which no charge is stored represents a logic 0, and a state in which a charge corresponding to a potential of 5 volts across the capacitor plate is stored represents a logic 1). ). This one bit of information is accessed (read or write a new bit) each time a voltage is applied to the word line 14 connected to the gate 16.
This turns on transistor 18. When transistor 18 is turned on, capacitor 12 is brought into conduction with bit line 20, and reading or writing is performed. At this time, it is necessary to periodically refresh the charge in order to compensate for the disappearance of the charge accumulated in the capacitor 12 due to leakage current or other causes, and this is the origin of the name dynamic RAM (dRAM).

FIG. 1B is a plan view showing a part of the array in which the memory cells 30 of the above embodiment are arranged at the intersection of each line in a dRAM array consisting of a word line 14 and a bit line 20, where the word line 20 is a word line. It is formed to pass below 14. These memory cells 3
The zeros extend below these lines in the board to maximize memory density. As shown in the figure, if the minimum figure dimension is f and the minimum allowable layer spacing dimension (minimum allowable amount of printing error) is R, the area of each cell is (a(f
-1)). Therefore, for example, the minimum figure size is 1.0
If the minimum interlayer tolerance is 0.25 microns, the area of each cell will be approximately 6.25 square microns.

FIG. 2 is a sectional view of the memory cell 30 according to an embodiment of the present invention. This memory cell 30 is formed on a P-type silicon substrate 32 having a P-type shrimp layer 34, and is made up of a word line 14 made of N-type polysilicon, an N-type buried layer 21, and an N-type layer 23. The bit line 20, the oxide layer 25 for bit line isolation, the oxide 842 for pit line isolation, the word line 14 made of N+ polysilicon, the channel 44 of the transistor 18, and the gate oxide of the transistor 18. layer 4
6 and N forming the source region of this transistor 18.
48, and the P-shaped substrate 32 is connected to the capacitor 12.
An N+ polysilicon region 50 forming one of the plates, that is, the other plate when used as a ground side plate, and an oxide layer forming an insulating layer between both plates of this capacitor 12.
It includes a nitride/oxide stack 52, an insulating oxide layer 54 that isolates the channel region 44 from the shrimp layer 34, and an insulating oxide layer 56. The cross section of the memory cell 30 in FIG. 2 is taken along the arrow 112-- in FIG. 1B.
2, and therefore the cross-sectional structure of trench-formed capacitor 12 and transistor 18 will be clear from this FIG. 1B.

In the memory cell 30 configured as described above, one plate of the capacitor 12 is formed by the N+ region 50 and the N region 48, and the other plate is formed by the substrate 32 and the shrimp layer 34, respectively. However, in this case,
By setting the impurity concentration of the epi M34 to be much lower than that of the P-type substrate 32, the diffusion region 48 and the region 4
8/Stack 52/Capacity and area of the engineering layer 34 50/
The capacitance of the stack 52/process layer 34 is all in the N+ region 5.
The capacitance of the 0/stack 52/P0 board 32 is much smaller than that of the board 32, and is set to a value that can be ignored. Further, as explained next, the plate area of the shrimp layer 34 is the same as that of the substrate 3.
For this reason as well, the capacity associated with the shrimp layer 34 is not a very important factor. Note that when the cross section of the trench to be formed is 1 x 1 micron and the depth is 6 microns, if 2 microns of this depth is obtained by the shrimp layer 34 and the bit line 20 layer, the capacitor 12 The plate area of is approximately 17 microns square. Also, the illustrated P-substrate 32 is a ground layer common to all memory cells 30 in the array shown in FIG. 1B.

The transistor 18 of each memory cell 30 has its polysilicon channel region 44 covered with an oxide layer 54.
its source region 48 (which is also part of one plate of capacitor 12) and drain region 2
0 (which is also a part of the bit line 20) is an impurity-introduced portion of the polysilicon layer forming the channel region VL44, which will be described further later. Transistor 18 thus has the characteristics of a polysilicon transistor, but is isolated from substrate 32 and shrimp layer 34 by oxide layer 54.

The oxide layer 25 has a considerable thickness to reduce the capacitance Φ of the bit line 20.

Further, signal charges are stored in the N+ polysilicon layer 50,
The stack 52 isolates it from the substrate 32 .

Next, an example of a method for manufacturing the memory cell 30 having the above structure will be described, and through this description, the dimensional and material characteristics of the memory cell 30 will also be clarified. Figures 38 to 3E show this manufacturing procedure.

(a) A P+ silicon base plate 32 with a resistivity of 1 x 10-2 ohm α or less with a crystal orientation of 100, a carrier concentration of 2 x 10 cells/caI3, and a thickness after all heat treatments and diffusion reactions are completed. , a P layer 34 having a final thickness of 1.5 microns is grown. Next, an oxide layer 25 is grown to a thickness of 2000 nm and LPC
N+ type polysilicon pJ to thickness 3000 by VD method
After depositing 21, the carrier concentration was 1×1020/Cl4.
Dope to 3. Then 1 micron thick oxide 11i
64 is deposited by plasma enhanced LPCVD. The structure thus obtained is shown in FIG. 3A.

0 Patterning the oxide layer 64 and cutting it
Define a trench area of microns square.

This patterned oxide layer 64 is then used as a mask to perform a reactive ion etch to remove H.
After trenches with a depth of 6 microns are dug with Cl, the side walls and bottoms of these trenches are wet-etched with acid to remove scratches and dirt caused by the reactive ion etching. The stack 52 is then formed on the sidewalls and bottom of this trench as described below. That is, first, an oxide layer is grown to a thickness of 100 nm, and then a nitride layer is deposited to a thickness of 75 nm by LPCVD. This nitride layer is thermally oxidized to improve its dielectric properties, thus obtaining an oxide/nitride/w1ide stack 52. Subsequently, the trench is filled with polysilicon doped with N0 type impurities. The structure thus obtained is shown in Figure 38 □.

(f) After flattening the polysilicon B50 by spin coating on photoresist, for example, plasma etching is performed to form the interface between the shrimp layer 34 and the substrate 32 on the surface and in the trench. Remove the top part. In this case, as will be explained later, the position of the upper surface of polysilicon layer 50 remaining in the trench is not very important. The oxide layer 64 is then etched to remove exposed portions of the stack 52. The structure thus obtained is shown in FIG. 3C.

Fourth, add an oxide layer with a thickness of 1000 using conventional LPCV
After deposition by method D, an anisotropic etch is performed to leave sidewall oxide layer 54. Subsequently, a polysilicon layer 41 is deposited by LPCVD to contact the N0 region 50 and the N0 region 14!21. The thickness of this polysilicon region 41 is set to 2000 nm, and boron ions B+0 are implanted at 200 keV to make it P type (thereby, the peak value of the impurity density is located approximately in the middle of the vertical channel region). ), adjust the threshold voltage of the transistor. The structure thus obtained is 3D
As shown in the figure.

(e) Next, the polysilicon layer 41 is subjected to ordinary furnace annealing or beam recrystallization to increase the grain size and improve device characteristics. Also, by this process, the N-type region 21.5
Impurities diffuse from 0 to N-type regions 23.48, respectively.
is also formed. On the other hand, polysilicon layer 41
The non-introduced portion becomes the channel region 44. Thus area 2
Oxide layers 42, 46, and 56 are grown on 3.44° 48, respectively. Note that these oxide layers are formed thicker on the impurity introduced region l1123.56 than on the non-introduced region 44, and the respective thicknesses are determined by the desired thickness of the gate oxide layer 46. In the illustrated cell 30, the gate oxide layer 46 is approximately 250 nm thick. The structure thus obtained is shown in Figure 3E.

Finally, a layer of N0 type polysilicon 14 is deposited and patterned to form the word line 14. The cell thus obtained has the structure shown in FIG.

Although the embodiments of the present invention have been described above, the described embodiments can be modified in various ways as long as the signal charge accumulation by the capacitor and the on/off function of the transistor are not impaired.

Examples of such modifications include the following.

First, the cross-sectional shape of the trench can be any convenient shape, such as circular, oblong, arbitrary concave, wavy, or composite connected shape, and the shape can be continuous in the vertical direction. Alternatively, it can be changed stepwise, or partly continuously and partly stepwise. Similarly, the sidewalls of the trench do not necessarily have to be vertical; they can be formed in any other way, for example by having a portion of the sidewall bulge laterally, being tapered overall, or having other slopes. No matter what shape it is,
It is reasonably effective. In fact, for example, in the case of a configuration in which trenches are simply connected, the trenches will be topologically similar to the rectangular parallelepiped shape in the described embodiment. Furthermore, the various dimensions of the trench (depth, cross-sectional area, diameter, etc.) can be changed in various ways, but in practice these depend on the conditions for convenient processing, the required capacitance, etc. This value is selected as a compromise value considering the board area, etc. Needless to say, the required capacitance in this case is determined by the refresh time, transistor leakage current, commercial voltage, margin against soft errors, capacitor leakage current, etc.

Furthermore, the material used for the insulating layer of the capacitor may be an oxide, a nitride, a laminated structure made of a combination of an oxide and a nitride, or a laminated structure made of a combination of an oxide, a nitride, and an oxide. can do. Also,
As an oxide, this is produced by thermal growth method or LPCVD method.
Alternatively, it can be formed by a dry growth method or a steam growth method. Furthermore, the thickness of this insulating layer is selected as a compromise value taking into consideration conditions for convenient processing, reliability of the insulating layer, dielectric constant, breakdown voltage, etc., but this value can also be changed over a wide range. can do. If the cell and array are made of a semiconductor material other than silicon (for example, gallium arsenide, mercury cadmium telluride, germanium, indium phosphide, etc.), the insulating layer of the capacitor shall also be made of a similar material. . It is also possible to use amorphous silicon instead of polysilicon.

In general, the transistor adjusts its threshold voltage in accumulation mode or inversion mode and as an N-channel or P-channel device (this may be done, for example, by shallow diffusion into the channel region immediately before the growth or deposition of the gate oxide layer). (by forming layers), the transistor can be made to operate at different threshold voltages. In this case, the doping level and the material used as the dopant can be varied in various ways to change the characteristics of the transistor. However, the channel length of the transistor is approximately determined by the depth of the trench, and the channel width is approximately equal to the distance between the peripheral edges of the trench. Generally speaking, in the case of silicon transistors, the doping level and channel thickness have a large effect on their performance, and their values can be changed significantly. For example, the channel thickness can vary from a few to one-half the trench diameter (provided that adequate space is reserved for the gate insulator and gate). Furthermore, the gate of the 1-transistor can be made of polysilicon, metal, silicide, or the like. When various changes are made as described above, the characteristics of the transistor will also change accordingly, but such changes will not affect the required readout as long as it operates properly as a pass transistor for the cell in question. There is no problem in view of other cell characteristics such as write time, capacitance, and refresh time.

In another embodiment of the memory cell of the present invention, the source region is formed by diffusing impurities from the first material layer.

In another embodiment of the memory cell of the present invention, a conductive line insulated from the substrate is provided loosely on the substrate, and the drain region is formed by diffusing impurities from the conductive line.

In another embodiment of the memory cell of the invention, the substrate is a silicon layer and the first, second and third material layers are each polysilicon layers.

Yet another embodiment of the present invention provides a one-transistor, one-capacitor memory cell formed in a trench in a substrate, comprising:
(b) a second capacitor plate formed in a second region of a first material layer inserted primarily into the lower part of the trench; (e) a capacitor insulating layer formed on the sidewalls of the trench between the second regions; (e) a third insulating layer formed on the sidewalls of the trench; a transistor channel region formed in the second material layer; and a transistor source region formed in the fourth region of the second material layer and formed by diffusing impurities from the first material layer. 0 a transistor drain region formed in a fifth region of the second material layer and formed by diffusing impurities from a conductive line on the substrate; (i)
A one-transistor, one-capacitor type memory cell comprising a gate insulating layer formed on a side wall of the trench between the gate region and the channel region.

Another embodiment of the present invention is a memory cell array formed in a substrate, including: (a) a plurality of first conductor lines arranged parallel to each other on the substrate; and (b) these first IJ conductors. Each of these cells consists of a plurality of mutually parallel second conductor lines that intersect and are insulated from each other, and a plurality of hills placed at the intersections of these first and second conductor lines, respectively. comprises a field effect transistor and a capacitor formed in a trench in the substrate directly below the intersection, a first plate of the capacitor being formed primarily on the sidewall of the trench and a second plate formed in a material inserted into the trench. and is insulated from the first plate by an insulator on the sidewall, while the transistor is insulated from the substrate by a second insulator on the sidewall and insulated from the insulator for the capacitor. the drain is coupled to one of the first conductor lines and the gate is coupled to one of the second conductor lines.
A memory cell array having a source coupled to a second plate of the capacitor.

A method for manufacturing a one-transistor, one-capacitor device in a trench memory cell of a semiconductor substrate, comprising: (a) forming a trench in the substrate; (f) forming an insulating layer on the sidewalls and bottom of the trench; and (f) doping an impurity. Filling the lower part of the trench with a conductive material introduced with the conductive material, and depositing a second material layer on the unfilled upper part of the trench to form the source and channel regions of the transistors 1 to 1. , and a drain region, and the source region is formed by diffusing impurities from the conductive material into the second material; (e) forming an insulating layer on the second material layer; , (0) A method for manufacturing a one-transistor, one-capacitor device characterized in that a gate is formed in an insulator layer on this second material layer.

[Brief explanation of drawings]

FIG. 1A and FIG. 1B each show a dRA according to the present invention.
A schematic diagram showing a circuit of M cells and a plan view showing a cell array using the cells, FIG. 2 is a dRAM according to the present invention.
A sectional view showing the first embodiment of the cell taken along the line 2-2 in FIG.
It is a figure which shows a series of processes in the case of manufacturing by the Example. 12 - Capacitor, 14... Word line, 16... Gate, 18... Transistor, 20... Pit line, 21.50... Polysilicon region, 25.42, 46° 54.56 .64... Oxide layer, 30... Memory cell, 32... Substrate, 34... Shrimp layer, 44... Channel, 52... Oxide/nitride/oxide stack.

Claims (1)

[Claims] (1) In a memory cell formed in a substrate, (a) one plate formed in a trench of the substrate and mainly formed within the sidewall of the trench, and a first material mainly inserted into the trench; (b) a capacitor formed in the trench and having a drain thereof;
a third layer of material with a channel and source region inserted into the trench, a second layer of material adjacent to the first material and insulated from the sidewalls, and a gate thereof inserted into the trench; and a transistor further comprising a gate insulating layer between the gate and the channel region.