JPS6118370B2 - - Google Patents

Info

Publication number
JPS6118370B2
JPS6118370B2 JP20121581A JP20121581A JPS6118370B2 JP S6118370 B2 JPS6118370 B2 JP S6118370B2 JP 20121581 A JP20121581 A JP 20121581A JP 20121581 A JP20121581 A JP 20121581A JP S6118370 B2 JPS6118370 B2 JP S6118370B2
Authority
JP
Japan
Prior art keywords
line
conductive
delay line
inductance element
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP20121581A
Other languages
Japanese (ja)
Other versions
JPS58101513A (en
Inventor
Kazuo Kametani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Erumetsuku Kk
Original Assignee
Erumetsuku Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Erumetsuku Kk filed Critical Erumetsuku Kk
Priority to JP20121581A priority Critical patent/JPS58101513A/en
Publication of JPS58101513A publication Critical patent/JPS58101513A/en
Publication of JPS6118370B2 publication Critical patent/JPS6118370B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/30Time-delay networks
    • H03H7/34Time-delay networks with lumped and distributed reactance

Description

【発明の詳細な説明】 本発明は、インダクタンス素子と容量を組合せ
てなる遅延線に係り、低周波から極めて高い高周
波に至るまでの非常に広い周波数帯域の使用に適
する遅延線に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay line formed by combining an inductance element and a capacitance, and relates to a delay line suitable for use in a very wide frequency band from low frequencies to extremely high frequencies.

従来、立上り時間の速い、例えば立上り時間が
1ns以下の遅延線としては、同軸ケーブルを目的
の遅延時間となる長さに切つたものや、メアンダ
ーライン等の分布定数回路の一種と考えられるも
のが提案されている。しかし前者は形状が大きく
端末処理が面倒であるし、後者は形状も大きく高
価であるうえ特性が良好でないという理由から、
いずれも実用化されていない。
Traditionally, the rise time is fast, e.g.
As a delay line of 1 ns or less, a coaxial cable cut to a length that provides the desired delay time, and a type of distributed constant circuit such as a meander line have been proposed. However, the former has a large size and terminal processing is troublesome, and the latter has a large size and is expensive, and its characteristics are not good.
None of these have been put into practical use.

また小型の遅延線としては、ボビンに複導線を
複数ターン巻いたインダクタンス素子とその導線
の複数ターン毎にアースとの間に接続された容量
を用いた集中定数型遅延線が適している。ところ
がこの遅延線は、周波数帯域が高くなるとインダ
クタンス素子が周波数特性を持つうえインダクタ
ンス素子のQも低下するため、遅延特性と振幅特
性が共に劣化して立上り時間が1ns以下の高速遅
延線には使用困難である。
Further, as a small-sized delay line, a lumped constant type delay line is suitable, which uses an inductance element made by winding multiple turns of a double conductor wire around a bobbin, and a capacitor connected between each of the multiple turns of the conductor wire and the ground. However, as the frequency band increases, the inductance element has frequency characteristics and the Q of the inductance element also decreases, so both the delay and amplitude characteristics deteriorate, making it unsuitable for high-speed delay lines with rise times of 1 ns or less. Have difficulty.

本発明は以上の欠点を解消するためになされた
もので、低周波から高周波まで極めて広い周波数
帯域での使用が可能な小型の遅延線の提供を目的
とする。
The present invention was made to eliminate the above-mentioned drawbacks, and aims to provide a small-sized delay line that can be used in an extremely wide frequency band from low frequencies to high frequencies.

以下本発明の詳細を図面を参照して説明する。 The details of the present invention will be explained below with reference to the drawings.

第1図および第2図は本発明の遅延線の一実施
例を示す図であり、特に第1図は本発明の遅延線
を構成するインダクタンス素子Lの導線路1を示
す展開図である。第1図においてインダクタンス
素子の導線路1は、ジグザグ状に折返して連結さ
れた導線路1と、この導線路における折返し部か
ら突設される接続片3とからなつており、個々の
各導線路は、幅W方向中央部すなわち導線路1上
の平行線X−XとY−Y間の領域において平行な
傾斜導線路1Eを有し、縦導線路1A,1B,1
C,1D…に分割されている。そのため各導線路
1は、傾斜導線路1Eを至て1ピツチP先行する
よう平行に形成されている。つまり各傾斜導線路
1Eの前後(図中上下)が、1ピツチずれてい
る。なお、導線路1の幅方向Wは、各導線路1の
延長線方向である。
1 and 2 are diagrams showing an embodiment of the delay line of the present invention, and in particular, FIG. 1 is a developed view showing a conducting path 1 of an inductance element L constituting the delay line of the present invention. In FIG. 1, a conductive line 1 of an inductance element is made up of a conductive line 1 which is folded back in a zigzag pattern and connected together, and a connecting piece 3 which is protruded from the folded part of this conductive line. has a parallel inclined conducting line 1E in the central part in the width W direction, that is, a region between parallel lines X-X and Y-Y on the conducting line 1, and vertical conducting lines 1A, 1B, 1
It is divided into C, 1D, and so on. Therefore, each conducting line 1 is formed in parallel so as to precede the inclined conducting line 1E by one pitch P. In other words, the front and rear (top and bottom in the figure) of each inclined conducting path 1E are shifted by one pitch. Note that the width direction W of the conductive line 1 is the direction in which each conductive line 1 extends.

そしてこのように形成された導線路1が、導線
路上の平行線X−XおよびY−Yでコ字状に折曲
げられ、ガラスや合成樹脂製の細長い非磁性絶縁
板2に接着され、第2図に示すようなインダクタ
ンス素子Lを構成している。インダクタンス素子
Lは、非磁性絶縁板2の一方の側面に傾斜導線路
1Eを、対向する主表面に傾斜導線路1Eの前後
の縦導線路1A,1B,1C,1D…を接着され
るとともに、他方の側面から接続片3が突出して
いる。
The conductive line 1 thus formed is bent into a U-shape along the parallel lines X-X and Y-Y on the conductive line, and is adhered to an elongated non-magnetic insulating plate 2 made of glass or synthetic resin. An inductance element L as shown in FIG. 2 is configured. The inductance element L has the inclined conductive line 1E bonded to one side surface of the non-magnetic insulating plate 2, and the vertical conductive lines 1A, 1B, 1C, 1D... before and after the inclined conductive line 1E bonded to the opposing main surface. A connecting piece 3 protrudes from the other side.

細長い絶縁板2の他方の側面には、接地電極6
を挾んで配置した誘電体板4の対向表面にコンデ
ンサ電極5を設けて構成されたコンデンサ素子C
が、インダクタンス素子Lの接続片3とコンデン
サ電極5を接続して固定されている。そしてイン
ダクタンス素子Lの各縦導線路1A,1B,1
C,1D…と、導線路の接続片3と接地電極6間
に形成されるコンデンサ素子Cとによつて第3図
に示すように集中定数型遅延線が形成される。
A ground electrode 6 is provided on the other side of the elongated insulating plate 2.
A capacitor element C is constructed by providing a capacitor electrode 5 on the opposite surface of a dielectric plate 4 which is arranged to sandwich the capacitor element C.
is fixed by connecting the connecting piece 3 of the inductance element L and the capacitor electrode 5. And each vertical conducting line 1A, 1B, 1 of the inductance element L
C, 1D, . . . and the capacitor element C formed between the connecting piece 3 of the conducting line and the ground electrode 6 form a lumped constant delay line as shown in FIG.

このように構成した本発明の遅延線は、インダ
クタンス素子Lの導線路1のうちの任意の近接す
る4本の縦導線路、例えば1A,1B,1C,1
Dについて考察すると、第2図Bに示す矢印方向
に流れる電流によつて同図Aのような磁束Φ
よびΦが生ずる。これらの磁束ΦおよびΦ
は、非磁性絶縁板2の対向する主面表上の対向す
る縦導線路1Aと1C、および1Bと1Dを流れ
る電流がそれぞれ同方向となるので、それぞれ正
の結合となつて形成されるものである。一方、そ
れぞれの主表面における隣り合う縦導線路1Aと
1Bおよび1Cと1D間は負の結合となるので磁
束ΦおよびΦはそれぞれ独立の短かい磁束ル
ープを形成する。これらの関係は任意の近接する
4本の縦導線路のどこを選んでも成立する。
The delay line of the present invention configured in this way can be constructed by connecting any four adjacent longitudinal conductive lines of the conductive line 1 of the inductance element L, for example, 1A, 1B, 1C, 1
Considering D, magnetic fluxes Φ 1 and Φ 2 as shown in FIG. 2A are generated by the current flowing in the direction of the arrow shown in FIG. 2B. These magnetic fluxes Φ 1 and Φ 2
The currents flowing through the opposing longitudinal conductive lines 1A and 1C and 1B and 1D on the opposing main surfaces of the non-magnetic insulating plate 2 are in the same direction, so that they are each formed as a positive coupling. It is. On the other hand, since there is a negative coupling between the adjacent longitudinal conductive lines 1A and 1B and 1C and 1D on each main surface, the magnetic fluxes Φ 1 and Φ 2 form independent short magnetic flux loops. These relationships hold true no matter which one of the four adjacent longitudinal conductive lines is selected.

このように磁束ΦおよびΦが非磁性絶縁板
2を挾んで2つの縦導線路による短かい閉ループ
を形成するので、インダクタンス素子Lは非常に
高い周波数まで平担なインダクタンス特性を有
し、かつ磁束ΦおよびΦが正の結合によつて
構成されるのでインダクタンスが増加し、極めて
高い高周波例えば1GHz以上の超高周波帯域にお
いても十分高インダクタンスが平担に得られる。
その結果、超高周波における超高速遅延線が得ら
れる。特にこの点は、インダクタンス素子のイン
ダクタンスの向上させるフエライト等の磁性体
が、超高周波帯域で導磁率が低下するとともに損
失が大きくなりボビンとして使用できない状況下
にあつても、非磁性絶縁板2を用いて高インダク
タンスが得られるので、極めて有用である。
In this way, the magnetic fluxes Φ 1 and Φ 2 sandwich the non-magnetic insulating plate 2 and form a short closed loop with two vertical conducting paths, so the inductance element L has an inductance characteristic that is flat up to very high frequencies. In addition, since the magnetic fluxes Φ 1 and Φ 2 are configured by positive coupling, the inductance increases, and a sufficiently high inductance can be easily obtained even in an extremely high frequency band, for example, an ultra-high frequency band of 1 GHz or more.
As a result, an ultra-fast delay line at ultra-high frequencies is obtained. In particular, this point is important because magnetic materials such as ferrite, which improve the inductance of the inductance element, have lower magnetic permeability in the ultra-high frequency band and large losses, making it impossible to use them as bobbins. It is extremely useful because high inductance can be obtained by using it.

また本発明の遅延線は、インダクタンス素子L
において、第3図の等価回路図における互に隣り
合う区間に相当する導線路1A,1C,1B,1
Dが正の結合となつて、第3図の等価回路図で示
すように誘導m型の集中定数型遅延線を構成し、
この点からも遅延特性を改善している。
Further, the delay line of the present invention has an inductance element L
, conductive lines 1A, 1C, 1B, 1 corresponding to mutually adjacent sections in the equivalent circuit diagram of FIG.
D becomes a positive coupling to configure an inductive m-type lumped constant delay line as shown in the equivalent circuit diagram of FIG.
From this point of view as well, the delay characteristics have been improved.

第4図および第5図は、本発明の遅延線の他の
実施例を示す図である。第4図はインダクタンス
素子の展開図であり、導線路1は折返し幅Wを上
述の第1図の折返し幅よりも長く構成してなり、
折返し幅W方向中央部の2本の平行線X−X,Y
−Y間に相当する位置に傾斜導線路1Eを有する
とともに、この傾斜導線路1Eと両折返し部1
F,1F(図中上端および下端)の間に各々2本
の平行線X′−X′,Y′−Y′に相当する間で傾斜導
線路1E′,1E′が形成されている。しかも両傾
斜導線路1E′,1E′は、中央の傾斜導線路1E
と同様にその前後の導線路が1ピツチ分だけ中央
の傾斜導線路1Eに対し逆方向にずれるように形
成されている。すなわち縦導線路1は、平行線X
−XとY−Yに相当する間に形成される傾斜導線
路1Eを基準とすると、その前後(図中上下)に
おいて傾斜導線路1Eによつてずれた折返しピツ
チP分を、平行線X′−X′,Y′−Y′に相当する間
に形成される傾斜導線路1E′,1E′によつて逆
方向に戻すように構成されている。
4 and 5 are diagrams showing other embodiments of the delay line of the present invention. FIG. 4 is a developed view of the inductance element, and the conductive line 1 has a folding width W longer than the folding width shown in FIG.
Two parallel lines X-X, Y at the center of the folding width W direction
-Y, and has an inclined conductive line 1E at a position corresponding to between
Inclined conductive lines 1E' and 1E' are formed between F and 1F (upper and lower ends in the figure) corresponding to two parallel lines X'-X' and Y'-Y', respectively. Moreover, both inclined conductive lines 1E' and 1E' are arranged in the central inclined conductive line 1E.
Similarly, the conductive lines before and after the conductive line are formed to be offset by one pitch in the opposite direction with respect to the central inclined conductive line 1E. In other words, the vertical conducting line 1 is parallel to the parallel line
-X and Y-Y, parallel line X'-X',Y' - Y' is configured to return in the opposite direction by inclined conductive lines 1E' and 1E' formed between the lines corresponding to Y' and Y'.

また導線路における折返し部たる横導線路1
F,1Fは、縦導線路よりも導線路の幅が広なつ
ており、後述するコンデンサ電極5,5として機
能する。
In addition, the horizontal conductor line 1 which is a folded part in the conductor line
F and 1F have conductive lines wider than the vertical conductive lines, and function as capacitor electrodes 5, which will be described later.

第5図は、このような第4図に示す導線路1を
用いた遅延線を示すものである。
FIG. 5 shows a delay line using the conducting line 1 shown in FIG. 4. As shown in FIG.

符号2,2′は細長い非磁性絶縁板であり、上
述の第2図の非磁性絶縁板2と同材質で厚味が僅
かに薄くなつている。そして前記第4図に示す導
線路1が平行線X−X,Y−Yに相当する箇所で
平行かつコ字状に折曲げられて非磁性絶縁板2に
接着され、かつ平行線X′−X′,Y′−Y′に相当す
る箇所が平行にX−X,Y−Y相当箇所とは逆方
向にコ字状に折曲げられ、非磁性絶縁板2′,
2′に接着されている。即ち導線路1がクランク
状に折曲げられ、3枚の非磁性絶縁板2,2′,
2′の対向する主表面に縦導線路が、また傾斜導
線路1E,1E′,1E′が側面面に配置されるよ
う止着されてインダクタンス素子Lを構成してい
る。なお導線路のコンデンサ電極5,5たる横導
線路1F,1Fは非磁性絶縁板2′,2′の同一方
向(図中下方)に位置している。
Reference numerals 2 and 2' designate elongated non-magnetic insulating plates, which are made of the same material as the non-magnetic insulating plate 2 shown in FIG. 2, but are slightly thinner. Then, the conducting line 1 shown in FIG. 4 is bent parallel to the U-shape at locations corresponding to the parallel lines The parts corresponding to X', Y'-Y' are bent parallel to each other in a U-shape in the opposite direction to the parts corresponding to X-X, Y-Y, and the non-magnetic insulating plates 2',
It is glued to 2'. That is, the conductor line 1 is bent into a crank shape, and three non-magnetic insulating plates 2, 2',
Vertical conductive lines 1E, 1E', and 1E' are fixed to the opposing main surfaces of 2', and inclined conductive lines 1E, 1E', and 1E' are fixed to the side surfaces thereof to form an inductance element L. The horizontal conductive lines 1F, 1F, which are the capacitor electrodes 5, 5 of the conductive lines, are located in the same direction (lower in the figure) of the nonmagnetic insulating plates 2', 2'.

インダクタンス素子Lの両側の非磁性絶縁板
2′,2′の長手方向下部には、コンデンサ電極
5,5を覆つて誘電体板4,4が形成され、この
誘電体板4,4には横断面U字状の接地板7が非
磁性絶縁板2′,2,2′を挾むように嵌合されて
コンデンサ素子Cが形成、配置され、集中定数型
遅延線が構成されている。
Dielectric plates 4, 4 are formed at the bottom of the non-magnetic insulating plates 2', 2' in the longitudinal direction on both sides of the inductance element L, covering the capacitor electrodes 5, 5. A U-shaped ground plate 7 is fitted to sandwich the non-magnetic insulating plates 2', 2, 2' to form and arrange a capacitor element C, thereby configuring a lumped constant delay line.

このように構成された遅延線は、第2図に示す
遅延線と同様に、非磁性絶縁板2′,2,2′を介
して対向する縦導線路が1ピツチづつずれている
ので、対向する縦導線路により発生する磁束がす
べて正の結合となり、一方向一平面上で隣り合う
縦導線路により発生する磁束が負の結合となつ
て、磁束が短いループを形成する。そのため、イ
ンダクタンス素子Lが非常に高い周波数帯域まで
平担で高いインダクタンスを示す。しかも正結合
する導線路の数が増加するとにより、インダクタ
ンス素子Lのインダクタンスが大巾に高くなる。
その結果、低い周波数から超高周波までの広い周
波数帯にて立上り時間の速い遅延線が得られる。
Similar to the delay line shown in FIG. 2, the delay line configured in this way has vertical conductor lines that are opposed to each other via non-magnetic insulating plates 2', 2, 2' and are shifted by one pitch. All the magnetic fluxes generated by the longitudinal conductive lines are positively coupled, and the magnetic fluxes generated by the vertical conductive lines adjacent in one direction and on one plane are negatively coupled, forming a short loop of magnetic flux. Therefore, the inductance element L exhibits a high inductance evenly up to a very high frequency band. Furthermore, as the number of positively coupled conducting lines increases, the inductance of the inductance element L increases significantly.
As a result, a delay line with a fast rise time can be obtained in a wide frequency band from low frequencies to very high frequencies.

またジグザグ状の導線路1の折返し幅Wを広く
して傾斜導線路の数を増加させて、コ字状に折曲
げる箇所を増加させるならば、非磁性絶縁板を挾
んで正結合する縦導線路の数が増えるので、イン
ダクタンス素子Lのインダクタンスを急増させる
ことが可能となる。なお導線路を折曲げる方向
は、第5図に示す例のほか第9図に示す如きもの
が考えられる。要は、ピツチをずらせて非磁性絶
縁板を挾んで縦導線路を正結合状態で対向させれ
ばよく、傾斜導線路の数や折曲げる数は目的とす
る遅延特性に合せて任意に決定すればよい。
Furthermore, if the folding width W of the zigzag-shaped conductor path 1 is widened to increase the number of inclined conductor paths and the number of places to be bent in a U-shape is increased, the vertical conductor path is positively coupled by sandwiching a non-magnetic insulating plate. Since the number of paths increases, it becomes possible to rapidly increase the inductance of the inductance element L. In addition to the example shown in FIG. 5, the direction in which the conducting path is bent may be as shown in FIG. 9. The point is to shift the pitch and sandwich the nonmagnetic insulating plates so that the vertical conductor lines face each other in positive coupling.The number of inclined conductor lines and the number of bends can be arbitrarily determined according to the desired delay characteristics. Bye.

さらに第5図に示す遅延線は、コンデンサ素子
の一方のコンデンサ電極5,5がインダクタンス
素子Lの導線路1における折返し部1F,1Fか
らなつているので、遅延線を構成するためのイン
ダクタンス素子Lとコンデンサ素子Cとの半田付
け等の必要がなくなる。したがつて接続不良が解
消して信頼性が向上し、接続工程の省略から組立
工数も減少してコストの大巾低減を図ることが可
能となる。
Furthermore, in the delay line shown in FIG. 5, since one capacitor electrode 5, 5 of the capacitor element is made up of folded parts 1F, 1F in the conducting path 1 of the inductance element L, the inductance element L is used to form the delay line. There is no need for soldering between the capacitor element C and the capacitor element C. Therefore, connection failures are eliminated, reliability is improved, and the number of assembly steps is reduced by omitting the connection process, making it possible to significantly reduce costs.

なお第5図に示す遅延線においても第2図の遅
延線と同様に誘導m型遅延線が得られるので、遅
延特性が極めて良好である。
Note that the delay line shown in FIG. 5 also provides an inductive m-type delay line similar to the delay line shown in FIG. 2, and therefore has extremely good delay characteristics.

上述の第1図ないし第5図に示す実施例におい
て、遅延線のインダクタンス素子Lを構成する導
線路1の傾斜導線路1E,1E′,1E′部分をコ
字状に折曲げているが、折曲げる幅を狭く、すな
わち上述の平行線X−X,Y−YおよびX′−
X′,Y′−Y′に相当する部分の内側の狭い幅と
し、非磁性絶縁板2,2′,2′の厚みも薄いもの
を用いる場合には、非磁性絶縁板2,2′,2′を
挾んで対向する縦導線路間の正の結合が増加する
ので、インダクタンス素子Lのインダクタンスが
より増加して良好な特性が得られるとともに、遅
延線の外形寸法を超小型化できる。なお縦導線路
間の正の結合の強さは、第3図に示す等価回路図
における隣区間のインダクタンス素子間の結合度
aの値とも関係するので、目的の特性に合せて導
線路を折曲げる箇所および非磁性絶縁板2,
2′,2′の厚みを決定する。
In the embodiments shown in FIGS. 1 to 5 described above, the inclined conductive lines 1E, 1E', and 1E' portions of the conductive line 1 constituting the inductance element L of the delay line are bent into a U-shape. The width of the bend is narrower, i.e. the parallel lines X-X, Y-Y and X'-
If the inner width of the portion corresponding to X', Y'-Y' is narrow and the non-magnetic insulating plates 2, 2', 2' are thin, the non-magnetic insulating plates 2, 2', 2', Since the positive coupling between the vertical conductive lines facing each other with 2' in between is increased, the inductance of the inductance element L is further increased, good characteristics can be obtained, and the external dimensions of the delay line can be miniaturized. The strength of the positive coupling between the vertical conductor lines is also related to the value of the degree of coupling a between the inductance elements in the adjacent sections in the equivalent circuit diagram shown in Figure 3, so the conductor lines can be folded according to the desired characteristics. Bending part and non-magnetic insulating plate 2,
Determine the thickness of 2' and 2'.

次に本発明の遅延線の応用例を説明する。 Next, an example of application of the delay line of the present invention will be explained.

第6図は本発明の遅延線を用いた可変遅延線を
示す部分正面図Aおよび部分側面図Bであり、第
7図は可変遅延線に用いるインダクタンス素子L
の導線路(第1図に示す導線路の変形例)1を示
すものである。
FIG. 6 is a partial front view A and a partial side view B showing a variable delay line using the delay line of the present invention, and FIG. 7 is an inductance element L used in the variable delay line.
This figure shows a conductive line (a modification of the conductive line shown in FIG. 1) 1.

第6図に示す可変遅延線に用いる導線路は、第
7図に示すように、傾斜導線路を形成する位置の
2本の平行線X−X,Y−Y間の内側にさらに形
成した相互距離の短かい2本の平行線U−U,V
−Vで挾まれる短い長さの縦導線路8を形成し、
この縦導線路8の前後(図中上下)において短い
傾斜導線路1Eが形成されて構成されている。
As shown in FIG. 7, the conductor line used in the variable delay line shown in FIG. Two parallel lines with a short distance U-U, V
- form a short length vertical conducting path 8 sandwiched by V,
A short inclined conductive line 1E is formed before and after this vertical conductive line 8 (upper and lower in the figure).

そして第6図に示すように導線路1のU−Uお
よびV−Vに相当する箇所でコ字状に折曲げら
れ、非磁性絶縁板2に、傾斜導線路1Eで挾まれ
た縦導線路8がその非磁性絶縁板2の側面に位置
するように接着されてインダクタンス素子Lが構
成されるとともに、非磁性絶縁板2の側面(図中
上面)の縦導線路8が可変遅延線の固定接点列と
して機能する。
As shown in FIG. 6, the vertical conductor line 1 is bent into a U-shape at locations corresponding to U-U and V-V, and is sandwiched between the inclined conductor lines 1E and the non-magnetic insulating plate 2. 8 is glued to the side surface of the non-magnetic insulating plate 2 to form the inductance element L, and the vertical conducting line 8 on the side surface (top surface in the figure) of the non-magnetic insulating plate 2 is used to fix the variable delay line. Functions as a contact row.

インダクタンス素子Lには長手方向にコンデン
サ電極5を覆つて形成された誘電体板4を介して
U字状に成形された接地電極6がコンデンサ電極
5と対向するように嵌合され、第2図に示したコ
ンデンサ素子Cと同様なコンデンサ素子Cが形成
され、インダクタンス素子Lとコンデンサ素子C
によつて切換用固定接点8列を有する可変遅延線
用の遅延線17が構成される。
A U-shaped ground electrode 6 is fitted into the inductance element L so as to face the capacitor electrode 5 through a dielectric plate 4 formed to cover the capacitor electrode 5 in the longitudinal direction. A capacitor element C similar to the capacitor element C shown in is formed, and an inductance element L and a capacitor element C are formed.
As a result, a variable delay line 17 having eight rows of fixed switching contacts is constructed.

そして非磁性絶縁板2は、可変遅延線の筐体1
4(一部を示す)内に、この筐体14の上部内面
に非磁性絶縁板2における固定接点8例側を対置
させるように収納されている。筐体14上部には
非磁性絶縁板2とその長手方向に沿つて対向する
摺動孔16が設けられ、筐体14上部内面には端
子電極13が設けられている。
The non-magnetic insulating plate 2 is connected to the housing 1 of the variable delay line.
4 (partially shown), the non-magnetic insulating plate 2 is housed in such a manner that the fixed contact 8 side of the non-magnetic insulating plate 2 is opposed to the upper inner surface of the housing 14. The upper part of the housing 14 is provided with a non-magnetic insulating plate 2 and a sliding hole 16 that faces the non-magnetic insulating plate 2 along its longitudinal direction, and the terminal electrode 13 is provided on the inner surface of the upper part of the housing 14.

この筐体14内には非磁性絶縁板2との間につ
まみ15を一体に設けた摺動体12が、そのつま
み15を摺動孔16から突出させるとともに端子
電極13に電気的に接触させ移動自在に配置され
ている。摺動体12の下面には、摺動体12を介
して筐体14内面の端子電極13と導通し、非磁
性絶縁板2の側面上のインダクタンス素子Lの固
定接点8列上を電気的に接触して摺動可能な弾性
を有する弓状の摺動子11が突設されている。す
なわち摺動体12の摺動に伴つて摺動子11が固
定接点8と筐体14の端子電極13とを順次接続
するようになつており、可変遅延線が構成されて
いる。第8図は遅延線の等価回路図である。
Inside this housing 14, a sliding body 12 with a knob 15 integrally provided between it and the non-magnetic insulating plate 2 is moved so that the knob 15 protrudes from a sliding hole 16 and comes into electrical contact with the terminal electrode 13. They are freely placed. The lower surface of the sliding body 12 is electrically connected to the terminal electrode 13 on the inner surface of the casing 14 through the sliding body 12, and electrically contacts eight rows of fixed contacts of the inductance element L on the side surface of the non-magnetic insulating plate 2. An arcuate slider 11 having elasticity that can be slid on is protruded. That is, as the sliding body 12 slides, the slider 11 sequentially connects the fixed contact 8 and the terminal electrode 13 of the housing 14, thereby forming a variable delay line. FIG. 8 is an equivalent circuit diagram of the delay line.

なお筐体14の端子電極13は、筐体底面の出
力端子(いずれも図示省略)に接続されている。
Note that the terminal electrode 13 of the casing 14 is connected to an output terminal (both not shown) on the bottom of the casing.

このように構成された可変遅延線は、第6図に
示す摺動子12を移動させてインダクタンス素子
Lの固定接点8を順次筐体14の端子電極13を
介して出力端子に導出することによつて、目的の
遅延時間を選択して任意の遅延特性が設定でき
る。しかも第2図の遅延線において説明したよう
にインダクタンス素子Lが、極めて高い周波数ま
で平担なインダクタンス特性を有するので、広い
周波数帯域に渡つて良好な可変遅延特性が得られ
る。さらに可変遅延線としての遅延時間選択スイ
ツチの固定接点8がインダクタンス素子Lの導線
路1の一部からなつているので、構造が簡単で極
めて小型となる。なお第7図に示す導線路1を第
2図および第5図に示す遅延線において実施する
ことができるし、第6図に示す可変遅延線は第5
図および第9図に示す構造のインダクタンス素子
で構成することも可能である。
In the variable delay line configured in this way, the fixed contact 8 of the inductance element L is sequentially led out to the output terminal via the terminal electrode 13 of the housing 14 by moving the slider 12 shown in FIG. Therefore, arbitrary delay characteristics can be set by selecting a desired delay time. Furthermore, as explained in connection with the delay line of FIG. 2, since the inductance element L has an inductance characteristic that is flat up to extremely high frequencies, good variable delay characteristics can be obtained over a wide frequency band. Further, since the fixed contact 8 of the delay time selection switch as a variable delay line is formed from a part of the conductive line 1 of the inductance element L, the structure is simple and extremely small. Note that the conductor line 1 shown in FIG. 7 can be implemented in the delay lines shown in FIGS. 2 and 5, and the variable delay line shown in FIG.
It is also possible to use an inductance element having the structure shown in FIG. 9 and FIG.

また上述の遅延線においては導線路1を非磁性
絶縁板2,2′に形成する構造を説明したが、こ
の導線路の設けられた非磁性絶縁板を磁性板にて
挾む構造を採用するならば、更にインダクタンス
が増加して遅延時間の向上に有用である。
Furthermore, in the above-mentioned delay line, the structure in which the conducting line 1 is formed between the non-magnetic insulating plates 2 and 2' has been explained, but a structure in which the non-magnetic insulating plate on which the conducting line is provided is sandwiched between magnetic plates is adopted. If so, the inductance further increases, which is useful for improving delay time.

以上説明したように本発明の遅延線は、インダ
クタンス素子と容量を組合せてなる遅延線におい
て、そのインダクタンス素子が、導線路を所定の
ピツチでジグザグ状かつ平行に複数回折返し、そ
の折返し部間において途中にその導線路を1ピツ
チ分ずらせる傾斜導線路を形成するとともに、1
ピツチずれた隣合う導線路が絶縁板を挾んで対向
するようにその導線路をコ字状に折曲げて形成さ
れてなるから、低い周波数帯から極めて高い周波
数帯まで広い周波数帯において立上り時間が早く
良好な遅延特性が得られるのみならず、極めて小
型となる利点を有する。
As explained above, the delay line of the present invention is a delay line formed by combining an inductance element and a capacitor, in which the inductance element folds the conductor line multiple times in a zigzag shape and in parallel at a predetermined pitch, and between the folded parts. In addition to forming an inclined conductor line that shifts the conductor line by one pitch in the middle,
Since the conductor lines are bent into a U-shape so that adjacent conductor lines with different pitches face each other with an insulating plate in between, the rise time is reduced over a wide frequency range from low frequency bands to extremely high frequency bands. It not only provides good delay characteristics quickly, but also has the advantage of being extremely compact.

本発明は上述の如き集中定数型遅延線に限ら
ず、分布定数型遅延線にも応用可能である。
The present invention is applicable not only to the lumped constant type delay line as described above but also to distributed constant type delay lines.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の遅延線に用いるインダクタン
ス素子の導線路を示す展開図、第2図A〜Cは本
発明の遅延線の一実施例を示す部分断面図、部分
正面図および側面図、第3図は第2図に示す遅延
線の等価回路図、第4図は本発明の遅延線の他の
実施例におけるインダクタンス素子の導線路を示
す展開図、第5図A,Bは第4図に示す導線路を
用いて構成した本発明の遅延線の他の実施例を示
す部分正面図(一部破断して示す)および側面
図、第6図は本発明の遅延線を用いた可変遅延線
を示す部分正面図および部分側面図、第7図は第
6図に示す可変遅延線に用いるインダクタンス素
子を示す展開図、第8図は第6図に示す可変遅延
線の等価回路図、第9図A〜Dは本発明の遅延線
のインダクタンス素子における導線路の折り曲げ
方法を示す概略図である。 1……導線路、1A〜1D……縦導線路、1
E,1E′……傾斜導線路、1F……横導線路、
2,2′……非磁性絶縁板、3……接続片、4…
…誘電体板、5……コンデンサ電極、6……接地
電極、7……接地板、8……固定接点、11……
摺動子、12……摺動体、13……端子電極、1
4……筐体、17……遅延線、L……インダクタ
ンス素子、C……コンデンサ素子。
FIG. 1 is a developed view showing a conducting path of an inductance element used in the delay line of the present invention, and FIGS. 2A to 2C are a partial sectional view, a partial front view, and a side view showing one embodiment of the delay line of the present invention. FIG. 3 is an equivalent circuit diagram of the delay line shown in FIG. A partial front view (partially cut away) and a side view showing another embodiment of the delay line of the present invention constructed using the conductive line shown in the figure, FIG. 7 is a developed view showing an inductance element used in the variable delay line shown in FIG. 6; FIG. 8 is an equivalent circuit diagram of the variable delay line shown in FIG. 6; FIGS. 9A to 9D are schematic diagrams showing a method of bending a conductive line in an inductance element of a delay line according to the present invention. 1...Conductor line, 1A to 1D...Vertical conductor line, 1
E, 1E'... Inclined conductor line, 1F... Horizontal conductor line,
2, 2'...Nonmagnetic insulating plate, 3...Connection piece, 4...
...Dielectric plate, 5... Capacitor electrode, 6... Ground electrode, 7... Ground plate, 8... Fixed contact, 11...
Slider, 12...Sliding body, 13...Terminal electrode, 1
4... Housing, 17... Delay line, L... Inductance element, C... Capacitor element.

Claims (1)

【特許請求の範囲】 1 インダクタンス素子と容量を組合せてなる集
中定数型の遅延線において、 前記インダクタンス素子は、導線路が所定のピ
ツチでジグザグ状かつ平行に複数回折返されると
ともに、前記導線路の折返し部間において前記各
導線路の途中でその導線路が1ピツチ分ずらさ
れ、1ピツチ離れた前記導線路が重なつて対向す
るように前記導線路の折返し部間において前記導
線路が絶縁板を挾んでコ字状に折曲げられてな
り、 前記容量は、前記インダクタンス素子における
前記導線路の各折返し部と接地電極間に形成され
てなる、 ことを特徴とする遅延線。 2 前記導線路の前記折返し部間に、1ピツチ分
ずらされた部分が複数形成され、前記導線路が複
数回折曲げられてなる特許請求の範囲第1項記載
の遅延線。 3 前記導線路に遅延時間選択スイツチ用固定接
点が形成され、これら固定接点によつて固定接点
列が形成されてなる特許請求の範囲第1項または
第2項記載の遅延線。
[Scope of Claims] 1. In a lumped constant type delay line formed by combining an inductance element and a capacitance, the inductance element has a conductive line that is folded back multiple times in a zigzag shape and in parallel at a predetermined pitch, and the conductive line is The conductive lines are shifted by one pitch in the middle of each of the conductive lines between the folded parts of the conductive lines, and the conductive lines are insulated between the folded parts of the conductive lines so that the conductive lines that are one pitch apart overlap and face each other. What is claimed is: 1. A delay line formed by sandwiching a plate and folded into a U-shape, wherein the capacitance is formed between each folded portion of the conductive line in the inductance element and a ground electrode. 2. The delay line according to claim 1, wherein a plurality of portions shifted by one pitch are formed between the folded portions of the conductive line, and the conductive line is bent a plurality of times. 3. The delay line according to claim 1 or 2, wherein fixed contacts for a delay time selection switch are formed on the conductive line, and these fixed contacts form a fixed contact row.
JP20121581A 1981-12-14 1981-12-14 Delay line Granted JPS58101513A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20121581A JPS58101513A (en) 1981-12-14 1981-12-14 Delay line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20121581A JPS58101513A (en) 1981-12-14 1981-12-14 Delay line

Publications (2)

Publication Number Publication Date
JPS58101513A JPS58101513A (en) 1983-06-16
JPS6118370B2 true JPS6118370B2 (en) 1986-05-12

Family

ID=16437247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20121581A Granted JPS58101513A (en) 1981-12-14 1981-12-14 Delay line

Country Status (1)

Country Link
JP (1) JPS58101513A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4758807A (en) * 1984-12-18 1988-07-19 Elmec Corporation Distributed constant type electromagnetic delay line

Also Published As

Publication number Publication date
JPS58101513A (en) 1983-06-16

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