JPS58101513A - Delay line - Google Patents

Delay line

Info

Publication number
JPS58101513A
JPS58101513A JP20121581A JP20121581A JPS58101513A JP S58101513 A JPS58101513 A JP S58101513A JP 20121581 A JP20121581 A JP 20121581A JP 20121581 A JP20121581 A JP 20121581A JP S58101513 A JPS58101513 A JP S58101513A
Authority
JP
Japan
Prior art keywords
line
delay line
inductance element
inductance
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20121581A
Other languages
Japanese (ja)
Other versions
JPS6118370B2 (en
Inventor
Kazuo Kametani
一雄 亀谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Elmec Corp
Original Assignee
Elmec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elmec Corp filed Critical Elmec Corp
Priority to JP20121581A priority Critical patent/JPS58101513A/en
Publication of JPS58101513A publication Critical patent/JPS58101513A/en
Publication of JPS6118370B2 publication Critical patent/JPS6118370B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/30Time-delay networks
    • H03H7/34Time-delay networks with lumped and distributed reactance

Landscapes

  • Coils Or Transformers For Communication (AREA)

Abstract

PURPOSE:To obtain a small-sized delay line usable in a very broad frequency, from low to high frequencies, by constituting an inductance element into a zigzag conductor line and folding back the broadwise direction of the line in parallel. CONSTITUTION:A conductor line consists of a conductor line 1 connected with zigzag folding and connecting pieces 3 projected from the folding sections of the conductor line and each folded section is formed in parallel so as to be ahead by one pitch P through a tilted jumper 1E. Currents flowing to opposing longitudinal conductors 1A, 1C and 1B, 1D are the same direction and those flowing between adjacent conductors 1A, 1B and 1C, 1D are opposite. Since magnetic fluxes phi1, phi2 form a short closed loop with two longitudinal conductors by clipping a nonmagnetic substance insulating plate 2, an inductance element L has the flat inductance characteristics up to a very high frequency, and through the positive interlinking of the phi1, phi2, a flat high inductance can be obtained even in an ultra high frequency band.

Description

【発明の詳細な説明】 本発明は、インダクタンス素子と容量を組合せてなる遅
延線に係り、低周波から極めて高い高周波に至るまでの
非常に広い周波数帯域の使用に適する遅延線に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay line formed by combining an inductance element and a capacitance, and relates to a delay line suitable for use in a very wide frequency band from low frequencies to extremely high frequencies.

従来、立上り時間の速い、例えば立上り時間がI ns
以下の遅延線としては、同軸ケーブルを目的の遅延時間
となる長さに切ったものや、メアンダーライン等の分布
定数回路の一種と考えられるものが提案されている。し
かし前者は形状が大きく端末処理が面倒であるし、後者
は形状も大きく高価であるうえ特性が良好でないという
理由から、いずれも実用化されていな啼。
Conventionally, the rise time is fast, for example, the rise time is Ins.
As the following delay lines, a coaxial cable cut to a length that provides the desired delay time, and a type of distributed constant circuit such as a meander line have been proposed. However, the former is large and requires troublesome terminal processing, and the latter is large and expensive, and its characteristics are not good, so neither has been put into practical use.

また小型の遅延線としては、インダクタ素子りと容量C
を用いた集中定数型遅延線が適している。
In addition, as a small delay line, an inductor element and a capacitance C
A lumped constant delay line using

ところがこの遅延線は、周波数帯域が高くなるとインダ
クタンス素子が周波数特性を持つうえインダクタンス素
子のQも低下するため、遅延特性と振幅特性が共に劣化
して立上り時間がInsns以高速遅延1fMKは使用
困難である。
However, in this delay line, as the frequency band increases, the inductance element has frequency characteristics and the Q of the inductance element also decreases, so both the delay and amplitude characteristics deteriorate, making it difficult to use a 1fMK with a high-speed delay of 1fMK when the rise time is longer than Insns. be.

本発明は以上の欠点を解消するためになされたもので、
低周波から高周波まで極めて広い周波数帯域での使用が
可能な小型の遅延線の提供を目的とする。
The present invention has been made to solve the above-mentioned drawbacks.
The purpose of this invention is to provide a compact delay line that can be used in an extremely wide frequency band from low frequencies to high frequencies.

以下本発明の詳細を図面を参照して説明する。The details of the present invention will be explained below with reference to the drawings.

第1図および第2図は本発明の遅延線の一実施例を示す
図であり、特に第1図は本発明の遅延線を構成するイン
ダクタンス素子りの導線路1を示す展開図である0第1
図においてインダクタンス素子の導線路1は、ジグザグ
状に折返して連結された導線路1と、この導線路におけ
る折返し部から突設される接続片3とからなっており、
個々の各導線路は、幅W方向中央部すなわち導線路1上
の平行線x−xとY−Y間の領域において平行な傾斜導
線路1Eを有し、縦導線路IA、1B。
1 and 2 are views showing an embodiment of the delay line of the present invention, and in particular, FIG. 1st
In the figure, the conductive line 1 of the inductance element consists of a conductive line 1 which is folded in a zigzag shape and connected together, and a connecting piece 3 which projects from the folded part of the conductive line.
Each individual conductive line has a parallel inclined conductive line 1E in the center part in the width W direction, that is, a region between parallel lines xx and Y-Y on the conductive line 1, and vertical conductive lines IA, 1B.

IC,ID・・・に分割されている。そのため各導線路
1は、傾斜導線路1Eを至て1ピッチP先行するよう平
行に形成されている。つまり各傾斜導線路1Eの前後(
図中上下)が、1ピツチずれている。なお、導線路1の
幅方向wh、各導線路1の延長線方向である。
It is divided into IC, ID, etc. Therefore, each conductive line 1 is formed in parallel so as to precede the inclined conductive line 1E by one pitch P. In other words, the front and back of each inclined conductor path 1E (
(top and bottom in the figure) are shifted by one pitch. Note that the width direction wh of the conductive line 1 is the direction of the extension line of each conductive line 1.

そしてこのように形成された導線路1が、導線路上の平
行1x−xおよびY−Yでコ字状に折曲げられ、ガラス
や合成樹脂製の細長い非磁性絶縁板2に接着され、第2
図に示すようなインダクタンス素子りを構成している。
The conductive line 1 thus formed is bent into a U-shape along the parallel lines 1x-x and Y-Y on the conductive line, and is adhered to a long and thin non-magnetic insulating plate 2 made of glass or synthetic resin.
It constitutes an inductance element as shown in the figure.

インダクタンス素子しは、非磁性絶縁板2の一方の側面
に傾斜導線路1Eを、対向する主表面に傾斜導線路1E
の前後の縦導線路IA、IB、IC,ID・・・を接着
されるとともに、他方の側面から接続片3が突出してい
る。
The inductance element has an inclined conductive line 1E on one side surface of the non-magnetic insulating plate 2, and an inclined conductive line 1E on the opposite main surface.
The front and rear vertical conducting lines IA, IB, IC, ID, . . . are bonded together, and a connecting piece 3 protrudes from the other side.

細長い絶縁板2の他方の側面には、接地室&6を挾んで
配置した誘電体板4の対向表面にコンデンサ電極5を設
けて構成されたコンデンサ素子Cが、インダクタンス素
子りの接続片3とコンデンサ電極6を接続して固定され
ている。そしてインダクタンス素子りの各縦導線路IA
、1B、IC。
On the other side of the elongated insulating plate 2, a capacitor element C is formed by providing a capacitor electrode 5 on the opposite surface of a dielectric plate 4 with a ground chamber &6 in between. The electrode 6 is connected and fixed. And each vertical conducting line IA with an inductance element
, 1B, IC.

1D・・・と、導線路の接続片3と接地電極6間に形成
されるコンデンサ素子Cとによって第3図に示すように
集中定数型遅延線が形成される。
1D... and the capacitor element C formed between the connecting piece 3 of the conducting line and the ground electrode 6, a lumped constant delay line is formed as shown in FIG.

このように構成した本発明の遅延線は、インダクタンス
素子りの導線路1のうちの任意の近接する4本の縦導線
路、例えばIA、  1B、  IC。
The delay line of the present invention configured in this manner includes any four adjacent longitudinal conductive lines of the conductive line 1 including the inductance element, for example, IA, 1B, and IC.

1Dについて考察すると、第2図Bに示す矢印方向に流
れる電流によって同図Aのような磁束Φ1およびΦ2が
生ずる。これらの磁束Φ、およびΦ2は、非磁性絶縁板
20対向する主面表土の対向する縦導線路1AとIC,
および1Bと1Dを流れる電流がそれぞれ同方向となる
ので、それぞれ正の結合となって形成されるものである
。一方、それぞれの主表面における隣り合う縦導線路I
A(!:1日および1Cと1D間は負の結合となるので
磁束Φ1およびΦ2はそれぞれ独立の短かい磁束ループ
を形成する。これらの関係は任意の近接する4本の縦導
線路のどこを選んでも成立する。
Considering 1D, magnetic fluxes Φ1 and Φ2 as shown in FIG. 2A are generated by the current flowing in the direction of the arrow shown in FIG. 2B. These magnetic fluxes Φ and Φ2 are distributed between the vertical conductive lines 1A and IC on the main surface topsoil facing the non-magnetic insulating plate 20,
Since the currents flowing through 1B and 1D are in the same direction, a positive bond is formed. On the other hand, adjacent longitudinal conductive lines I on each main surface
A(!: Since there is a negative coupling between 1C and 1D, the magnetic fluxes Φ1 and Φ2 form independent short magnetic flux loops. It holds true even if you choose .

このよう、に磁束Φ1およびΦ2が非磁性絶縁板2を挾
んで2つの縦導線路による短かい閉ループを形成するの
で、インダクタンス素子りは非常に高い周波数まで平担
なインダクタンス特性を有゛シ、かつ磁束Φ1およびΦ
2が正の結合によって構成されるのでインダクタンスが
増加し、極めて高い高周波、例えばIGHz以上の超高
周波帯域においても十分高インダクタンスが平担に得ら
れる。その結果、超高周波における超高速遅延線が得ら
れる。特にこの点は、インダクタンス素子のインダクタ
ンスを向上させるフェライト等の磁性体が、超高周波帯
域で導磁率が低下するとともに損失が大きくなりボビン
として使用できない状況下にあっても、非磁性絶縁板2
を用いて高インダクタンスが得られるので、極めて有用
である。
In this way, the magnetic fluxes Φ1 and Φ2 sandwich the non-magnetic insulating plate 2 and form a short closed loop with two vertical conducting paths, so the inductance element has flat inductance characteristics up to very high frequencies. and magnetic flux Φ1 and Φ
2 is constituted by positive coupling, the inductance increases, and a sufficiently high inductance can be easily obtained even at extremely high frequencies, for example, in ultra-high frequency bands of IGHz or higher. As a result, an ultra-fast delay line at ultra-high frequencies is obtained. In particular, this point is important because magnetic materials such as ferrite, which improve the inductance of inductance elements, have lower magnetic permeability and higher losses in ultra-high frequency bands, making it impossible to use them as bobbins.
It is extremely useful because a high inductance can be obtained using this method.

また本発明の遅延Sは、インダクタンス素子りにおいて
、第3図の等価回路図における互に隣り合う区間に相当
する導線路I A、  I C,I B、IDが正の結
合となって、第3図の等価回路図で示すように誘導m型
の集中定数型遅延線を構成し、この点からも遅延特性を
改善している。
Furthermore, the delay S of the present invention is caused by positive coupling between conductive lines I A, I C, I B, and ID corresponding to mutually adjacent sections in the equivalent circuit diagram of FIG. 3 in the inductance element. As shown in the equivalent circuit diagram of FIG. 3, an inductive m-type lumped constant delay line is constructed, and the delay characteristics are improved from this point as well.

第4図および第5図は1本発明の遅延線の他の実施例を
示す図である。第4図はインダクタンス素子の展開図で
あり、導線路1は折返し幅Wを上述の第1図の折返し幅
よりも長く構成してなり、折返し幅W方向中央部の2本
の平行IfsX−X。
FIGS. 4 and 5 are diagrams showing other embodiments of the delay line of the present invention. FIG. 4 is a developed view of the inductance element, and the conductive line 1 has a folded width W longer than the folded width shown in FIG. .

Y−Y間に相当する位置に傾斜導線路1Eを有するとと
もに、この傾斜導線路1Eと両折返し部IF、IF(図
中上端および下端)の間に各々2本の平行mX’−X’
、  Y’−Y’に相当する間で傾斜導線路I E’、
  I E’が形成されている。しかも面傾斜導線路I
 E’、  I E’は、中央の傾斜導線路1Eと同様
にその前後の導線路が1ピツチ分だけ中央の傾斜導線路
1Eに対し逆方向にずれるように形成されている。すな
わち縦導線路1は、平行1x−xとY−Yに相当する間
に形成される傾斜導線路1Eを基準とすると、その前後
(図中上下)において傾斜導線路1Eによってずれた折
返しピッチ1分を、平行線X’ −X’、  Y’ −
Y’に相当する間に形成される傾斜導線路I E’、 
 I E’によって逆方向に尿すように構成されている
It has an inclined conducting line 1E at a position corresponding to between Y and Y, and two parallel lines mX'-X' are provided between this inclined conducting line 1E and both folded parts IF and IF (upper end and lower end in the figure).
, an inclined conductor line IE' between Y'-Y',
IE' is formed. Moreover, the plane inclined conductor line I
E' and IE' are formed so that the conductive lines before and after the central inclined conductive line 1E are shifted by one pitch in the opposite direction with respect to the central inclined conductive line 1E. In other words, the vertical conducting line 1 has a folding pitch 1 shifted by the inclined conducting line 1E in front and back (up and down in the figure), with the inclined conducting line 1E formed between parallel lines 1x-x and Y-Y as a reference. minutes, parallel lines X' - X', Y' -
Inclined conductive line IE' formed between corresponding to Y',
IE' is configured to urinate in the opposite direction.

また導線路における折返し部たる横導線路I F。Also, a horizontal conducting line IF is a folded part in the conducting line.

1Fは・縦導線路よりも導線路の幅が広なっており、後
述するコンデンサ電極6,6として機能するO 第5図は、このような第4図に示す導線路1を用いた遅
延線を示すものである。
In 1F, the conductor line is wider than the vertical conductor line, and functions as capacitor electrodes 6, 6, which will be described later. This shows that.

符号2.2′は細長い非磁性絶縁板であり、上述の第2
図の非磁性絶縁板2と同材質で厚味が僅かに薄くなって
いる。そして前記第4図に示す導線路1が平行線IX 
 X、  Y  Yに相当する箇所で平行かつコ字状′
に折曲げられて非磁性絶縁板2に接着され、かつ平行m
X’−X’、  Y’−Y’に相当する箇所が平行にX
−X、Y−Y相当箇所とは逆方向にコ字状に折曲げられ
、非磁性絶縁板2’、  2’に接着されている。即ち
導線路1がクランク状に折曲げられ、3枚の非磁性絶縁
板2. 2’、  2’の対向する主表面に縦導線路が
、また傾斜導線路IE、IE’。
Reference numeral 2.2' is an elongated non-magnetic insulating plate, which is similar to the above-mentioned second
It is made of the same material as the non-magnetic insulating plate 2 shown in the figure, but is slightly thinner. The conductive line 1 shown in FIG. 4 is the parallel line IX.
X, Y Parallel and U-shaped at the location corresponding to Y'
It is bent to the non-magnetic insulating plate 2 and is
The points corresponding to X'-X' and Y'-Y' are parallel to
It is bent into a U-shape in the opposite direction to the locations corresponding to -X and YY, and is bonded to the non-magnetic insulating plates 2', 2'. That is, a conductive line 1 is bent into a crank shape, and three non-magnetic insulating plates 2. On the opposing main surfaces of 2' and 2' are longitudinal conductive lines, and inclined conductive lines IE and IE'.

I E’が側面に配置されるよう正着されてインダクタ
ンス素子りを構成している。なお導線路のコンデンサ電
極5,6たる横導線路IF、IFは非磁性絶縁板2’、
  2’の同一方向(図中下方)に位置している。
IE' is properly attached to the side surface to form an inductance element. The horizontal conducting lines IF and IF, which are the capacitor electrodes 5 and 6 of the conducting lines, are non-magnetic insulating plates 2',
2' in the same direction (lower in the figure).

インダクタンス素子りの両側の非磁性絶縁板2゜2′の
長手方向下部には、コンデンサ電極5,6を覆って誘電
体板4,4が形成され、この誘電体板4.4には横断面
U字状の接地板7が非磁性絶縁板2’、  2. 2’
を挾むように嵌合されてコンデンサ素子Cが形成、配置
され、集中定数型遅延線が構成されている〇 このように構成された遅延線は、第2図に示す遅延線と
同様に、非磁性絶縁板2’、  2. 2’を介して対
向する縦導線路が1ピツチづつずれているので、対向す
る縦導線路により発生する磁束がすべて正の結合となり
、一方同一平面上で隣り合う縦導線路により発生する磁
束が負の結合となって、磁束が短いループを形成する0
そのため、インダク。タンス素子りが非常に高い周波数
帯域まで平担で高いインダクタンスを示す。しかも正結
合する導線路の数が増加することにより、インダクタン
ス素子りのインダクタンスが大巾に高くなる0その結果
、低い胸波数から超高周波までの広い周波数帯にて立上
り時間の速い遅延線が得られるOまたジグザグ状の導線
路1の折返し幅Wを広くして傾斜導線路の数を増加させ
て、コ字状に折曲げる箇所を増加させるならば、非磁性
絶縁板を挾んで正結合する縦導線路の数が増えるので、
インダクタンス素子りのインダクタンスを急増させるこ
とが可能となる。なお導線路を折曲げる方向は、第6図
に示す例のほか第9図に示す如きものが考えられる。要
は、ピンチをずらせて非磁性絶縁板を挾んで縦導線路を
正結合状態で対向させればよく、傾斜導線路の数や折曲
げる数は目的とする遅延特性に合せて任意に決定すれば
よい。
Dielectric plates 4, 4 are formed at the bottom in the longitudinal direction of the non-magnetic insulating plates 2゜2' on both sides of the inductance element, covering the capacitor electrodes 5, 6. The U-shaped ground plate 7 is a non-magnetic insulating plate 2'; 2. 2'
A capacitor element C is formed and arranged so as to sandwich the , and a lumped constant type delay line is constructed.The delay line configured in this way is made of non-magnetic material, similar to the delay line shown in FIG. Insulating plate 2', 2. Since the vertical conductive lines facing each other via 2' are shifted by one pitch, the magnetic flux generated by the opposing vertical conductive lines is all positive coupling, while the magnetic flux generated by the adjacent vertical conductive lines on the same plane is 0 where the magnetic flux forms a short loop due to negative coupling.
Therefore, induct. The transducer element exhibits high inductance evenly up to very high frequency bands. Furthermore, as the number of positively coupled conductive lines increases, the inductance of the inductance element increases significantly.As a result, a delay line with a fast rise time can be obtained in a wide frequency band from low chest wave numbers to very high frequencies. In addition, if the folding width W of the zigzag-shaped conductor line 1 is increased to increase the number of inclined conductor lines and the number of parts to be bent in a U-shape is increased, positive coupling is performed by sandwiching a nonmagnetic insulating plate. As the number of vertical conducting lines increases,
It becomes possible to rapidly increase the inductance of the inductance element. In addition to the example shown in FIG. 6, the direction in which the conducting path is bent may be as shown in FIG. 9. In short, all you have to do is shift the pinch and sandwich the nonmagnetic insulating plates so that the vertical conductor lines face each other in a positive coupling state.The number of inclined conductor lines and the number of bends can be arbitrarily determined according to the desired delay characteristics. Bye.

さらに第6図に示す遅延線は、コンデンサ素子Cの一方
のコンデンサ電極5. 5がインダクタンス素子りの導
線路1における折返し部IF、IFからなっているので
、遅延線を構成するためのインダクタンス素子りとコン
デンサ素子Cとの半田付は等の必要がなくなる。したが
って接続不良が解消して信頼性が向上し、接続工程の省
略から組立工数も減少してコストの大巾低減を図ること
が可能となる。
Further, the delay line shown in FIG. 6 is connected to one capacitor electrode 5. Since 5 consists of folded portions IF and IF in the conductive line 1 of the inductance element, there is no need for soldering between the inductance element and the capacitor element C for constructing the delay line. Therefore, connection failures are eliminated, reliability is improved, and the number of assembly steps is reduced due to the omission of connection steps, making it possible to significantly reduce costs.

なお第6図に示す遅延線においても第2図の遅延線と同
様に誘導m型遅延線が得られるので、遅延特性が極めて
良好である◇ 上述の第1図ないし第6図に示す実施例において、遅延
線のインダクタンス素子りを構成する溝絶縁板2. 2
’、  2’の厚みも薄いものを用いる場合には、非磁
性絶縁板2. 2’、  2’を挾んで対向する縦導線
路間の正の結合が増加するので、インダクタンス素子り
のインダクタンスがより増加して良好な特性が得られる
とともに、遅延線の外形寸法を超小型化できる。なお縦
導線路間の正の結合の強さは、第3図に示す等価回路図
における隣区間のインダクタンス素子間の結合度aの値
とも関係するので、目的の特性に合せて導線路を折曲げ
る箇所および非磁性絶縁板2. 2’、  2’の厚み
を決定する。
Note that the delay line shown in FIG. 6 also has an inductive m-type delay line similar to the delay line shown in FIG. 2, so the delay characteristics are extremely good. In , the groove insulating plate 2 constituting the inductance element of the delay line. 2
When using thin plates 2 and 2, non-magnetic insulating plates 2 and 2 are used. Since the positive coupling between the vertical conductor lines facing each other with 2' and 2' in between increases, the inductance of the inductance element increases further, resulting in good characteristics, and the external dimensions of the delay line can be made ultra-small. can. The strength of the positive coupling between the vertical conductor lines is also related to the value of the degree of coupling a between the inductance elements in the adjacent sections in the equivalent circuit diagram shown in Figure 3, so the conductor lines can be folded according to the desired characteristics. Bending area and non-magnetic insulating plate 2. Determine the thickness of 2' and 2'.

次に本発明の遅延線の応用例を説明する〇第6図は本発
明の遅延線を用いた可変遅延線を示す部分正面図Aおよ
び部分側面図8であり、第7図は可変遅延線に用いるイ
ンダクタンス素子りの導線路(第1図に示す導線路の変
形例)1を示すものである。
Next, an application example of the delay line of the present invention will be explained.〇Figure 6 is a partial front view A and a partial side view 8 showing a variable delay line using the delay line of the present invention, and Figure 7 is a partial front view A and a partial side view 8 of a variable delay line using the delay line of the present invention. This figure shows a conductive line (a modification of the conductive line shown in FIG. 1) 1 having an inductance element used in the present invention.

第6図に示す可変遅延線に用いる導線路は、第7図に示
すように、傾斜導線路を形成する位置の2本の平行#X
−X、Y−Y間の内側にさらに形成した相互距離の短か
い2本の平行線U−U、V−Vで挾まれる短い長さの縦
導線路8を形成し、この縦導線路8の前後(図中上下)
において短い傾斜導線路1Eが形成されて構成されてい
る。
The conductive line used for the variable delay line shown in Fig. 6 consists of two parallel #X
A short length vertical conductive line 8 is formed between two parallel lines U-U and V-V with a short mutual distance formed further inside between -X and Y-Y, and this vertical conductive line Before and after 8 (top and bottom in the diagram)
A short inclined conductive path 1E is formed at.

そして第6図に示すように導線路1のU−Uおよびv−
■に相当する箇所でコ字状に折曲げられ、非磁性絶縁板
2に、傾斜導線路1Eで挾まれた縦導線路8がその非磁
性絶縁板2の側面に位置するように接着されてインダク
タンス素子りが*aされるとともに、非磁性絶縁板2の
側面(図中上面)の縦導線路8が可変遅延線の固定接点
列として機能する。
Then, as shown in FIG.
It is bent into a U-shape at the location corresponding to (2), and is glued to the non-magnetic insulating plate 2 so that the vertical conductive line 8 sandwiched by the inclined conductive line 1E is positioned on the side surface of the non-magnetic insulating plate 2. The inductance element is increased *a, and the vertical conductive line 8 on the side surface (upper surface in the figure) of the nonmagnetic insulating plate 2 functions as a fixed contact array of the variable delay line.

字状に成形された接−他電極6がフンデンサ電極5と対
向するように嵌合され、第2図に示したコンデンサ素子
Cと同様なコンデンサ素子Cが形成され、インダクタン
ス素子りとコンデンサ素子Cによって切換用固定接点8
列を有する可変遅延線用の遅延@17が構成される。
The contact electrode 6 formed in the shape of a letter is fitted so as to face the capacitor electrode 5, and a capacitor element C similar to the capacitor element C shown in FIG. 2 is formed, and the inductance element and the capacitor element C are Fixed contact 8 for switching by
A delay @17 is configured for a variable delay line with columns.

そして非磁性絶縁板2は、可変遅延線の筐体14(一部
を示す)内に・この筐体14の上部内面に非磁性絶縁板
2における固定接点8列側を対置させるように収納され
ている。筐体14上部には非磁性絶縁板2とその長手方
向に沿って対向する摺動孔16が設けられ、筐体14上
部内面には端子電極13が設けられている。
The non-magnetic insulating plate 2 is housed in a housing 14 (partially shown) of the variable delay line, with the 8 rows of fixed contacts of the non-magnetic insulating plate 2 facing against the inner surface of the upper part of the housing 14. ing. A non-magnetic insulating plate 2 and a sliding hole 16 facing each other along the longitudinal direction are provided on the upper part of the casing 14, and a terminal electrode 13 is provided on the inner surface of the upper part of the casing 14.

この筐体14内には非磁性絶縁板2との間につまみ16
を一体に設けた摺動体12が、そのっまみ16を摺動孔
16から突出させるとともに端子電極13に電気的に接
触させ移動自在に配置されている@摺動体12の下面に
は・摺動体12を介して筐体14内面の端子電極13と
導通し、非磁性Mm板2の側面上のインダクタンス素子
りの固定接点8列上を電気的に接触して摺動可能な弾性
を有する弓状の摺動子11が突設されている。すなわち
摺動体12の摺動に伴って摺動子11が固定接点8と筐
体14の端子電極13とを順次接続するようになってお
り、可変遅延線が構成されている。第8図は可変遅延線
の等価回路図である。
Inside this housing 14 there is a knob 16 between it and the non-magnetic insulating plate 2.
A sliding body 12 is provided with a knob 16 protruding from the sliding hole 16 and is movably arranged in electrical contact with the terminal electrode 13. 12, and has an elastic arcuate shape that is electrically connected to the terminal electrode 13 on the inner surface of the casing 14 and slidable in electrical contact with the 8 rows of fixed contacts of the inductance element on the side surface of the non-magnetic Mm plate 2. A slider 11 is provided protrudingly. That is, as the sliding body 12 slides, the slider 11 sequentially connects the fixed contact 8 and the terminal electrode 13 of the housing 14, thereby forming a variable delay line. FIG. 8 is an equivalent circuit diagram of the variable delay line.

なお筐体14の端子電極13は、筐体底面の出力端子(
いずれも図示省略)K接続されている。
Note that the terminal electrode 13 of the housing 14 is connected to the output terminal (
(all not shown) K-connected.

このように構成された可変遅延線は、第6図に示す摺動
子12を移動させてインダクタンス素子りの固定接点8
を順次筐体14の端子電極13を介して出力端子に導出
することによって、目的の遅延時間を選択して任意の遅
延特性が設定できる。
The variable delay line configured in this way is constructed by moving the slider 12 shown in FIG.
By sequentially leading out the signals to the output terminals via the terminal electrodes 13 of the housing 14, an arbitrary delay characteristic can be set by selecting a desired delay time.

しかも第2図の遅延線において説明したようにインダク
タンス素子りが、極めて高い周波数まで平担なインダク
タンス特性を有するので、広い周波数帯域に渡って良好
な可変遅延特性が得られる。
Moreover, as explained in connection with the delay line of FIG. 2, the inductance element has a flat inductance characteristic up to extremely high frequencies, so that good variable delay characteristics can be obtained over a wide frequency band.

さらに可変遅延線としての、優延時間選択スイッチの固
定接点8がインダクタンス素子りの導線路1の一部から
なっているので、構造が簡単で極めて小型となる。なお
第7図に示す導線路1を第2図および第6図に示す遅延
線において実施することができるし、第6図に示す可変
遅延線は第5図および第9図に示す構造のインダクタン
ス素子で構成することも可能である。
Furthermore, since the fixed contact 8 of the preferential time selection switch, which serves as a variable delay line, is made up of a part of the conductive line 1 having an inductance element, the structure is simple and extremely compact. Note that the conductor line 1 shown in FIG. 7 can be implemented as a delay line shown in FIGS. 2 and 6, and the variable delay line shown in FIG. It is also possible to configure it with elements.

また上述の遅延線においては導線路1を非磁性絶縁板2
,2′に形成する構造を説明したが、この導線路の設け
られた非磁性絶縁板を磁性板にて挾む構造を採用するな
らば、更にインダクタンスが増加して遅延時間の向上に
有用である。
In addition, in the above-mentioned delay line, the conducting line 1 is connected to the non-magnetic insulating plate 2.
, 2' has been explained, but if a structure is adopted in which the non-magnetic insulating plate provided with the conductive path is sandwiched between magnetic plates, the inductance will further increase and it will be useful for improving the delay time. be.

以上説明したように本発明の遅延線は、インダクタンス
素子と容量を組合せてなる遅延線において、インダクタ
ンス素子が、ジグザグ状の導線路の幅方向を平行にずら
せて折り返して構成されてなることから、低い周波数帯
から極めて高い周波数帯まで広い周波数帯において立上
り時間が早く良好な遅延特性が得られるのみならず、極
めて小型となる利点を有する。
As explained above, the delay line of the present invention is a delay line that is a combination of an inductance element and a capacitance, in which the inductance element is constructed by shifting the width direction of a zigzag conductive path in parallel and folding it back. It not only provides a fast rise time and good delay characteristics in a wide frequency band from low frequency bands to extremely high frequency bands, but also has the advantage of being extremely compact.

本発明は上述の如き集中定数型遅延線に限らず、分布定
数型遅延線にも応用可能である。
The present invention is applicable not only to the lumped constant type delay line as described above but also to distributed constant type delay lines.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の遅延線に用いるインダクタンス素子の
導線路を示す展開図、第2図A−Cは本発明の遅延線の
一実施例を示す部分断面図、部分正面図および側面図、
第3図は第2図に示す遅延線の等価回路図、第4図は本
発明の遅延線の他の実施例におけるインダクタンス素子
の導線路を示す展開図、第5図A、  Bは第4図に示
す導線路を用いて構成した本発明の遅延線の他の実施例
を示す部分正面図(一部破断して示す)および側面図、
第6図は本発明の遅延線を用いた可変遅延線を示す部分
正面図および部分側面図、第7図は第6図に示す可変遅
延線に用いるインダクタンス素子を示す展開図、第8図
は第6図に示す可変遅延線の等価回路図、第9図A−D
H本発明の遅延線のインダクタンス素子に□おける導線
路の折り曲げ方法を示す概略図である。 1・・・・・・導線路、1A〜10・・・・・・縦導梅
路、I E。 1 E’・・・・・・傾斜導線路、1F・・・・・・横
導線路、2゜2′・・・・・・非磁性絶縁板、3・・・
・・・接続片、4・・・・・・誘電体板、6・・・・・
・コンデンサ電極、6・・・・・・接地電極、7・・・
・・・接地板、8・・・・・・固定接点、11・・・・
・・摺動子、12・・・・・・摺動体、13・・・・・
・端子電極、14・・・・・・筐体、17・・・・・・
遅延線、L・・・・・・インダクタンス素子、C・・・
・・・コンデンサ素子特許出願人 エルメック株式会社 ヤ 1 図 ヤ 2  回 (A) (B)           (C) ヤ 3 図 ヤ4図 ヤ 5  図 (A)            CB)ZZ’lP  
コ 4Cj   SL       Cl315   
リヤ 7 図 ヤ 6 図 ヤ 8 図 ヤ (A)      (日)       (C)(0)
FIG. 1 is a developed view showing a conducting path of an inductance element used in the delay line of the present invention, and FIGS. 2A-2C are a partial sectional view, a partial front view, and a side view showing an embodiment of the delay line of the present invention.
FIG. 3 is an equivalent circuit diagram of the delay line shown in FIG. 2, FIG. 4 is a developed diagram showing a conductive path of an inductance element in another embodiment of the delay line of the present invention, and FIGS. A partial front view (partially cut away) and side view showing another embodiment of the delay line of the present invention configured using the conductive line shown in the figure,
FIG. 6 is a partial front view and a partial side view showing a variable delay line using the delay line of the present invention, FIG. 7 is a developed view showing an inductance element used in the variable delay line shown in FIG. 6, and FIG. Equivalent circuit diagram of the variable delay line shown in Figure 6, Figures 9A-D
H is a schematic diagram showing a method of bending a conductive line in the inductance element of a delay line of the present invention. 1... Conductor path, 1A to 10... Longitudinal Umeji, IE. 1 E'... Inclined conductor line, 1F... Horizontal conductor line, 2゜2'... Nonmagnetic insulating plate, 3...
... Connection piece, 4 ... Dielectric plate, 6 ...
・Capacitor electrode, 6... Ground electrode, 7...
...Ground plate, 8...Fixed contact, 11...
...Slider, 12...Sliding body, 13...
・Terminal electrode, 14... Housing, 17...
Delay line, L...Inductance element, C...
...Capacitor element patent applicant Elmec Co., Ltd. 1 Figure 2 times (A) (B) (C) 3 Figure 4 Figure 5 Figure (A) CB) ZZ'lP
Ko 4Cj SL Cl315
Riya 7 Figure ya 6 Figure ya 8 Figure ya (A) (Japanese) (C) (0)

Claims (4)

【特許請求の範囲】[Claims] (1)  インダクタンス素子と容量を組合せてなる遅
延線において、前記インダクタンス素子が、ジグザグ状
の導線路の幅方向を平行にずらせて折り返して構成され
てなることを特徴とする遅延線。
(1) A delay line formed by combining an inductance element and a capacitor, characterized in that the inductance element is constructed by folding back a zigzag-shaped conductive line with its width direction shifted in parallel.
(2)  インダクタンス素子が、ジグザグ状の各導線
路の幅方向の途中に形成された傾斜導線路によってこの
傾斜導電路の前後における導線路を折り返し1ピッチ分
ずらせて構成されるとともに、前記傾斜導線路において
折り返されてなることを特徴とする特許請求の範囲第1
項記載の遅延線。
(2) The inductance element is configured by an inclined conductive path formed halfway in the width direction of each zigzag conductive path, and the conductive paths at the front and rear of the inclined conductive path are folded back and shifted by one pitch, and the inclined conductive path is shifted by one pitch. Claim 1 characterized in that it is folded back at the road.
Delay line as described in section.
(3)インダクタンス素子が、ジグザグ状導線路に形成
された複数の傾斜導線路において複数回折り返されてな
ることを特徴とする特許請求の範囲第2項記載の遅延線
(3) The delay line according to claim 2, wherein the inductance element is folded back multiple times in a plurality of inclined conductive paths formed in a zigzag conductive path.
(4)  インダクタンス素子が、ジグザグ状導線路に
形成された傾斜導電路を遅延時間選択スイッチ用固定接
点列としてなることを特徴とする特許請求の範囲第2項
または第3項記載の遅延様。
(4) The delay mode according to claim 2 or 3, wherein the inductance element is a slanted conductive path formed in a zigzag conductive path as a fixed contact array for a delay time selection switch.
JP20121581A 1981-12-14 1981-12-14 Delay line Granted JPS58101513A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20121581A JPS58101513A (en) 1981-12-14 1981-12-14 Delay line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20121581A JPS58101513A (en) 1981-12-14 1981-12-14 Delay line

Publications (2)

Publication Number Publication Date
JPS58101513A true JPS58101513A (en) 1983-06-16
JPS6118370B2 JPS6118370B2 (en) 1986-05-12

Family

ID=16437247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20121581A Granted JPS58101513A (en) 1981-12-14 1981-12-14 Delay line

Country Status (1)

Country Link
JP (1) JPS58101513A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4758807A (en) * 1984-12-18 1988-07-19 Elmec Corporation Distributed constant type electromagnetic delay line

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4758807A (en) * 1984-12-18 1988-07-19 Elmec Corporation Distributed constant type electromagnetic delay line

Also Published As

Publication number Publication date
JPS6118370B2 (en) 1986-05-12

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