JPS6117633Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a counter circuit that causes an up-down counter to count according to a forward count command and a subtraction command.

Copying machines use counters to count the number of copies, and methods for setting the number of copies on this counter include a mechanical dial setting method, a numeric keypad method, a thumbwheel method, and an up-down method. Conventionally, in this up-down method, as shown in Figure 1, when the forward count switch is pressed to give a forward count command, the preset terminal PR of flip-flop _U1 goes to a high potential (hereinafter referred to as H) due to the forward count command, and becomes a clear terminal. The output terminal Q becomes H while CL remains at a low potential (hereinafter referred to as L). The up-down counter is composed of two-digit decimal counters u ₂ and u ₃ , and its up-down terminal U/D becomes H in response to the output signal of the flip-flop u ₁ to enter the up mode. At the same time, the output of the AND circuit u ₄ becomes H due to the forward calculation command and the output of the inverter u ₅ , and therefore the output of the OR circuit u ₆ becomes H, and the output of the AND circuit u ₇ becomes H.
can be opened. As a result, the clock pulse from the oscillator OSC passes through the AND circuit _u7 to the lower digit 10
It enters the clock pulse input terminal CLP of the decimal counter _u2 and the upper digit decimal counter _u3 , and the lower digit 10
The carry signal of the decimal counter _u2 enters the carry signal input terminal Cin of the decimal counter _u3 of the upper digit, and the clock pulses thereof are counted up by the up-down counters _u2 and _u3 . In this case, the upper digit decimal counter _u3 counts up the clock pulse when the lower digit decimal counter _u2 counts up by the clock pulse, and its carry signal output terminal Cout becomes H. Furthermore, when the contents of up-down counters u ₂ and u ₃ reach the upper limit value of 20, the second bit output of the upper digit decimal counter u ₃ becomes H, the output of inverter u ₅ becomes L, and the AND circuit
When the output of _u4 becomes L, the AND circuit _u7 closes and the up-down counters _u2 and _u3 stop receiving clock pulses. When the forward calculation switch is released, the output of the AND circuit _u4 becomes L because the forward calculation command is no longer input, the AND circuit _u7 is closed, and the up-down counters _u2 + _u3 are stopped.

Also, when the subtraction switch is pressed and a subtraction command is given, flip-flop _U1 becomes the preset terminal PR.
remains low and the clear terminal CL becomes high due to the subtraction command.
Therefore, the output becomes L. Therefore, the up-down counters u ₂ and u ₃ become in the down mode because the up-down terminal U/D becomes L. and circuit u ₈ at the same time
If the output obtained by ORing the _2nd to 4th bit outputs of the decimal counter u2 and the 1st and 2nd bit outputs of the decimal counter _u3 in the OR circuit _u9 is H, that is, the up-down counter _u2 , If the content of _u3 is not 1, which is the lower limit value, the output becomes H due to the subtraction command. Therefore, the output of the OR circuit _u6 becomes H, the AND circuit _u7 opens, and the up-down counters _u2 and _u3 count down the clock pulses applied from the oscillator OSC through the AND circuit _u7 . In this case, when the upper digit decimal counter u ₃ is inputting a borrow signal from the lower digit decimal counter u ₂ , that is, when the lower digit decimal counter u ₂ counts down to 0 by the clock pulse, it receives its carry signal. Output terminal Cout is H
When the clock pulse reaches , the next clock pulse is counted down. When the contents of the up-down counters u ₂ and u ₃ reach the lower limit of 1, the output of the OR circuit u ₉ becomes L and the output of the AND circuit u ₈ becomes L. Therefore, the output of the OR circuit _u6 becomes L, the AND circuit _u7 closes, and the up-down counters _u2 and _u3 stop. Also, when the subtraction switch is released, the output of the AND circuit _u8 becomes L because no subtraction command is input, and therefore the AND circuit _u9 is closed and the up-down counters _u2 , _u3
stops. The upper and lower limits of the up-down counters u ₂ and u ₃ were set to 20 and 1, respectively, but they can be changed arbitrarily depending on the specifications of each copying machine, such as fatigue of the photoconductor, number of sheets of paper set, usage limits of parts, etc. can be determined. During the standby period, the contents of the up-down counters _u2 and _u3 are preset to the briset counters _u10 and _u11 , and a count pulse is applied during the copy cycle to count the number of copies. Incidentally, up-down counters u ₂ and u ₃ are set by a reset pulse when the power is turned on.

However, in such an up-down type electronic counter, there is no problem when only one of the forward count command and the subtraction command is given, but there is a problem when both are given at the same time. That is, when a forward calculation command and a subtraction command are given at the same time, flip-flop _u1 's preset terminal PR and clear terminal CL both become H, and the output terminal Q becomes L, as is clear from the truth table in FIG. Become. Therefore, the up/down counters u ₂ and u ₃ enter the down mode and count down. and up-down counter
When u ₂ and u ₃ are in the down mode with only a subtraction command, they stop counting down at the lower limit of 1, but when they are in the down mode with forward commands and subtraction commands, they reach the lower limit of 1 and the AND circuit u ₈ output is L
Even when , the output of AND circuit u ₄ becomes H due to the forward calculation command, so AND circuit u ₇ does not close and continues down counting from the lower limit value to the upper limit value. The setting range will be exceeded.

In view of these points, the present invention has been designed so that when a forward count command and a subtraction command are input at the same time, one of the predetermined commands is interrupted so that the up-down counter always counts within the set range. It is intended to provide a counter circuit.

Embodiments of the present invention will be described below with reference to the drawings.

In the first embodiment of the present invention, the above-mentioned up-down electronic counter is provided with a priority circuit A that gives priority to subtraction commands over forward calculation commands, as shown in FIG. This priority circuit A is an inverter
Consisting of u ₁₂ and AND circuit u ₁₃ , if only a subtraction command is issued, the subtraction command is sent directly to priority circuit A.
It operates in the same way as the up-down electronic counter described above. Also, when only the forward calculation command is given, the output of inverter _u12 becomes H and the AND circuit
_U13 opens, and the forward count command passes through the AND circuit _u13 to perform up-counting in the same way as the up-down electronic counter described above. When a forward calculation command and a subtraction command are given at the same time, the subtraction command passes through as is, but the output of the inverter _u12 becomes L due to the subtraction command, the AND circuit _u13 is closed, and the forward calculation command is cut off. Therefore, down-counting is performed in the same way as when only a subtraction command is issued, and when the up-down counters u ₂ and u ₃ reach the lower limit, they stop counting down.

In another embodiment of the present invention, the above-mentioned up-down electronic counter is provided with a priority circuit B for giving priority to forward calculation commands over subtraction commands, as shown in FIG. This priority circuit B is an inverter
u ₁₄ and a NAND circuit u _15. When only a forward counting command is issued, the forward counting command passes through the priority circuit B as it is and performs up counting in the same way as the up-down type electronic counter described above. If only the subtraction command is given, the output of the inverter _u14 becomes H and the AND circuit _u15 opens, and the subtraction command passes through the AND circuit _u15 and counts down in the same way as the up-down electronic counter described above. conduct. When a forward calculation command and a subtraction command are given at the same time, the forward calculation command passes through as is, but the output of the inverter _u14 becomes L due to the forward calculation command, the AND circuit _u15 is closed, and the subtraction command is cut off. Therefore, up counting is performed in the same way as when only the forward count command is issued.

As described above, according to the counter circuit according to the present invention, when a forward count command and a subtraction command are simultaneously input to the up-down counter, a predetermined one is cut off, so that the up-down counter counts within the set range. can be done.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a conventional electronic counter, Fig. 2 is a truth table of a flip-flop, and Fig. 3 is a block diagram showing a conventional electronic counter.
4 and 4 are block diagrams each showing an embodiment of the present invention. A, B...priority circuit, _u1 ...mode setting means,
u ₂ , u ₃ ...up-down counter, u ₄ ~ u ₆ , u ₈ ,
_u9 ...Count stop means, _u7 ...Clock pulse control means.

Claims (1)

[Scope of utility model registration request] an up-down counter that counts up the clock pulse in the up mode and counts down the clock pulse in the down mode; a mode setting means that sets the up-down counter to the up mode by a forward count command and the down mode by a subtraction command; clock pulse control means for inputting a forward count command and a subtraction command; and a clock pulse control means for detecting that the value of the up-down counter has reached the upper limit value, and interrupting the forward count command to the clock pulse control means to input the value of the up-down counter. count stop means that detects that the count has reached a lower limit and cuts off a subtraction command to the clock pulse control means; and when a forward count command and a subtraction command are input at the same time, a predetermined one of them is cut off. A counter circuit with a priority circuit.