JPS61174772A - Charge transfer device - Google Patents
Charge transfer deviceInfo
- Publication number
- JPS61174772A JPS61174772A JP1587185A JP1587185A JPS61174772A JP S61174772 A JPS61174772 A JP S61174772A JP 1587185 A JP1587185 A JP 1587185A JP 1587185 A JP1587185 A JP 1587185A JP S61174772 A JPS61174772 A JP S61174772A
- Authority
- JP
- Japan
- Prior art keywords
- thermal oxide
- oxide film
- gate electrode
- gate
- charge transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000000203 mixture Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 10
- 238000000926 separation method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910007277 Si3 N4 Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000005865 ionizing radiation Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000000638 stimulation Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76866—Surface Channel CCD
- H01L29/76875—Two-Phase CCD
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電荷転送素子に関し、特に電荷転送ゲートの
ゲート構造およびゲート電極相互の分離構造を改善した
電荷転送素子に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charge transfer device, and more particularly to a charge transfer device in which the gate structure of a charge transfer gate and the separation structure between gate electrodes are improved.
電荷転送素子は、半導体基板の一生表面に複数個のＭＯ
Ｓ１１ゲートを配置し、ある一つのゲート下の半導体基
板にできている空乏層内に、光学的ないし電気的に注入
された少数キャリア群を、隣接するＭＯＳ型ゲートのゲ
ート電極に印加される電圧を適当に変化させることによ
り、定められた方向に一意的に転送することが基本とな
りている。A charge transfer element consists of multiple MOs on the surface of a semiconductor substrate.
S11 gates are arranged, and a group of minority carriers optically or electrically injected into the depletion layer formed in the semiconductor substrate under one gate is applied to the voltage applied to the gate electrode of the adjacent MOS type gate. The basic idea is to uniquely transfer data in a predetermined direction by appropriately changing the data.
転送方向の一意性を確保するには、当初ゲート電極に３
相のクロックパルスを印加していた。しかしながら、３
相クロツクパルスの印加は各ゲート電極とクロックパル
ス供給源との接続が難かしいことから、現在では２相ク
ロツクパルス駆動によっても電荷転送方向の一意性を確
保し得る構造が各種提案されている。To ensure the uniqueness of the transfer direction, three
A phase clock pulse was applied. However, 3
Since application of phase clock pulses makes it difficult to connect each gate electrode to a clock pulse supply source, various structures have been proposed that can ensure uniqueness of charge transfer direction even by driving two-phase clock pulses.
第２図は、２相クロツクパルス駆動であシかつ！荷転送
方向の一意性が確保される電荷転送素子の構造の内、現
在最も多く使われているものの断面図である。Ｐ型Ｓｉ
基板１の表面に６００〜１０００人厚の熱酸化膜２がゲ
ート絶縁層として存在し、この熱酸化膜２０表面には第
１のゲート電極３と第２のゲート電極４とがそれぞれ４
０００〜８０００人厚のポリＳｉ層により形成されてい
る。第２のゲート電極４は、その両端で第１のゲート電
極３に重なっており、かつ相互は第１のゲート電極３の
ポリＳｉ層表面の熱酸化膜５によって分離されている。Figure 2 shows two-phase clock pulse drive! 1 is a cross-sectional view of the structure of a charge transfer element that is currently most commonly used, which ensures uniqueness in charge transfer direction. P-type Si
A thermal oxide film 2 with a thickness of 600 to 1000 layers is present on the surface of the substrate 1 as a gate insulating layer, and a first gate electrode 3 and a second gate electrode 4 are formed on the surface of this thermal oxide film 20.
It is formed of a poly-Si layer with a thickness of 0.000 to 8000. The second gate electrode 4 overlaps the first gate electrode 3 at both ends thereof, and is separated from each other by a thermal oxide film 5 on the surface of the poly-Si layer of the first gate electrode 3.
さらに第２のゲート電極４下のＰ型Ｓｉ基板１表面はさ
らにＰ型不純物が導入された高濃度Ｐ型領域６が形成さ
れている。ここで、第１のゲート電極部分が蓄積ゲート
部、第２のゲート電極部分が転送ゲート部である。Further, on the surface of the P-type Si substrate 1 under the second gate electrode 4, a heavily doped P-type region 6 into which a P-type impurity is further introduced is formed. Here, the first gate electrode portion is the storage gate portion, and the second gate electrode portion is the transfer gate portion.
２相クロックパルスφ、−φの印加は、蕗１のグー）［
極３と第２のゲート電極４とを一組としてできる複数組
を、−組おきにクロックパルス供給源７に接続して行な
っている。The application of two-phase clock pulses φ and -φ is
A plurality of pairs of the pole 3 and the second gate electrode 4 are connected to the clock pulse supply source 7 every other pair.
第３図（ａ）〜（Ｃ）は、第２図に示した構造における
電荷転送の概略を示し次回である。第２のゲート電極４
下のＰ型Ｓｉ基板１の表面には高濃度Ｐ型領域６が形成
されているから、ある−組の第１のゲート電極３と第２
のゲート電極４とは、同一クロックパルスが印加される
ように接続されているにもかかわらず、それぞれのゲー
ト電極下に形成される空乏層の深さは異なシ、第２のゲ
ート電極４下の方が浅い。したがって２相のクロックパ
ルス電圧が相等しい時、空乏層の深さのプロファイルは
同図（ａ）の如くなる。この状態で、光学的ないし電気
的に励起された電子８は同図（ｂ）に示す如く、深い方
の空乏層すなわち、第１のゲート電極３下の空乏層内に
注入される。次いで、２相のクロックパルスφ、−φの
一方の電圧は高くなりもう一方の電圧が低く々る方に変
化してゆくと、同図（Ｃ）に示すように、電圧が高くな
る方のクロックパルスが印加されている組のゲート電極
下の空乏層は深くなり、電圧が低くなる方のクロックパ
ルスが印加されている組のゲート電極下の空乏層は浅く
なってゆく結果、第１のゲート電極３下の空乏層内に注
入されていた電子８は、第２のゲート電極４下の空乏層
との深さの差によってできるポテンシャル障壁の非対称
性によって一意的に定まった方向へ転送される。FIGS. 3(a) to 3(C) schematically show charge transfer in the structure shown in FIG. 2. Second gate electrode 4
Since a high-concentration P-type region 6 is formed on the surface of the lower P-type Si substrate 1, a certain pair of first gate electrode 3 and second gate electrode
Although the two gate electrodes 4 are connected so that the same clock pulse is applied, the depth of the depletion layer formed under each gate electrode is different. is shallower. Therefore, when the two-phase clock pulse voltages are equal, the depth profile of the depletion layer becomes as shown in FIG. In this state, the optically or electrically excited electrons 8 are injected into the deeper depletion layer, that is, the depletion layer below the first gate electrode 3, as shown in FIG. Next, as the voltage of one of the two-phase clock pulses φ and -φ increases and the voltage of the other decreases, as shown in FIG. The depletion layer under the gate electrode of the set to which the clock pulse is applied becomes deeper, and the depletion layer under the gate electrode of the set to which the clock pulse with lower voltage is applied becomes shallower. The electrons 8 injected into the depletion layer under the gate electrode 3 are transferred in a uniquely determined direction due to the asymmetry of the potential barrier created by the difference in depth with the depletion layer under the second gate electrode 4. Ru.
したがって、転送方向は同一のクロックパルスが印加さ
れる一組のゲート電極で考えれば、常に第２のゲート電
極４から第１のゲート電極３の側であり、これは、電荷
転送素子製作過程で定まってしまうものである。すなわ
ち、第２図に示した、従来の２相クロツク駆動型電荷転
送素子は、基本的な３相クロツク駆動型電荷転送素子に
比べて、ゲート電極とクロックパルス供給源との接続は
容易になった半面、電荷転送方向を任意に選択するとい
う自由度は失なわれている。（３相クロツク駆動におい
ては、クロックパルスの相関関係を反転することで、電
荷転送方向を反転できた。）従って、本発明の目的は、
２相クロツク駆動型電荷転送素子のゲート電極とクロッ
クパルス供給源との接続の容易性は維持し、かつ電荷転
送方向を外部から可変しうる電荷転送素子を提供するこ
とにある。Therefore, when considering a set of gate electrodes to which the same clock pulse is applied, the transfer direction is always from the second gate electrode 4 to the first gate electrode 3, and this is due to the fact that during the charge transfer element manufacturing process, It is fixed. In other words, in the conventional two-phase clock-driven charge transfer device shown in FIG. 2, the connection between the gate electrode and the clock pulse supply source is easier than in the basic three-phase clock-driven charge transfer device. On the other hand, the degree of freedom to arbitrarily select the direction of charge transfer is lost. (In three-phase clock driving, the charge transfer direction could be reversed by reversing the correlation of clock pulses.) Therefore, the object of the present invention is to
It is an object of the present invention to provide a charge transfer device which maintains the ease of connection between the gate electrode of a two-phase clock driven charge transfer device and a clock pulse supply source, and whose charge transfer direction can be varied from the outside.
本発明の電荷転送素子は、Ｓｉ基板の一主表面上に、複
数個のＭＯＳ型ゲートを配置し、隣接する２個のＭＯＳ
型ゲートを一組として構成される複数組のＭＯＳ型ゲー
ト群を一組おきに同一のクロックパルス供給源に接続し
てなる電荷転送素子において、前記２個一組のＭＯＳ型
ゲートの内、蓄積ゲート部は第１の熱酸化膜をゲート絶
縁層とするＭＯＳ型ゲート構造を有し、転送ゲート部は
ゲート絶縁層が前記第１の熱酸化膜より厚さの薄い第２
の熱酸化膜と該第２の熱酸化膜を覆う熱酸化膜とは異な
る組成の絶縁物層とからなる二重ゲート絶縁層型閾値可
変ＭＯＳゲート構造であシ、かつ蓄積ゲート部のゲート
電極３表面も前記第１の熱酸化膜より厚さの薄い第３の
熱酸化膜と該第３の熱酸化膜を覆り熱酸化膜とは異なる
組成の絶縁物層とからなる二重絶縁物層で覆われている
ことからなっている。In the charge transfer device of the present invention, a plurality of MOS type gates are arranged on one main surface of a Si substrate, and two adjacent MOS type gates are arranged on one main surface of a Si substrate.
In a charge transfer element in which a plurality of sets of MOS gates are connected to the same clock pulse supply source every other set, one of the two sets of MOS gates is The gate part has a MOS type gate structure in which the first thermal oxide film is a gate insulating layer, and the transfer gate part has a second thermal oxide film whose gate insulating layer is thinner than the first thermal oxide film.
A double gate insulating layer type variable threshold MOS gate structure consisting of a thermal oxide film and an insulating layer having a composition different from that of the thermal oxide film covering the second thermal oxide film, and a gate electrode of the storage gate section. 3. The surface is also a double insulator consisting of a third thermal oxide film thinner than the first thermal oxide film and an insulating layer covering the third thermal oxide film and having a composition different from that of the thermal oxide film. It consists of being covered with layers.
本発明の基健は、Ｓｉ基板表面に極めて薄い熱酸化膜を
形成し、さらに、この熱酸化膜を覆うよりに熱酸化膜と
は異なる組成の絶縁物層を形成した二重絶縁層をゲート
絶縁層とすると、ゲート電極に印加するパルスの極性、
電圧、パルス幅にしたがって、Ｓｉ基板と上層の絶縁物
層との間で電荷の移動が起り、かつ電荷の種類、量が変
化する。さらにＳｉ基板から上層の絶縁物層に注入され
た電荷は、熱的、電気的刺激ないし電離放射線照射を受
けない限９１０年以上保持されることにある。したがっ
て、ゲート電極にあらかじめ所定のパルスを印加するこ
とにより電荷転送方向を変えることができる。The fundamental feature of the present invention is to form an extremely thin thermal oxide film on the surface of the Si substrate, and then to cover this thermal oxide film, a double insulating layer with a composition different from that of the thermal oxide film is formed as a gate gate. If it is an insulating layer, the polarity of the pulse applied to the gate electrode,
Charges move between the Si substrate and the upper insulating layer, and the type and amount of charges change depending on the voltage and pulse width. Furthermore, the charge injected from the Si substrate into the upper insulating layer is retained for more than 910 years unless subjected to thermal or electrical stimulation or irradiation with ionizing radiation. Therefore, the charge transfer direction can be changed by applying a predetermined pulse to the gate electrode in advance.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第１図（ａ）は本発明の一実施例を示す断面図、第１図
（ｂ）はその−組のゲートを示す部分拡大図である。FIG. 1(a) is a cross-sectional view showing one embodiment of the present invention, and FIG. 1(b) is a partially enlarged view showing the second set of gates.
本実施例は、ＰｉＳｉ基板１の一主表面上に、複数個の
ＭＯＳ型ゲートを配置し、隣接する２個のＭＯＳ型ゲー
トを一組として構成される複数組のＭＯＳ型ゲート群を
一組おきに同一のクロックパルス供給源７に接続してな
る電荷転送素子において、前記２個一組のＭＯＳ型ゲー
トの内、蓄積ゲート部は第１の熱酸化膜２をゲート絶縁
層とし、第１のゲート電極３を有するＭＯＳ型ゲート構
造を有し、転送ゲート部は、ゲート絶縁層が第１の熱酸
化膜より厚さの薄い第２０熱酸化膜１１とこの第２の熱
酸化膜１１を覆う熱酸化膜とは異なる組成の絶縁物層と
してのＳｉ３Ｎ４層１２からカり第２のゲート電極４を
有する二重ゲート絶縁層型閾値可変ＭＯＳゲート構造で
あシ、か°つ第１のゲート電極３表面も第１の熱酸化膜
２より厚さの薄い第３の熱酸化膜１３とＳｉ３Ｎ４層１
２とからなる二重絶縁物層で覆われていることからなっ
ている。In this embodiment, a plurality of MOS type gates are arranged on one main surface of a PiSi substrate 1, and a plurality of MOS type gate groups each consisting of two adjacent MOS type gates are combined into one set. In the charge transfer device which is connected to the same clock pulse supply source 7 every other time, the storage gate part of the set of two MOS gates has the first thermal oxide film 2 as the gate insulating layer, and the first thermal oxide film 2 as the gate insulating layer. The transfer gate part has a gate insulating layer including a 20th thermal oxide film 11 thinner than the first thermal oxide film and this second thermal oxide film 11. It is a double gate insulating layer type variable threshold MOS gate structure having a second gate electrode 4 formed from a Si3N4 layer 12 as an insulating layer having a composition different from that of the covering thermal oxide film, and the first gate The surface of the electrode 3 also has a third thermal oxide film 13 thinner than the first thermal oxide film 2 and a Si3N4 layer 1.
It consists of being covered with a double insulating layer consisting of 2.
即ち、Ｐ型Ｓｉ基板１、第１のゲート電極３、第２のゲ
ート電極４の相互関係は従来構造と変ることはない。ま
た第１のゲート電極３下のゲート絶縁層も従来構造と同
様６００〜１０００人厚の熱酸化膜２で構成される。一
方、第２のゲート電極４下のゲート絶縁層は、１５〜３
０人厚の熱酸化膜１１とＣＶＤ法により成長した４００
〜１０００人厚のＳｉ３Ｎ４層１２とからなっている。That is, the mutual relationship among the P-type Si substrate 1, the first gate electrode 3, and the second gate electrode 4 is unchanged from the conventional structure. Further, the gate insulating layer under the first gate electrode 3 is also composed of a thermal oxide film 2 having a thickness of 600 to 1000 layers, similar to the conventional structure. On the other hand, the gate insulating layer under the second gate electrode 4 is 15 to 3
A thermal oxide film 11 with a thickness of 0 and a film 400 grown by the CVD method.
It consists of 12 Si3N4 layers with a thickness of ~1000.
また第１のゲート電極３０表面もポ１７Ｓｉの薄い熱酸
化膜１３と、Ｓｉ３Ｎ４層１２とからなる二重絶縁物層
で覆われておυ、この二重絶縁物層によって第１のゲー
ト電極３と第２のゲート電極４とのオーバーラツプ部に
おいて相互を絶縁している。Further, the surface of the first gate electrode 30 is also covered with a double insulating layer consisting of a thin thermal oxide film 13 of po-17Si and a Si3N4 layer 12. and the second gate electrode 4 are insulated from each other at the overlap portion.
なお、熱酸化膜１１．１３の厚さを１５〜３０人、Ｓｉ
３Ｎ４層１２の厚さを４００〜１０００人に制限するの
は、転送ゲート部が二重ゲート絶縁層型閾値可変ＭＯＳ
ゲートとして動作させることと、熱酸化膜１１゜１３は
同一熱酸化工程で形成できるようにするためである。Note that the thickness of the thermal oxide film 11.13 is 15 to 30,
The reason why the thickness of the 3N4 layer 12 is limited to 400 to 1000 is that the transfer gate part is a double gate insulating layer type variable threshold MOS.
This is to operate as a gate and to form the thermal oxide films 11 and 13 in the same thermal oxidation process.
上記本発明の構造によれば、クロックパルス供給源７と
接続する前に、ゲート電極に、例えば、＋ａｏｖ、 ５
０ｍ５幅程度０パルスを印加すると、第１のゲート電極
３下の熱酸化膜２およびＰ型Ｓｉ基板１表面には何ら変
化を生じないが、第２のゲート電極４下のＳｉ３Ｎ４１
２には、周知のキャリヤ注入現象により、Ｐ型Ｓｉ基板
１から電子が注入され蓄積される結果、Ｐ型Ｓｉ基板１
表面の正孔濃度は第１のゲート電極３下のＰ型Ｓｉ基板
１表面の正孔濃度より高くなる。即ち、従来構造におい
て第２のゲート電極下にＰ型不純物を導入し高濃度Ｐ型
領域６を形成したものと同一の効果となる。また、例え
ば、−３ｏｖ、 ５０ｍ５幅程度０パルスを印加すると
、上記と同様第１のゲート電極３下には何ら変化は生じ
ないが、第２のゲート電極４下では、Ｐ型Ｓｉ基板１よ
１）Ｓｉ３Ｎ４層１２に正孔が注入され蓄積される結果
、Ｐ型Ｓｉ基板１表面の正孔濃度は第１のゲート電極３
下のＰ型Ｓｉ基板１表面の正孔濃度より低くなる。According to the structure of the present invention, for example, +aov, 5 is applied to the gate electrode before connecting to the clock pulse supply source 7.
When a pulse of about 0 m5 width is applied, no change occurs in the thermal oxide film 2 under the first gate electrode 3 and the surface of the P-type Si substrate 1, but the Si3N41 under the second gate electrode 4 changes.
2, as a result of electrons being injected and accumulated from the P-type Si substrate 1 due to the well-known carrier injection phenomenon, the P-type Si substrate 1
The hole concentration at the surface is higher than the hole concentration at the surface of the P-type Si substrate 1 under the first gate electrode 3. That is, the effect is the same as that of the conventional structure in which a P-type impurity is introduced under the second gate electrode to form a heavily doped P-type region 6. Further, for example, if a zero pulse of about -3 ov and width of 50 m5 is applied, no change occurs under the first gate electrode 3 as described above, but under the second gate electrode 4, there is a change compared to the P-type Si substrate 1. 1) As a result of holes being injected and accumulated in the Si3N4 layer 12, the hole concentration on the surface of the P-type Si substrate 1 is lower than that of the first gate electrode 3.
The hole concentration is lower than the hole concentration on the surface of the P-type Si substrate 1 below.
即ち、ゲート電極に印加するパルス電圧の極性に応じて
第２のゲート電極４下のＰ型Ｓｉ基板１表面の正孔濃度
は、第１のゲート電極３下のＰ型Ｓｉ基板１表面の正孔
濃度より高くなるか、あるいは低くなる。従って、第１
のゲート電極３と第２のゲート電極４とに同一のクロッ
クパルスを印加した場合、それぞれのゲート電極下に形
成される空乏層の深さの差は異な’） 、Ｓ”３Ｎ４層
１２に電子が注入されている時は、ＷＩＪ２のゲート電
極４下の空乏層の方が浅く、逆に、Ｓｉ３Ｎ４層１２に
正孔が注入されている時は、第１のゲート電極３下の空
乏層の方が浅くなる。That is, depending on the polarity of the pulse voltage applied to the gate electrode, the hole concentration on the surface of the P-type Si substrate 1 under the second gate electrode 4 increases with the positive hole concentration on the surface of the P-type Si substrate 1 under the first gate electrode 3. It can be higher or lower than the pore concentration. Therefore, the first
When the same clock pulse is applied to the gate electrode 3 and the second gate electrode 4, the difference in the depth of the depletion layer formed under each gate electrode is different. When holes are injected into the Si3N4 layer 12, the depletion layer under the gate electrode 4 of the WIJ2 is shallower. Conversely, when holes are injected into the Si3N4 layer 12, the depletion layer under the first gate electrode 3 It becomes shallower.
第３図において説明したように、電荷の転送方向は、第
１のゲート電極３と第２のゲート電極４のそれぞれの下
にできる空乏層の深さの差で定まるから、第２のゲート
電極４下のＳｉ３Ｎ４層１２内に注入・蓄積されている
電荷が電子であるか正孔であるかによ２て、電荷転送方
向は反転する。即ち、本発明の構造によれば、電荷転送
方向を外部から定めることが可能な電荷転送素子を得る
ことができる。As explained in FIG. 3, the direction of charge transfer is determined by the difference in depth of the depletion layer formed under each of the first gate electrode 3 and the second gate electrode 4. The direction of charge transfer is reversed depending on whether the charges injected and stored in the Si3N4 layer 12 below 4 are electrons or holes. That is, according to the structure of the present invention, it is possible to obtain a charge transfer element whose charge transfer direction can be determined from the outside.
また、従来構造では、第２のゲート電極下のゲート絶縁
層を熱酸化により形成する際、同時に第１のゲート電極
表面に形成されるボ１７Ｓｉの熱酸化膜によって第１の
ゲート電極と第２のケート電極とを絶縁分離していたが
、本発明においては、第２のゲート電極下の熱酸化膜は
１５〜３０人の厚さしかないため、第１のゲート電極表
面に形成されるボＩＪＳｉの熱酸化膜の厚さも１００人
程成長しかならず、これでは第１のゲート電極と第２の
ゲート電極とを十分絶縁分離することは不可能である。In addition, in the conventional structure, when forming the gate insulating layer under the second gate electrode by thermal oxidation, a thermal oxide film of 17Si formed on the surface of the first gate electrode simultaneously connects the first gate electrode and the second gate electrode. However, in the present invention, since the thermal oxide film under the second gate electrode is only 15 to 30 times thick, the void formed on the surface of the first gate electrode The thickness of the IJSi thermal oxide film is only about 100 nm thick, which makes it impossible to sufficiently insulate and separate the first gate electrode and the second gate electrode.
しかしながら、本発明の構造では、第２のゲート電極下
の電荷蓄積層であるＣＶＤ法による５ｉａＮａ層を第１
のゲート電極表面にまで延在させることにより、第１の
ゲート電極と第２のゲート電極との十分な絶縁分離を確
保している。However, in the structure of the present invention, the 5iaNa layer formed by the CVD method, which is the charge storage layer under the second gate electrode, is
By extending to the surface of the gate electrode, sufficient insulation separation between the first gate electrode and the second gate electrode is ensured.
以上説明したように、本発明によれは、外部から電荷転
送方向を定めることが可能な電荷転送素子を、ゲート電
極相互間の絶縁分離を妨げることなく得ることができる
。As described above, according to the present invention, a charge transfer element whose charge transfer direction can be determined from the outside can be obtained without interfering with insulation separation between gate electrodes.
第１図（ａ）は本発明の一実施例を示す断面図、第れに
よる電荷転送の説明図である。
１・・・・・・Ｐ型Ｓｉ基板、２・・・・・・熱酸化膜
、３・・・・・・第１のゲート電極、４・・・・・・第
２のゲート電極、５・・・・・・熱酸化膜、６・・・・
・・高濃度Ｐ型領域、７・山・・クロックパルス供給源
、１１・・・・・・熱酸化膜、１２・・・・・・Ｓｉ３
Ｎ４層、１３・・・・・・熱酸化膜、φ、−φ・・・・
・・クロック。
苗ｆ 図
ｌレ
ス Ｃα２源
？
（ｂ）FIG. 1(a) is a cross-sectional view showing one embodiment of the present invention, and a second explanatory diagram of charge transfer. DESCRIPTION OF SYMBOLS 1... P-type Si substrate, 2... Thermal oxide film, 3... First gate electrode, 4... Second gate electrode, 5 ...Thermal oxide film, 6...
...High concentration P-type region, 7. Mountain... Clock pulse supply source, 11... Thermal oxide film, 12... Si3
N4 layer, 13... thermal oxide film, φ, -φ...
··clock. Seedling f Figure l reply Cα2 source? (b)
Claims (2)
トを配置し、隣接する２個のＭＯＳ型ゲートを一組とし
て構成される複数組のＭＯＳ型ゲート群を一組おきに同
一のクロックパルス供給源に接続してなる電荷転送素子
において、前記２個一組のＭＯＳ型ゲートの内、蓄積ゲ
ート部は第１の熱酸化膜をゲート絶縁層とするＭＯＳ型
ゲート構造を有し、転送ゲート部はゲート絶縁層が前記
第１の熱酸化膜より厚さの薄い第２の熱酸化膜と該第２
の熱酸化膜を覆う熱酸化膜とは異なる組成の絶縁物層と
からなる二重ゲート絶縁層型閾値可変ＭＯＳゲート構造
であり、かつ蓄積ゲート部のゲート電極表面も前記第１
の熱酸化膜より厚さの薄い第３の熱酸化膜と該第３の熱
酸化膜を覆う熱酸化膜とは異なる組成の絶縁物層とから
なる二重絶縁物層で覆われていることを特徴とする電荷
転送素子。(1) A plurality of MOS type gates are arranged on one main surface of a Si substrate, and every other set of MOS type gate groups, each consisting of two adjacent MOS type gates, is the same. In the charge transfer device connected to a clock pulse supply source, the storage gate portion of the set of two MOS gates has a MOS gate structure with a first thermal oxide film as a gate insulating layer. , in the transfer gate section, the gate insulating layer includes a second thermal oxide film thinner than the first thermal oxide film and the second thermal oxide film.
This is a double gate insulating layer type variable threshold MOS gate structure consisting of an insulating layer having a composition different from that of the thermal oxide film covering the thermal oxide film, and the gate electrode surface of the storage gate portion also covers the first thermal oxide film.
be covered with a double insulating layer consisting of a third thermal oxide film thinner than the thermal oxide film of and an insulating layer having a composition different from that of the thermal oxide film covering the third thermal oxide film; A charge transfer device characterized by:
り、熱酸化膜を覆う該熱酸化膜とは異なる組成の絶縁物
層が、ＣＶＤ法により成長させたＳｉ＿３Ｎ＿４層であ
って、かつ該Ｓｉ＿３Ｎ＿４の厚さは４００〜１０００
Åである特許請求の範囲第（１）項記載の電荷転送素子
。(2) The thickness of the second and third thermal oxide films is 15 to 30 Å, and the insulating layer covering the thermal oxide film and having a composition different from that of the thermal oxide film is a Si_3N_4 layer grown by the CVD method. , and the thickness of the Si_3N_4 is 400 to 1000
The charge transfer device according to claim (1), which is Å.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1587185A JPS61174772A (en) | 1985-01-30 | 1985-01-30 | Charge transfer device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1587185A JPS61174772A (en) | 1985-01-30 | 1985-01-30 | Charge transfer device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61174772A true JPS61174772A (en) | 1986-08-06 |
Family
ID=11900860
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1587185A Pending JPS61174772A (en) | 1985-01-30 | 1985-01-30 | Charge transfer device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61174772A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5585653A (en) * | 1993-07-30 | 1996-12-17 | Nec Corporation | Solid-state photoelectric imaging device with reduced smearing |
| US6018170A (en) * | 1996-06-28 | 2000-01-25 | Nec Corporation | Single-layer-electrode type two-phase charge coupled device having smooth charge transfer |
-
1985
- 1985-01-30 JP JP1587185A patent/JPS61174772A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5585653A (en) * | 1993-07-30 | 1996-12-17 | Nec Corporation | Solid-state photoelectric imaging device with reduced smearing |
| US6018170A (en) * | 1996-06-28 | 2000-01-25 | Nec Corporation | Single-layer-electrode type two-phase charge coupled device having smooth charge transfer |
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