KR970053612A - Manufacturing method of capacitor for semiconductor device - Google Patents

Manufacturing method of capacitor for semiconductor device Download PDF

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Publication number
KR970053612A
KR970053612A KR1019960061178A KR19960061178A KR970053612A KR 970053612 A KR970053612 A KR 970053612A KR 1019960061178 A KR1019960061178 A KR 1019960061178A KR 19960061178 A KR19960061178 A KR 19960061178A KR 970053612 A KR970053612 A KR 970053612A
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KR
South Korea
Prior art keywords
layer
support structure
substrate
sequential
capacitor
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KR1019960061178A
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Korean (ko)
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KR100432772B1 (en
Inventor
마르틴 프라노쉬
헤르만 벤트
라인하르트 슈텡클
Original Assignee
로더리히 네테부쉬·롤프 옴케
지멘스 악티엔게젤샤프트
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Publication of KR970053612A publication Critical patent/KR970053612A/en
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Publication of KR100432772B1 publication Critical patent/KR100432772B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor

Abstract

본 발명은 반도체 장치용 캐패시터 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a capacitor for a semiconductor device.

캐패시터, 특히 적층 캐패시터를 가지는 다이내믹 메모리 셀 장치를 위해, 제1도전 재료로 형성되는 층 및 상기 제1층과 선택적으로 에칭될 수 있는 제2재료로 교대로 형성되는 층을 포함하는 순차적 층이 형성된다. 층 구조는 순차적 층으로부터 형성되며, 상기 층 구조의 측면은 각각 도전 지지 구조(5)를 가진다. 상기 층의 표면이 커버되지 않는 개구부, 특히 갭이 상기 층 구조에 형성된다. 상기 제2재료로 형성되는 층은 상기 제1재료로 형성되는 층에 대해 선택적으로 제거된다. 상기 제1재료(41)와 상기 지지구조(5)로 형성되는 층의 커버되지 않은 표면은 카운터 전극(7)이 노출되는 캐패시터 유전체(6)를 가진다. 상기 캐패시터는 P+도핑된 폴리실리콘에 선택적인 P-도핑된 폴리실리콘의 애칭을 사용하여 제조될 수 있다.For dynamic memory cell devices having capacitors, in particular stacked capacitors, a sequential layer is formed comprising a layer formed of a first conductive material and a layer alternately formed of a second material that can be selectively etched with the first layer. do. The layer structure is formed from sequential layers, each side of the layer structure having a conductive support structure 5. Openings, in particular gaps, are formed in the layer structure in which the surface of the layer is not covered. The layer formed of the second material is selectively removed relative to the layer formed of the first material. The uncovered surface of the layer formed of the first material 4 1 and the support structure 5 has a capacitor dielectric 6 to which the counter electrode 7 is exposed. The capacitor can be made using the nickname of P − doped polysilicon selective to P + doped polysilicon.

Description

반도체 장치용 캐패시터 제조 방법Manufacturing method of capacitor for semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 제1재료로 형성되는 층과 제2재료로 형성되는 층을 교대로 포함하는 순차적 층을 가지는 기판을 도시하는 도면이다. 제12도는 캐패시터 유전체와 카운터 전극의 형성 후 기판을 도시하는 도면이다.1 is a diagram showing a substrate having a sequential layer that alternately includes a layer formed of a first material and a layer formed of a second material. 12 is a diagram showing a substrate after formation of a capacitor dielectric and a counter electrode.

Claims (8)

반도체 장치용 캐패시터 제조 방법에 있어서, 제1재료로 형성되는 층(41)과 제2재료로 형성되는 층(42)을 교대로 포함하여 순차적 층(4)이 형성되는데, 상기 제1재료는 전기적으로 도전되고 상기 제2재료는 상기 제1재료에 관련하여 선택적으로 에칭될 수 있고, 상기 순차적 층(4)은 측면은 갖는 적어도 하나의 층 구조(4')가 형성되도록 구조화되고, 도전 재료로 형성되는 지지 구조(5)가 형성되는데, 상기 지지 구조는 적어도 상기층 구조(4')의 측면을 커버하고, 상기 제1및 제2재료로 형성되는 층(41,42)의 표면이 커버되지 않는 적어도 하나의 개구부가 상기 층 구조에 형성되고, 상기 제2재료로 형성되는 층(42)은 상기 제1재료로 형성되는 층(41)과 상기 지지구조(5)에 관련하여 선택적으로 제거되고, 상기 제1재료로 형성되는 층(41)과 상기 지지 구조(5)의 커버되지 않은 표면을 캐패시터 유전체(6)를 가지며, 게이트 전극(7)이 상기 캐패시터 유전체(6)의 표면위에 형성되는 것을 특징으로 하는 방법.In the method of manufacturing a capacitor for a semiconductor device, a sequential layer 4 is formed by alternately including a layer 4 1 formed of a first material and a layer 4 2 formed of a second material, wherein the first material Is electrically conductive and the second material can be selectively etched in relation to the first material, the sequential layer 4 being structured to form at least one layer structure 4 'having sides A support structure 5 formed of a material is formed, the support structure covering at least the sides of the layer structure 4 'and of the layers 4 1 , 4 2 formed of the first and second materials. At least one opening whose surface is not covered is formed in the layer structure, and the layer 4 2 formed of the second material is formed in the layer 4 1 formed of the first material and the support structure 5. Related is selectively removed by a layer (41) and said support structure (5) is formed of a first material Has a non-covered surface of the capacitor dielectric (6), a gate electrode 7 is characterized in that formed on the surface of the capacitor dielectric (6). 제1항에 있어서,상기 제1재료로 형성되는 층(41)과 상기 지지구조(5)는 도판트 농도가 1020㎝-3미만인 P+도핑된 실리콘으로 형성되고, 상기 제2재료로 형성되는 층(42)은 도판트 농도가 1019㎝-3미만인 P-도핑된 실리콘으로 형성되는 것을 특징으로 하는 방법.The layer 4 1 and the support structure 5 of claim 1, wherein the layer 4 1 and the support structure 5 are formed of P + doped silicon having a dopant concentration of less than 10 20 cm -3 . The layer (4 2 ) formed is formed from P − doped silicon having a dopant concentration of less than 10 19 cm −3 . 제2항에 있어서, 상기 제1재료로 형성되는 층(41)과 상기 제2재료로 형성되는 층(42)은 폴리실리콘의 인시튜 도핑 층착을 통해 형성되고, 상기 지지 구조(5)는 도핑된 실리콘의 선택적 에피텍셜 성장을 통해 형성되는 것을 특징으로 하는 방법.3. The support structure (5) according to claim 2, wherein the layer (4 1 ) formed of the first material and the layer (4 2 ) formed of the second material are formed through in-situ doping lamination of polysilicon, Is formed through selective epitaxial growth of doped silicon. 제3항에 있어서, 상기 선택적 에피텍셜 성장은 700과 750℃ 상이의 온도 범위에서 SiCl2H2,HCl,H2,B2H2를 사용하여 수행되는 것을 특징으로 하는 방법.The method of claim 3, wherein the selective epitaxial growth is performed using SiCl 2 H 2 , HCl, H 2 , B 2 H 2 in a temperature range of 700 and 750 ° C. 5. 제2항에 있어서, 상기 제1재료로 형성되는 층(241)과 상기 제2재료로 형성되는 층(24)은 폴리실리콘의 인 시튜 도핑 층착을 통해 형성되고, 상기 지지 구조(25')는 도핑된 폴리실리콘층(25)의 인 시튜 도핑 증착및 이방성 에칭 백을 통해 형성되는 것을 특징으로 하는 방법.The method of claim 2, wherein the layer (24) formed of a second material and a layer (24 1) formed of a first material is formed through in-situ doping cheungchak of polysilicon, characterized in that the support structure (25 ') Is formed through in-situ doping deposition and anisotropic etching back of the doped polysilicon layer (25). 제1항 내지 제5항 중 어느 한 항에 있어서, 상기 층 구조(4')내의 상기 개구부는 상기 지지 구조(5)를 갖는 상기 층 구조를 갭에 의해 분리되는 2개 섹션으로 분할하는 것을 특징으로 하는 방법.6. The opening as claimed in claim 1, wherein the opening in the layer structure 4 ′ divides the layer structure with the support structure 5 into two sections separated by a gap. 7. How to. 제1항 내지 제5항 중 어느 한 항에 있어서, 상기 기판(1)은 선택 트랜지스터(AT), 비트 라인(BL), 워드라인(WL) 및 절연층(2)을 가지는 반도체 기판을 포함하는데, 이 반도체 표면 위에 상기 순차적 층(4)이배치 되는 것을 특징으로 하는 방법.The substrate (1) according to any one of the preceding claims, wherein the substrate (1) comprises a semiconductor substrate having a selection transistor (AT), a bit line (BL), a word line (WL) and an insulating layer (2). And the sequential layer (4) is arranged on this semiconductor surface. 제6항에 있어서, 상기 기판(1)은 선택 트랜지스터(AT), 비트 라인(BL), 워드 라니(WL) 및 절연층(2)을 가지는 반도체 기판을 포함하는데, 이 반도체 표면위에 상기 순차적 층(4)이 배치되는 것을 특징으로 하는 방법.7. The substrate (1) of claim 6, wherein the substrate (1) comprises a semiconductor substrate having a select transistor (AT), a bit line (BL), a word line (WL) and an insulating layer (2), on which the sequential layer is placed. (4) is arranged. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019960061178A 1995-12-15 1996-12-03 Capacitor Manufacturing Method for Solid State Devices KR100432772B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19546999.2 1995-12-15
DE19546999A DE19546999C1 (en) 1995-12-15 1995-12-15 Capacitor mfg system for semiconductor device

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KR970053612A true KR970053612A (en) 1997-07-31
KR100432772B1 KR100432772B1 (en) 2004-08-09

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US (1) US5817553A (en)
EP (1) EP0779656A3 (en)
JP (1) JP3681490B2 (en)
KR (1) KR100432772B1 (en)
DE (1) DE19546999C1 (en)
TW (1) TW396497B (en)

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US6114201A (en) * 1998-06-01 2000-09-05 Texas Instruments-Acer Incorporated Method of manufacturing a multiple fin-shaped capacitor for high density DRAMs
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Also Published As

Publication number Publication date
JPH09199689A (en) 1997-07-31
JP3681490B2 (en) 2005-08-10
EP0779656A2 (en) 1997-06-18
EP0779656A3 (en) 1999-11-17
TW396497B (en) 2000-07-01
DE19546999C1 (en) 1997-04-30
KR100432772B1 (en) 2004-08-09
US5817553A (en) 1998-10-06

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