JPS61174770A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain an N-P-N transistor characterized by a high speed operation, which is formed in longitudinal up and down direction, by forming N<+>N<->P<+>N<+>N<+> laminated bodies on a P<-> substrate. CONSTITUTION:On a P<-> Si substrate 1, a P<+> channel cutting part 12 and SiO2 13 are laminated, and a hole 14 is provided. An N<+> layer 15 is embedded from the hole 14, and an N<-> epitaxial layer 16 is continuously grown. ions are implanted into the N<-> layer 16, and P<+> layers 17a adn 17b are simultaneously formed. B high implanted energy, an N<+> layer 18a is formed through the P<+> layer 17b and annealed. As a result, an N<+> collector 15a, the N-epitaxial layer 16 and an N<+> emitter 18a held between the P<+> base 17c and the P<+> layer 17b are formed. Then, only the exposed part of the emiter-base junction is covered by the SiO2 13. N<+>, P<+> and N<+> type impurity ions are implanted in the emitter, base and collector regions. After annealing, electrodes 19-21 are attached. In this constitution, junction capacity is decreased, the current feeding path to the base layer is broadened, the base resistance is decreased, and the device characterized by a high speed operation can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a high-speed operating semiconductor device and a method for manufacturing the same.

[Conventional technology]

Generally speaking, in order to increase the speed of semiconductor devices,
In the case of semiconductor devices using silicon as a substrate,
Bipolar transistors are often used, and in order to improve the operating performance of bipolar transistors, the emitter-base, collector-base, and collector-substrate junction capacitances are usually reduced, and the base resistance is minimized as much as possible. It is necessary to make it small, and theoretically in the case of a normal submicron device, 23 GHz
It is said that it is possible to achieve a cutoff frequency up to about 100%.

Conventionally, in order to obtain this type of high-speed semiconductor device, bipolar transistors have been configured to be as small as possible, thereby reducing their junction capacitance. Reducing the resistance was technically extremely difficult.

That is, FIG. 2 shows a schematic structure of a conventional high-speed semiconductor device of this type, in this case a transistor having an oxide film isolation structure.

In the conventional structure shown in FIG. 2, reference numeral 1 denotes a p-type silicon semiconductor substrate, 2 an N" type buried layer, 3 an N-type epitaxial growth layer, and 4 a P+ type base region.

5 is an N+ type emitter region, 6 is a P'' type implantation region, 7 is a protective oxide film, and 8, 9.10 are emitter, base, and collector electrodes.In other words, in the case of the conventional configuration, In general, the transistor structure is expanded laterally on a semiconductor substrate to form an emitter, base, and collector, respectively.

[Problem that the invention seeks to solve]

As you can see, the current technological trends for this type of high-speed device are to extremely reduce the lateral dimension and miniaturize the structure itself, in order to meet the above-mentioned requirements, and to increase the junction capacitance of each part. Structures that reduce as much as possible tend to be preferred. However, even if such a method were adopted and a design rule of, for example, IJL width could be achieved, there was a limit to the reduction of base resistance as long as the base was formed laterally. .

In view of these conventional problems, this invention achieves miniaturization of the transistor structure, and through this miniaturization, improves the integration density and reduces the junction capacitance of each part, as well as reduces the base resistance. The object of the present invention is to obtain a semiconductor device and a method for manufacturing the same.

[Means for solving problems]

In order to achieve the above object, a semiconductor device according to the present invention has an oxide film formed on a semiconductor substrate with an opening of a predetermined size, and each part of a transistor is vertically arranged in the opening. In addition, the emitter region is sandwiched between the base region and the emitter region from above and below.

[For production]

Therefore, in this invention, by arranging each part of the transistor in the vertical and vertical directions, it is possible to reduce the lateral spread with respect to the semiconductor substrate, improve the integration density, and reduce the junction capacitance of each part of the transistor. By configuring the base region to sandwich the emitter region from above and below, the base current supply path becomes wider and the base resistance can be reduced.

〔Example〕

Below, a first embodiment of a semiconductor device according to the present invention will be described.
This will be explained in detail with reference to Figures (a) to (e).

These FIGS. 1(a) to 1(e) show the method of manufacturing a semiconductor device according to this embodiment in step-by-step order.

In this embodiment method, first, a P+ channel cut layer 12 and then an oxide film 13 are sequentially formed on the entire main surface of a P- semiconductor substrate 11, and these are formed in a predetermined area so that they can be seen through the opening 14. Along with selectively opening the size,
By ion implantation or diffusion from this opening 14, N
1 buried layer 15 is formed (FIG. 1(a)), and an N-epitaxial growth layer tilt is grown within this opening 14 (FIG. 2(b)).

Next, the junctions of the P+ base layer 17a, the N'' emitter Wj18, and the P'' base layer 17b are sequentially formed in the N- epitaxial growth layer 1B by ion implantation or diffusion (FIG. 3(C)). For each junction, first, the P+ base layer 17a is diffused into the N- epitaxial growth layer 16, then the N+ emitter layer 18 is ion-implanted and driven, and then an epitaxial layer is stacked again, and the P+ base 517
b by ion implantation and driving, or first, P is formed on the N- epitaxial growth layer 1B.
+ base layers 17a and 17b are formed at the same time, and then the N+ emitter layer 1B is formed by ion implantation and driving so as to exceed the P base layer +7b using relatively high implantation energy. , an N+ collector buried layer 15a that constitutes a transistor.
, N-epitaxial growth LLB, P" base region 17
c, and an N+ emitter region 18a sandwiched from above and below by this P'' base region 17c.

Next, in the cross-sectional state shown in FIG. 1(C), the plane is 90
From a different direction, only the portion where the emitter-base junction is exposed on the surface is covered with the oxide film 13 in the same manner as above, and the emitter-base junction is covered with the oxide film 13.

For each area that becomes a collector, N
", P", and N+ impurities are ion-implanted and driven at the same time (Fig.
! 9, 20, and 21 are provided (see (e) in the same figure), and in this way, the desired transistor configuration is obtained.

Therefore, in the case of the above embodiment, since the emitter, base, and collector of the transistor structure are arranged vertically and vertically with respect to the semiconductor substrate, it is possible to control the spread in the lateral direction and achieve high-density integration. By making each part as small as possible, the junction capacitance can be reduced, and since the emitter region is sandwiched between the base region and the emitter region from above and below, the base current supply path is widened. ,
As a result, base resistance can be reduced.

Incidentally, in the configuration of the above embodiment, the case where a p-type semiconductor substrate is used has been described, but it goes without saying that similar effects can be obtained even when applied to an n-type semiconductor substrate.

〔Effect of the invention〕

As detailed above, according to the present invention, each component of a transistor is formed as small as possible in the vertical and vertical directions on a semiconductor substrate, and the emitter region is sandwiched between the base regions from above and below. Since the structure is arranged in such a manner that the junction capacitance of each part of the structure can be reduced, the supply current path is widened in the base region, and the base resistance can be significantly reduced. For example, if the base resistance is carefully reduced, the gate delay speed can be suppressed to less than % when operating at high speed with low current consumption, and a high speed operating semiconductor device on the order of 10 to 50 psec can be obtained even with a Si substrate. By sandwiching the emitter from above and below to form a base current path in a cylindrical shape, the base current caused by surface recombination due to the misaligned lattice constant between the oxide film and Si, which would normally occur in the past, can be reduced. Problems such as a decrease in hFE due to the disappearance of 2 are resolved, and the noise margin is also improved due to the reduction in base resistance, making it easier to apply to bipolar linear processes, which has been difficult in the past. Moreover, this transistor configuration can be easily manufactured by applying conventional techniques, and the main junction formation is
In particular, it has nine excellent features, such as ease of manufacture since it does not require mask alignment at all.

[Brief explanation of drawings]

FIGS. 1(a) to 1(e) are cross-sectional views showing the manufacturing method of a semiconductor device according to an embodiment of the present invention in the order of steps, and FIG. 2 is a cross-sectional view showing the general structure of a conventional semiconductor device. It is a diagram. 11... Semiconductor substrate, 12... Channel cut layer 13... Oxide film, 14... Opening, 15.
(15a)...buried layer, (collector buried layer),
16...Epitaxial growth layer, 17a, 17b,
(17c) ...Base layer, (base region),
18. (18a)...Emitter layer, (emitter region), 19.20.21...Emitter, base,
Each external electrode of the collector. Agent Masuo OiwaFigure 1Figure 1

Claims (2)

[Claims] (1) A first semiconductor layer of a second conductivity type formed sequentially on a semiconductor substrate of a first conductivity type, a low concentration semiconductor layer of a second conductivity type, and a semiconductor layer formed on the low concentration semiconductor layer. a second semiconductor layer of a first conductivity type; and a third semiconductor layer of a second conductivity type formed to be sandwiched between the second semiconductor layer from above and below; What is claimed is: 1. A semiconductor device comprising at least a transistor structure in which first, second, and third semiconductor layers are used as a collector, a base, and an emitter, respectively. (2) Forming an oxide film on the semiconductor substrate of the first conductivity type and selectively opening the oxide film to a predetermined size; a step of forming a first semiconductor layer of a second conductivity type; a step of burying the opening with a low concentration semiconductor layer of a second conductivity type; a second semiconductor layer, and a third semiconductor layer of the second conductivity type that serves as an emitter sandwiched by the second semiconductor layer.
A method of manufacturing a semiconductor device, the method comprising at least the step of forming semiconductor layers in each of the semiconductor layers.