JPS61174762A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain an RAM having excellent rising characteristic, by connecting CMOSFETs by an N-type poly Si layer, decreasing Al wiring layers, making the device compact, and providing a P-N junction in a P layer. CONSTITUTION:CMOSFETs 13 and 14 and a source and a drain 11 and 12 are provided in an N layer 81 and a P layer 82. Gate elements 23 and 24 are formed at intersecting positions 84 and 85 of a word line 22 of a first poly Si layer 83 and the N layer 81. Elements 11 and 12 are provided at intersecting positions 88 and 89 of first poly Si layers 86 and 87, and the layer 81. Of second poly Si layers 92 and 93, the layer 92 is connected to the N layer 81 and the P layer 82 through holes 94 and 95 and connected to the layer 87 through a hole 96. The layer 93 is connected to the N layer 81 through a hole 97 and connected to the layer 86 and a part of the layer 82 through a hole 98. Al wirings 100 and 101 (bit lines 21 and 22) are connceted to a part of the N layer 81 through holes 102 and 103. A grounding Al wiring 99 is connected to the N layer 81 through a hole 104. Esaki diodes 27 and 28 are formed by diffusion from the poly Si layer 92 to the P layer 82. In this constitution, the number of the Al wiring is decreased than in a conventional device. The device can be made compact. An RAM having a quick rising speed is obtained by the insertion of the diodes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a semiconductor device provided with a wiring layer connecting semiconductor regions of different conductivity types, and a method for manufacturing the same.

Technical Yellow Steel of the Invention and Its Problemsj In the field of semiconductor integrated circuits, especially devices such as RAM and ROM, memory cells are becoming smaller year by year. 8th
The figure is a circuit diagram showing the configuration of a memory cell of a CMOS static RAM, which is a type of RAM. As is well known, this memory cell includes a P-channel MO8 transistor 11.
CMOS inverters 15.12 each and N-channel, \40S transistors 13.14 respectively.
A data storage flip-flop circuit 17 configured by alternately connecting 16 input/output terminals, and a source-drain connection between one data storage node 18 of this flip-flop circuit 17 and one focus line 20. A transfer gate N-channel MOS transistor 23 with a gate connected to the word line 22 and a source-drain connection between the other data storage node 19 of the flip-flop circuit 17 and the bit line 21 on the other side are connected. It consists of an inserted N-channel MOS transistor 24 for a transfer gate whose gate is connected to the word line 22. Incidentally, all of the MO8l-transistors 11 to 14 and 23.24 are of the enhancement type.

FIG. 9 is a circuit diagram showing the structure of a so-called E/R type thrust static RAM Morisel, which is a type of RAM and is composed of a high impedance resistor and an enhancement type MOS transistor.

This memory cell is designed so that high impedance load resistors 25 and 26 are provided in place of the P channel MOS transistors 11 and 12 of the flip-flop circuit 17 in the CMOS static RAM cell.

By the way, when comparing the characteristics of both of the above-mentioned memory cells, the CMOS static RAM cell has a greater advantage in terms of power consumption in standby state, data storage retention ability, etc. For example, regarding power consumption, CMO
In the case of a static RAM cell, this is determined only by the leakage current of each transistor. However, in the case of E/R thruster static RAM cells, the drive transistor N
It is necessary to supply leakage current in channel MOS transistors 13 and 14 with high impedance resistors 25 and 26, respectively. In order to statically hold data, MOS transistors 13 and 14 are used.
A current of about 100 times the leakage current at storage node 1
It is necessary to supply it to 8 or 19.

Further, the resistors 25 and 26 are generally made of polycrystalline silicon. As devices become smaller, it becomes difficult for polycrystalline silicon resistors themselves to maintain a low current level.

Also, in terms of stability of cell operation, CMOS static RAM cells are more stable! It has excellent voltage margin, noise margin, and resistance to soft errors caused by alpha rays. This is because the load elements are transistors (11, 12), which are active elements, and the data storage nodes 18 and 19 have excellent recovery characteristics to a high level.

Furthermore, in terms of cell size, CMOS static R
E/R thruster static RAM cells are more advantageous than AM cells. This cell size determines the chimp size, and in terms of high integration and manufacturing cost, the E/R type thruster static RA
This means that the M cell is profitable. In other words, when using a normal transfer gate for an E/R thruster static RAM cell, it can be configured with four MOS transistors and two resistors as shown in Figure 9, of which the resistor is active as will be explained later. It can be easily formed on the device. Therefore, it is suitable for high integration.

On the other hand, in the case of a CMOS static RAM cell, as shown in FIG. The size is E/R type thruster static R
The AM cell also becomes large.

FIG. 10 is a pattern plan view of a CMOS static RAM cell. In the figure, 31 is an N-type diffusion region that becomes the source and drain regions of the N-channel transistors 13.14, and 32 is a P-type diffusion region that becomes the source and drain regions of the P-channel transistors 11.12. be. 33 is a first polycrystalline silicon layer that becomes the word line 22, and this polycrystalline silicon layer 3
The transfer gate transistors 23.2 are located at positions 34 and 35 where 3 and the N-type diffusion region 31 intersect.
4 is formed.

36 and 37 are also first layer polycrystalline silicon layers,
These polycrystalline silicon layers 36 and 37 and the above N
N-channel side MOS transistors 13.14 constituting the CMOS inverter 15.16 are formed at positions 38 and 39 where the type diffusion region 31 intersects. Further, P-channel side MOS transistors 11.12 constituting the CMOS inverter 15.16 are formed at positions 40 and 41 where the polycrystalline silicon layers 36 and 37 intersect with the P-type diffusion region 32, respectively. In addition, the diagonally shaded area downward to the right in the figure is the ground potential V.
2nd layer of N-type polycrystalline silicon 42 connected to ss
This polycrystalline silicon layer 42 is connected to a part of the N-type diffusion layer 31 via a contact hole 43. The diagonally shaded portions downward to the left in the figure are the weight-bearing parts 14 to 47 made of aluminum, respectively.

One of the wiring layers 44 is used as the one bit line, and this wiring R44 is connected to a part of the N type diffusion layer 31 through a contact hole 48. The wiring layer 45 is connected to the other bit line, and this wiring layer 45 is connected to a part of the N type diffusion layer 31 through a contact hole 49. The wiring layer 46 is used as an internal interconnect, and connects the N-type diffusion layer 31 and the P-type diffusion layer 32 via contact holes 50 and 51.
It is connected via a contact hole 52 to the first layer polycrystalline silicon layer 37 which becomes the gate wiring of the P-channel MO3 transistor. The wiring layer 41 is used as internal interconnection, and is connected to contact holes 53 and 5.
4, the N-type diffusion layer 31 and the P-type diffusion layer 32 are connected through the contact hole 54, and the first polycrystalline silicon layer 36 serves as the gate wiring of the P-channel MO8i-transistor. It is connected to the.

FIG. 11 is a pattern plan view of an E/R type static RAM cell. In the figure, reference numeral 61 indicates N-type diffusion regions of the source and drain regions of N-channel MOS transistors 13.14 and 23.24. Reference numeral 62 denotes a first polycrystalline silicon layer that becomes the word line 22, and the transfer gate transistors 23 and 24 are located at positions 63 and 64 where this polycrystalline silicon layer 62 and the N-type diffusion region 61 intersect. is formed. 65 and 6
6 is also a first polycrystalline silicon layer, and these polycrystalline silicon layers 65 and 66 and the above N-type diffusion region 6
The driving N-channel MOS transistors 13 and 14 are formed at positions 67 and 68 where 1 and 1 intersect. In addition, the diagonally shaded area downward to the right in the figure is the power supply potential Vc.
The second .c connected to A part of this second polycrystalline silicon layer 69 constitutes the resistor 25.26. The diagonally shaded portions downward to the left in the figure are wiring layers 70 to 72 formed of aluminum, respectively. Two of these wiring layers 71 and 72 are used as the pair of bit lines. The wiring layer 70 is connected to the ground potential Vss, and the wiring layer 10 is connected to the N-type diffusion layer 6 through the contact hole 73.
Connected to part of 1.

When actually integrating cells, CMOS static RAM
In the cell, as shown in FIG. 10, a second layer of N-type polycrystalline silicon layer 42 is used as a supply line for the potential Vss, and the wiring density of I4 to I47 made of aluminum in the lateral direction of the cell is as follows. There are four lines per cell. At this time, the density of the second polycrystalline silicon layer is one per cell.

On the other hand, as shown in FIG. 11, an E/R thruster static RAM cell consists of two bit lines made of wiring layers made of aluminum, and a high impedance resistance layer made of two second multilayer layers. It is composed of a crystalline silicon layer. These two second polycrystalline silicon layers are then formed over the active element. Here, when comparing the cell area in FIG. 10 and FIG. 11, the cell area in FIG. 10 is about 141% of that in FIG. 11. One of the things that particularly causes an increase in cell size is the wiring layer made of aluminum.

As is clear from FIGS. 10 and 11, the number of wiring layers made of aluminum is four in the case of FIG. 10, while there are three in the case of FIG. For this reason, CMO
The width of the S static RAM cell is determined by the density of the aluminum wiring layer, and reducing the number of wiring layers is effective in reducing the cell size.

However, it is important to ensure the length of the polycrystalline silicon layer that constitutes the high impedance resistor of the E/R thruster static RAM cell. Therefore, it is difficult to reduce the cell size of this E/R thruster static RAM cell in the vertical direction, and there is a limit to the reduction.

In this way, the CMOS static RAM cells that have existed for a long time have advantages in terms of characteristics, but at present there remains a problem with the cell size. The problem is that it can only be reduced.

Purpose of the Invention This invention was made in consideration of the above circumstances, and its purpose is to provide a semiconductor device that can reduce the cell size during integration and has good characteristics, and a method for manufacturing the same. Our goal is to provide the following.

[Summary of the Invention] In order to achieve the above object, the present invention connects a P-type first semiconductor region and an N-type second semiconductor region with a wiring layer made of polycrystalline silicon containing N-type impurities. By doing so, the number of wiring layers made of aluminum is reduced compared to the conventional technology, thereby achieving a reduction in cell size.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a pattern plan view showing one memory cell in which the semiconductor device according to the present invention is implemented as a CMOS static RAM cell. This cell is 0MO in FIG.
This is an integrated version of Type 3. In the figure, 81 is an N-type diffusion region that becomes the source and drain regions of N-channel transistors 13.14 and 23.24, and 82 is a P-type diffusion region that becomes the source and drain regions of P-channel transistors 11.12. This is the diffusion area. 83 is a first polycrystalline silicon layer that becomes the word line 22; this polycrystalline silicon layer 83
and the N-type diffusion region 81 intersect at positions 84 and 8
5 is the transfer gate transistor 23.2.
4 is formed.

86 and 87 are also first layer polycrystalline silicon layers,
These polycrystalline silicon layers 86 and 87 and the above N
N-channel side MOS transistors 13.14 constituting the CMOS inverter 15.16 are formed at positions 88 and 89 where the type diffusion regions 31 intersect. Further, P-channel side MOS transistors 11.12 constituting the CMOS inverter 15.16 are formed at positions 90 and 91 where the polycrystalline silicon layers 86 and 87 intersect with the P-type diffusion region 82, respectively. In addition, the diagonally shaded portions extending downward to the right in the figure are second-layer polycrystalline silicon layers 92 and 93 containing N-type impurities.

One polycrystalline silicon layer 92 is connected to the N-type diffusion layer 81 and the P-type diffusion layer 82 through contact holes 94 and 95, respectively, and is further connected to the polycrystalline silicon layer 87 through a contact hole 96. It is connected. The other polycrystalline silicon layer 93 has a contact hole 9
7 to the N-type diffusion layer 81, and is further connected to the polycrystalline silicon layer 86 and a part of the P-type diffusion region 82 via a contact hole 98. In the figure, the diagonally shaded portions downward to the left are wiring lines 11i99 to 101 formed of aluminum, respectively. One of the wiring layers 100 is used as the one bit line, and this wiring layer 100 is connected to a part of the N-type diffusion layer 81 through a contact hole 102. The wiring layer 101 is used as the other bit line, and this wiring layer 10
1 is connected to the N-type diffusion layer 8 through the contact hole 103.
Connected to part of 1.

The wiring layer 99 is connected to the ground potential Vss, and the wiring layer 99 is connected to the N-type diffusion layer 81 via a contact hole 104.

That is, in this cell, the CMOS inverter 15.
The drains of the P-channel and N-channel MOS transistors constituting MOS transistors 16 are connected using the 211th polycrystalline silicon layer 92.93 containing N-type impurities instead of the conventional wiring layer made of aluminum. It is something. In addition, the Vss wiring layer is changed from the conventional second layer polycrystalline silicon layer to the wiring layer 9 made of aluminum.
9. As a result, the number of wiring layers made of aluminum is three per cell, and the number of wiring layers made of the second layer of polycrystalline silicon is two per cell, and the number of wiring layers made of different materials is averaged. The cell size can be smaller than that of the conventional 0MO8 type shown in FIG. 10.

In particular, the reduction in the number of wiring layers made of aluminum from the conventional four to three per cell had a significant effect, and the cell size was able to be reduced to approximately 88% of the conventional size.

Incidentally, in a cell having a pattern as shown in FIG. N-channel MoS
It is connected to the N-type expanded region 81 which is the drain of the transistor. Therefore, a PN junction diode is formed between the P type diffusion region 82 and the N type polycrystalline silicon layer 92. Therefore, as shown in FIG. 2, the equivalent circuit of this cell is between the drain of P channel MOS transistor 11 and the drain of N channel MO8 transistor 13 in FIG. A PN junction diode 2 is connected between the drain of the channel MOS transistor 14 and the drain of the channel MOS transistor 14.
7.28 is inserted with the polarity shown.

Next, CM with diodes 27 and 28 inserted like this
The electrical characteristics of the OS static RAM cell will be explained. The eighth part, in which no diode is inserted as described above,
In a cell as shown, data storage nodes 18.19
The connection state between the P-type diffusion region and the N-type diffusion region in is ohmic. However, in the above embodiment, it reflects the forward characteristics of the diode. That is, in the forward voltage (V)-current (rp) characteristic of the PN junction diode, as shown in FIG. 3, when Ip=, a voltage drop of about 0.7 V occurs in the region sandwiching the diode. Roughly speaking, the DC high level at the data storage nodes 18.19 rises only to a level that satisfies 1F>1, assuming that the leakage current at the data storage nodes 18.19 is 1. The data storage node 18
．． The leakage current at node 19 is the sum of the leakage current in the N-type diffusion region and the off-state current of the N-channel MOS transistor, and is about 10-14 A/cell, so the DC high level at data storage node 18.19 is approximately The potential is about 0.2 V lower than the power supply voltage Vcc, which is the potential at point a in the forward characteristic curve diagram of the diode shown in FIG. At this time, the P-channel MO whose gate is controlled by the signal of the data storage node on the high level side
In the S transistor 11 or 12, the gate-source voltage Vaa is approximately 0.2V, and the drain-source voltage is approximately Vcc, so the leakage current in the standby state is slightly smaller than that of a transistor without a diode inserted. To increase. However, this increase in leakage current is very small and has almost no effect on power consumption, so it has almost no effect on the operation of peripheral circuits.

Next, the AC characteristics due to the insertion of the diodes 21 and 28 will be explained. FIG. 5 qualitatively shows the rise characteristics of the other node 19 when a kink waveform as shown in the figure is input to the data storage node 18. The characteristic curve (2) of the conventional CMOS static RAM cell shown in FIG. Slightly worse. However, the conventional E/R type thruster static RAM
It is sufficiently fast compared to that of a cell, and the stability of the data storage node of a cell is sufficient.

Next, a manufacturing method for realizing the memory cell of the above embodiment as an integrated circuit will be explained. 6(a) to 7(a) to 7(l) are cross-sectional views sequentially showing the manufacturing steps in manufacturing the memory cell of the above embodiment, and the one in FIG. 1 shows a cross section along the line AB in FIG. 1, and FIG. 7 shows a cross section along the same line C-D. Note that in FIGS. 6 and 7, parts corresponding to those in FIG. 1 are given the same reference numerals for explanation. First, as shown in FIGS. 6(a) and 7(a), a P-type or N-type semiconductor substrate 1 is used as a supporting substrate.
10 is prepared, and on the surface of this substrate 110 there are a P'' type semiconductor region 111 for forming the source and drain of a channel MOS transistor and a P channel MOS transistor.
A secondary MOS forming an N-type semiconductor region 112 for forming the source and train of the S transistor.
A field insulating film 113 is formed by selectively oxidizing the surface of the substrate other than the regions where the source, drain, and channel regions of the transistor are to be formed.

Next, as shown in FIGS. 6(b) and 7(b), a P-type impurity is introduced by ion implantation into a region surrounding the region where the PN junction diode is to be formed, and is diffused by heat treatment. A P-shaped head region 114 is formed.

Next, as shown in FIGS. 6(C) and 7(C), gate oxidation is first performed to form a Goo 1-oxide film 115, and then a first layer of polycrystalline silicon is deposited. This is patterned to form the polycrystalline silicon 1183.86.87 which will become the gate electrode of the MOS transistor.

Next, as shown in FIG. 6(d) and FIG. 7(d), P-type impurity or N
The N-type diffusion region 8 is formed by selectively ion-implanting type impurities.
1 and a P-type diffusion region 82 are formed.

Next, as shown in FIGS. 6(e) and 7(e), a silicon oxide film 116 is deposited on the entire surface by, for example, CVD (chemical vapor deposition), and this silicon oxide film 116 is further deposited on the entire surface. The contact hole 97 is selectively removed.
．． 98 etc. is opened.

Thereafter, the gate oxide film 115 on the surface of the P-type head region 114 is selectively removed, and then the second layer of polycrystalline silicon is deposited on the entire surface as shown in FIGS. 6(f) and 7(f). The second polycrystalline silicon layer 92,93 is deposited on the polycrystalline silicon layer, and then N-type impurities are introduced into the polycrystalline silicon by ion implantation, phosphorus diffusion, etc., and then patterned to selectively leave the second layer. form. At this time, the N-type impurity contained in the polycrystalline silicon layer 93 is diffused into the P-type head region 114 to form an N-type diffusion region 117.

This N-type diffusion region 117 together with the P-type head region 114 constitutes the PN junction diode 21 or 28.

Thereafter, an interlayer insulating film 118 is formed by a CVD method or the like, a contact hole is opened in this interlayer insulating film 118, aluminum is further deposited on the entire surface, and then this aluminum is selectively removed to form the aluminum layer. The wiring layer 101 and the like are formed, and a protective film 119 is deposited thereon.

[Effects of the Invention] As explained above, according to the present invention, the P-type first semiconductor region and the N-type second semiconductor region are connected by a wiring layer made of polycrystalline silicon containing N-type impurities. As a result, the number of wiring layers made of aluminum is reduced compared to the conventional one, so that the cell size during integration can be reduced, and a semiconductor device with good characteristics and a method for manufacturing the same can be provided.

[Brief explanation of drawings]

FIG. 1 is a pattern plan view showing the configuration of a semiconductor device according to the present invention implemented in a memory cell, FIG. 2 is an equivalent circuit diagram thereof, and FIGS. 3 to 5 each illustrate the above-mentioned embodiment device. FIGS. 6 and 7 are cross-sectional views showing the steps for manufacturing the above embodiment device, respectively. FIGS. 8 and 9 are circuit diagrams of a conventional memory cell, and FIGS. FIG. 11 is a pattern plan view of the conventional cell described above. 27, 28... PN junction diode, 81... N type diffusion region, 82... P type diffusion region, 83.86.87
...is-th polycrystalline silicon layer, 92.93...
1st WJ polycrystalline silicon layer, 99. 100. 1
01...Wiring layer made of aluminum. Applicant's agent Patent attorney Takeshi Suzue Guo 1 Figure cc Figure 3 IK 4 Figure -
■ Fig. 5 Fig. 6 Fig. 6 Fig. 11 (J (v) < Fig. 8 Vrr Fig. 10

Claims (4)

[Claims] (1) A P-type first semiconductor region, an N-type second semiconductor region, and one of the P-type and N-type semiconductor regions provided so as to connect the surfaces of the first semiconductor region and the second semiconductor region. a wiring layer made of a conductive material containing conductivity-type impurities;
An impurity contained in the wiring layer is introduced into the first or second semiconductor region, and a PN junction diode is formed on the surface of the first or second semiconductor region to form a PN junction diode between the first or second semiconductor region. A semiconductor device comprising a P-type or N-type third semiconductor region. (2) The P-type first semiconductor region is a drain region of a P-channel MOS transistor, the N-type second semiconductor region is a drain region of an N-channel MOS transistor, and the wiring layer and the third semiconductor region 2. The semiconductor device according to claim 1, wherein both impurities contained in the semiconductor device are N-type. (3) The P channel MOS transistor and the N
Claim 2: The gate electrode of the channel MOS transistor is made of a conductive material different from that of the wiring layer.
The semiconductor device described in . (4) forming a P-type first semiconductor region in the surface region of the N-type semiconductor region provided on the support base; and forming a P-type first semiconductor region in the surface region of the P-type semiconductor region provided on the support base forming a second semiconductor region;
forming an insulating film over the entire surface including the semiconductor region surface;
selectively removing the insulating film to form openings communicating with the surfaces of each of the first and second semiconductor regions; and a conductive layer containing impurities of one of P-type and N-type conductivity on the entire surface. a conductive material is deposited, and impurities contained in the conductive material are introduced into the surfaces of the first and second semiconductor regions through the openings to form a PN junction diode between the first and second semiconductor regions. forming a P-type or N-type third semiconductor region on the surface of the first or second semiconductor region; and forming a third semiconductor region on the first or second semiconductor region while selectively leaving the conductive material deposited in the above step. 1. A method of manufacturing a semiconductor device, comprising the step of forming a wiring layer for connecting surfaces.