JPS5816564A - Complementary metal-oxide-semiconductor static memory cell - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to complementary metal-oxide-semiconductor (CMos) static memory cells.

Complementary metal-oxide-semiconductor (0MO8) integrated circuits are
Generally well known and widely used. Because the 0M08 circuit is highly resistant to "soft 7 failures" (ie, failures associated with ionized particles moving across the substrate), this technology has recently become more widely used. The 0M08 circuit also has many advantages over other MO8 technologies, such as high noise immunity over a wide range of power supply voltages and low power consumption.

The method for producing 0MO8 was provided to the applicant of the present invention.
U.S. Patent Application No. 133,58 filed March 24, 1980
No. 0, the title of the invention is "Method for manufacturing 0MO8", which is fully explained. This manufacturing method, modified as described below, is used to manufacture the memory cell of the present invention. The memory cell shown in FIG. 10 of the above invention is closest to the present invention.

The present invention uses a well-known bistable circuit (clipfron), but with other regions and a unique arrangement, it can be fabricated at higher density than conventional cells and is more resistant to cuos launch-up. A memory cell having the following structure can be provided.

As will be explained in detail with reference to FIG. 5, the latch-up problem has been a conventional problem. Normally, the CMO8 circuit is
It has a transistor-like structure with adjacent NPN or PNP regions. If parasitic transistor operation occurs, it will cause a short circuit that destroys the 0MO8 circuit. The present invention and the p-shade region reduce this latch-up problem.

The present invention provides complementary metal-
The present invention relates to an oxide-semiconductor (cMOS) static memory cell. This cell consists of an n-channel transistor and a p-channel transistor.
It has a channel transistor. A polysilicon member interconnects a source region of one of the transistors and a drain region of another of the transistors. p
A shadow region is formed in the substrate between the transistors and intersects the polysilicon member. A ground member is used to connect the p-shaded area to a predetermined potential, such as ground potential. By using p-shaded regions and crossed polysilicon features, cells can be formed on a relatively small substrate area. The launch-up path, which includes the n-fer in which the p-channel transistor is formed, the p-type substrate, and the drain of the n-channel transistor, is a critical issue. However, due to the p-shaded region, the lateral beta (current amplification factor of the lateral transistor) associated with this path
The resistance value of this passage decreases. - That is, this reduces the possibility of substrate current conduction along this path causing launch amplifiers.

Embodiments of the present invention will be described below based on the accompanying drawings.

A phase-type metal monoxide semiconductor (AUOS) static memory cell will be described based on the manufacturing process of this cell. Note that specific numerical values such as thickness in the description are for helping understanding of the present invention, and are not limited to these numerical values. In other instances, detailed descriptions of well-known structures and processes are omitted so as not to obscure the present invention.

FIG. 1 shows a well-known bistable circuit used as a memory cell. This CMO8 circuit has two crossing branches, each branch having a p-channel transistor and an n-channel transistor connected in series with a diode. Transistors 45, 46 are on line 40
and transistors 47, 48 are cross-connected via line 51. The diode 33 is
In series with transistors 45, 46, likewise diode 3
8 is connected in series with transistors 47 and 48. A node between the diode 38 and the transistor 47 is connected to the bit line via the transistor 49 and the contact 54,
Similarly, the node between diode 33 and transistor 45 is connected to the complementary bit line via transistor 5o and contact 55.

The cell of FIG. 1, including additional regions such as p-shaded regions used to reduce latch amplifiers, can be arranged in accordance with the present invention to provide a high density memory cell. FIG. 6 is a plan view showing the arrangement of memory cells of the present invention. FIG. 8 is an equivalent circuit of the memory cell shown in FIG. 6, and the same reference numbers as those used in FIG. 1 are used. 1st
As will be apparent from a comparison of this figure and FIG. 8, the circuits in these figures are equivalent.

A series transistor, for example a transistor 45.46 with an intermediate diode 33, is connected to the bistable circuit according to the invention. A method of forming these transistors will be described in FIGS. 2-5.

For convenience of explanation, these transistors are shown as being formed side by side on the substrate 10, but as shown in FIG. 6, these transistors are actually in a parallel relationship with each other. For this reason, a disconnected portion as shown in region 11 of substrate 10 is provided.

A normal p-type single crystal silicon substrate 10 is used to manufacture the memory cell of the present invention. In the first step, field oxide regions 12a-12d of FIG. 2 are formed along with n-shaped wells 13. Furthermore, this n-type Wael 13
A p shadow area 14ap14b is formed inside. What is important is that at the same time as doping regions 14a+14b, another p shadow region 1 is added between field oxide regions 12b and 12a.
It is to form a T. Although not shown in FIG. 2, a channel stop region is formed below the field oxide film region.

The method of forming the field oxide film region shown in FIG. 2, the channel stop region thereunder, and the n-type 9L/p shadow region is described in the aforementioned U.S. Pat.
3.580.

Next, as shown in FIG. 3, a gate oxide film m is formed on the substrate.
form 18. In this example, the thickness of this layer is approximately 4
It is 0OA. Openings 19,20 are formed in layer 18 adjacent each oxide region 12b+12c by conventional masking and etching processes.

Furthermore, a polycrystalline silicon (polysilicon) layer is formed on the substrate and patterned using conventional lamination techniques. Next, polysilicon member 23 and polysilicon member) 2
2.24 is formed as shown in FIG. (in fact,
22.24 is a part of a long and thin polysilicon piece. ) Polysilicon member 23 extends into opening 19.20. The n-type dopant diffuses from this member into region 14b, forming region 26. Thus area 26.14
In addition to the diode, a buried contact (ie, a contact between the polysilicon member and the substrate) is formed at the junction of the polysilicon member and the substrate. At the other end of the member 23, where the polysilicon member 23 contacts the substrate, another buried contact 30 is formed, which forms a region 27.

As shown in FIG. 5, two separate masking and doping steps are used to create the source and drain regions of transistors 45 and 46. First, transistor 46 is covered with a photoresist strip and an n-type dopant is implanted in alignment with gate 24 to form region 37. Next, remove the transistor 45 and leave the transistor 46 exposed.
A p-type dopant is implanted in alignment with gate 22 to form region 3.
form 6.

In this embodiment, regions 14a, 14b and p-type guard band dovetail 17 are formed by ion implantation or a conventional diffusion process of boron dopant. Region 36 is 1xlO
14/crn and region 37 is formed by implanting dopants at a level of 5X1015/crn'
It is formed by implanting arsenic ions at a level of .

The remaining processing steps used to complete transistors 45, 46 are well known and will not be described here.

Note that this step includes the formation of a vanishing layer and a metallization step.

As is well known, the doped regions of the 0M08 circuit form a transistor-like structure. Therefore, unless these circuits are used to prevent current from flowing through these transistor-like structures, the integrated circuit may be destroyed. The current flowing in these parasitic paths is generally called "launchup", and such a latch amplifier has a large amount of C
This is one of the main deficiencies when used in MO8 circuits.

In FIG. 5, one passage forming a transistor-like structure is shown along dotted line 60. The n-shade area of the n-type well 33, the p-shade area of the substrate, and the n-shade area 3T form np.
n) Forms a transistor. If conduction occurs in this transistor, the integrated circuit will be destroyed. To reduce the possibility of such conduction, a p shadow region 1T is formed as shown, which acts as a guard band. This region is connected to a certain potential, eg, ground. Area 1
7 reduces the lateral beta in the substrate region of this transistor, ie, the "base" of the transistor.

Furthermore, since region 17 is connected to ground, this region reduces the resistance along path 60 and reduces the possibility of launch-up due to parasitic currents along path 60.

In line 61 of FIG. 6, the memory cell of FIG. 8 is shown. In the memory cells arranged in a play shape, the area formed by the lines 61 is not rectangular as shown. The area required for each cell is approximately 68.58μ (2,7
m1l).

In FIG. 6, the polysilicon member is shown in dashed lines. The n-type well in which the p-channel transistor is formed is shown in dashed lines, and the outline of the gate oxide region is shown in solid lines.

A description of these lines is shown on the right side of FIG.

Transistors 49,50 can be easily recognized in FIG. The substrate area of these transistors is
Although not shown, it is connected to a metal line above it. One area of transistor 49 connects to one metal line via contact 54, and one area of transistor 50 connects to one metal line via contact 54.
b is connected to the other metal line via contact 55. transistor 49°
The gate at 150 is formed by an elongated piece of polysilicon. This polytricone piece is usually located perpendicular to the metal bit line.

The cell consists of two usually parallel elongated polysilicon lines 2
3.40. This line 40 is a buried contact/
Extending from the diode 38 to the buried contact 31 . This line includes gates 22 and 24 of FIG. The transistor 45 is provided along this line,
Its placement is indicated by line 5a-5a. Similarly, transistor 46 is provided along polysilicon line 40, the placement of which is indicated by line sb-sb.

One terminal of transistor 46 is connected to the other polysilicon line 23 via a buried contact/diode.

Similarly, one terminal of transistor 45 connects to buried contact 30.
It is connected to line 23 at. Another polysilicon line 23 is an offset sector 7 for transistor 47.
It has yon. One terminal of this n-channel transistor is connected to line 23 at a buried contact 32.

The p-shaded region 17 is connected to a metal line above it which is grounded at a contact 35. This contact also connects one terminal of transistor 4T to ground. Contact 34 is also used to connect one terminal of transistor 45 to another overlying metal line that is grounded. Note that the P guardband connects to the same metal line and grounds the n-channel side of this memory cell. This makes it possible to connect the guard bands extremely efficiently and to form cells with a very high density by routing the same metal lines.

The cell shown in FIG. 6 is manufactured by the steps shown in FIGS. 2-5. The mask used to form the p shadow region, including the critical guard band region 17 in FIG. 2, is shown in FIG. The position in FIG. 6 where this mask is placed is indicated by "p-mask" in FIG. Region 17 is formed by the left part of the P-mask. A recess in the upper portion of the mask (where no p-dopants are diffused) allows formation of a p-channel transistor in an n-type well.

In the cross-sectional view of FIG. 9, an elongated polysilicon line 40 is shown. One end of this line extends to contact point 38;
The other end extends to the contact point 31. This figure shows game)
22.24 is also shown.

Region 39 is connected to Vcc, providing a positive potential to the two p-channel transistors. Region 41 provides a connection from one end of transistor 48 to line 40.

Part of the P-mask in FIG.
Guard band region 17 may be doped.

As described above, in the memory cell of the present invention, which includes a bistable (flip-flop) circuit, the possibility of parasitic current flowing through the transistor-like structure is minimized by providing a p-shaded region in the circuit. Since this p-shaded region is connected to ground, a polysilicon member can be placed directly on this region, and therefore a circuit can be formed with high density.

[Brief explanation of the drawing]

Fig. 1 is an electrical circuit diagram of a well-known bistable circuit, Figs. 2 to 5 show the manufacturing process of the memory cell of the present invention, and Fig. 2 shows an n-type well, a p-shade region, and a field oxide film. 3 is a cross-sectional view of the substrate of FIG. 2 after forming an opening in the oxide layer; FIG. 4 is a cross-sectional view of the substrate of FIG. 2 after forming a polysilicon layer on the substrate and patterning this layer. FIG. 5 is a cross-sectional view of the substrate shown in FIG. 4 after the doping process, FIG. 6 is a plan view showing the arrangement of the memory cell of the present invention, and FIG. 7 is a cross-sectional view of the substrate shown in FIG. 6 is a plan view of a mask used in manufacturing the memory cell shown in FIG. 6, FIG. 8 is a circuit diagram of the memory cell shown in FIG. 6, and FIG. 9 is a cross-sectional view taken along line 9-9 in FIG. be. 10---One substrate, 12a, 12b, 12c, 12d
...-field oxide film region, 13...n-type 9L, 14a + 14b...p shadow region, 17...
. . . p shadow region, 18 . . . gate oxide film region, 19.
20... Opening, 2:3, 40... Polysilicon member, 22, . 24...Polysilicon gate, 30
．． 33...Embedded contact, 45,46.49.50.
...Transistor.

Claims (1)

Claims: (1) an n-channel transistor, a p-channel transistor spaced from the n-channel transistor, and polysilicon interconnecting the source region of one of the transistors and the drain region of the other transistor; a p shadow region formed in the substrate between the member and the spaced apart transistor and intersecting the polysilicon member;
a complementary metal-oxide film formed on a substrate characterized by a grounding member connecting the shadow area to a predetermined potential, reducing latch-up problems and forming a high density memory cell. - Semiconductor static memory cells. (2. A static memory cell according to claim 1, wherein the polysilicon member has a diode connected in series with the polysilicon member. (3) Claim 1 (4) The static memory cell according to claim 3, wherein the substrate is a p-type substrate and the p-channel transistor is formed in an n-type well. In a static memory cell, the polysilicon member terminates in an n-shaded region;
The n-shaded area is arranged such that the two transistors are interconnected via diodes connected in series with the polysilicon member (,
A static memory cell, characterized in that it is formed in one of the source and drain regions of a p-channel transistor. (5) In the static memory cell according to claim 4, the gate of the transistor has an elongated second
A static memory cell characterized by being formed of a polysilicon member. (6) A static memory cell according to claim 5, wherein the second polysilicon member is connected to a second n-channel transistor. (The static memory cell according to claim 1, wherein the grounding member includes an upper metal line that grounds one terminal of the n-channel transistor.) 8) A first p-type region formed in the substrate, a grounding member that connects this p-shaded region to a predetermined potential, and first and second long and narrow regions that intersect with the first p-type region and are spaced apart in parallel.
a polysilicon member; a first p-channel transistor disposed on a first side of the first p-type region;
a second p-channel transistor on the first side of the first p-type region; a first n-channel transistor on the opposite side of the first p-type region; a second n-channel transistor on the opposite side; a connecting member connecting the first and second p-channel transistors and the first and second n-channel transistor to form a bistable circuit; wherein the first polysilicon member forms the gates of the first p-channel transistor and the first n-channel transistor, and the second polysilicon member forms the gates of the second p-channel transistor and the second n-channel transistor. A complementary metal-oxide-semiconductor static memory cell formed on a substrate, characterized in that it forms the gate of a channel transistor, reduces latch amplifier problems and forms a high density memory cell. (9) In the static memory cell described in item 8, the second polysilicon member includes an offset section, and along this section a 2n-th
A static memory cell characterized by forming a channel transistor. (11m) In the static memory cell described in claim 9, the connecting member includes a third polysilicon member that connects the first polysilicon member to one terminal of the second n-channel transistor, and a second polysilicon member that connects the first polysilicon member to one terminal of the second n-channel transistor. 1st
A static memory cell comprising a fourth polysilicon member connected to one terminal of an n-channel transistor. (11) In the static memory cell according to claim 10, the third polysilicon member is integrated with the first polysilicon member, and the fourth polysilicon member is integrated with the second polysilicon member. Characteristic static memory cells. (12. In the static memory cell according to claim 11, the connecting member includes a fifth polysilicon member connecting the first polysilicon member to one terminal of the second p-channel transistor, and a second polysilicon member. 1st page
- A static memory cell, characterized in that it comprises a sixth polysilicon member connected to one terminal of the channel transistor. (13) In the static memory cell according to claim 12, the fifth polysilicon member is integrated with the first polysilicon member, and the sixth polysilicon member is integrated with the second polysilicon member. Characteristic static memory cells. (14) In the static memory cell according to claim 13, the fifth polysilicon member has a diode connecting the member and one terminal of the second p-channel transistor, and the sixth polysilicon member A static memory cell characterized in that it has a diode connecting said member and one terminal of a first p-channel transistor. (15) The static memory cell according to claim 14, wherein the other terminals of the first and second p-channel transistors are connected to a positive potential with respect to a predetermined potential. . (16) In the static memory cell according to claim 15, one ends of the first and second polysilicon members are terminated at one terminal of the third and fourth n-channel transistors, respectively. A static memory cell featuring: (17) A static memory cell according to claim 16, wherein the p-channel transistor is formed in an n-type well. (18) In the static memory cell according to claim 17, the first p-type region is the second p-type region.
a static memory cell, characterized in that a shaped region is present between the first and second p-channel transistors and is connected to a terminal of the second p-channel transistor for supplying a positive potential to the p-channel transistor. .