GB2098799A - Multi-level interconnection system for integrated circuits - Google Patents

Multi-level interconnection system for integrated circuits Download PDF

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Publication number
GB2098799A
GB2098799A GB8115463A GB8115463A GB2098799A GB 2098799 A GB2098799 A GB 2098799A GB 8115463 A GB8115463 A GB 8115463A GB 8115463 A GB8115463 A GB 8115463A GB 2098799 A GB2098799 A GB 2098799A
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formed
polycrystalline silicon
transistors
conductivity type
semiconductor substrate
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GB2098799B (en )
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NEC Corp
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NEC Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/11Static random access memory structures
    • H01L27/1104Static random access memory structures the load element being a MOSFET transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A high-density integrated circuit employing different first and second channel types of insulated gate field effect transistors is disclosed, which comprises at least three stacked wiring layers, the lowest layer 207, 208 being formed of polycrystalline silicon and including silicon gates of the transistors, one 211 of the upper layers being formed of polycrystalline silicon and used for feeding a power supply to some of the transistors and being connected to at least one well region on which the first channel type of transistors are formed, and the other 209, 210 of the upper layers being formed of high-conductivity metal. The upper layer 211 of polysilicon may form PN junctions with semiconductor regions of the integrated circuit where it contacts those regions. <IMAGE>

Description

SPECIFICATION Improvements in or relating to integrated circuits This invention relates to integrated circuits.

CMOS circuits have been widely used because of their low power consumption, in which P type and N type field effect transistors are employed. In general, CMOS circuit arrangement is formed on a semiconductor substrate of a first conductivity provided with well regions of a second conductivity type opposite to the first conductivity formed therein in order to arrange both of P and N channel transistors on the same semiconductor chip. In this arrangement, it is required to provide the substrate and the well region with ohmic contacts for potential sources (Vcc PO tential and Vss potential).

in the CMOS circuit, however, as is well known, a current triggered by an external noise voltage or the like flows through the substrate or the well region, and a voltage drop due to this current acts as a dominant factor deciding the degree of occurrence of a parasitic thyristor effect that is, a so-called latch-up phenomenon caused in the CMOS structure. Accordingly, methods for preventing occurrence of this latch-up phenomenon have been performed such that a part of the well region or the substrate is made a low resistance layer by increasing the impurity concentration thereof, or the supplying of potential for the well region or the substrate is effected by performing the connection with a metal having a low sheet-resistance such as aluminium with a width as large as possible in layout.

However, with the recent increases in the memory capacity and in the density of the semiconductor memory circuit arrngement, it has been required to employ fine patterning technique and/or bi-layer or stacked layer of polyscrystalline silicon structure and the like.

The above situation is the same for the CMOS memory circuit arrangement also, and particularly according to the layout of the group of memory cells, an extensive variation of chip size is caused. That is, although the mash pattern used for fabricating the circuit arrangement is subjected to the fine patterning, the contact area between a power source wiring and the well region or the substrate cannot be simply reduced in view of the latchup phenomenon.In addition, in the situation where the bi-layer polycrystalline silicon structure, for instance, the upper polycrystalline silicon layer containing N type impurities is used for a wiring for supplying the Vss power source, the direct ohmic electrical connection to a well region of P-type or a substrate of a P-type is impossible, so that it is necessary that once the N doped polycrystalline silicon is connected with a metal such as alminium, and further the metal is connected with the Ptype well or the P type substrate.As a result, although the bilayer polycrystalline silicon structure is incorporated for the purpose of effecting the high density of integration, the expected high density cannot be attained in a specified pattern, for instance, a group of memory cells because of the above mentioned indirect connection between the power source wiring and the well region or the substrate.

It is an object of the present invention to provide an integrated circuit having a highdensity of circuit structure, which may be a semiconductor memory device provided with a a large memory capacity.

The circuit may be a CMOS circuit having a high integration and operable without causing latch-up phenomena due to stray thyristor effect, suitably a CMOS type semiconductor memory device of a high-density and operable with a low power consumption.

An integrated circuit according to the present invention comprises a semiconductor substrate of a first conductivity type, at least one well region of a second conductivity type formed in said semiconductor substrate, said second conductivity type being opposite to said first conductivity type, a plurality of insulated gate field effect transistors formed on said well region and a region of said semiconductor substrate other than said well region, and at least three stacked wiring layers, the lowest layer being formed of polycrystalline silicon and including silicon gates of said transistors, one of the upper layers being formed polycrystalline silicon and serving as power supply path to the selected ones of said transistors, said one of the upper layer being connected to said well region, and the other of the upper layers being formed of highconductivity metal.

A semiconductor memory device according to the invention comprises a semiconductor substrate of a first conductivity type, a plurality of semiconductor regions of a second opposite conductivity type formed in said semiconductor substrate, a plurality of memory cells arranged in a matrix form on a matrix area of said semiconductor substrate, each of said memory cells including at least one of first insulated gate field effect transistor formed on one of said first regions and at least one of second insulated gate field effect transistor formed on an area of said semiconductor substrate other than said one of said first regions, a first level of polycrystalline silicon formed on said semiconductor substrate serving as gates of said first and second transistors, and a second level of polycrystalline silicon forming a plurality of first wirings extended over said matrix area, each of said wirings having ohmic contact with an impurity region of said first conductivity type formed in the associated semiconductor region therewith, each of said first wirings being connected to the associated semiconductor region through PN junction formed therebetween.

In the above integrated circuit, the polycrystalline silicon as the above one of the upper layers is doped with impurity of the first conductivity so that good ohmic contact is obtained between an impurity region formed in the impurity-doped region and the polycrystalline silicon. While this polycrystalline silicon as the one of upper layer is connected to the impurity doped region through a PN junction in reverse-direction formed therebetween, and hence it may be conceived that the impuritydoped region cannot be biased by the power supply through the reverse-direction PN junction, according to the prima-facie concept of the skilled in the art. However, such PN junction is favourably formed by contacting highly doped polycrystalline silicon and the highly doped contact region in the impuritydoped region and hence the PN junction is very leaky like resistors.Therefore, the impurity-doped region can be well biased by the leakage current of the PN junction so that the latch-up phenomena may be effectively prevented.

According to the present invention, it is possible to obtain a CMOS memory circuit arrangement in which a polycrystalline silicon used for a power source wiring and a well region or a substrate, which contains impurity of conductivity type opposite to that contained in the polycrystalline silicon, are connected with each other in a junction state under the notice that the latch-up phenomena is comparatively hardly caused in memory cell matrix.

The invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram illustrating a memory cell of CMOS static RAM; Figure 2 is a plan view showing a conventional layout of a part of a memory cell matrix; Fig. 3 is a plan view showing a part of a memory matrix according to one embodiment of the present invention; Fig. 4 is a cross sectional view corresponding to a line a-a' of Fig. 4; Figs. 5A to 5C are plan views respectively showing detailed layout patterns of Fig. 1; and Figure 6A to 6D are plan views respectively showing detailed layout patterns.

First, with reference to Fig. 1, a general circuit structure of a CMOS type memory cell will be briefly explained.

In Fig. 1, a memory cell is composed of Nchannel field effect transistors Q, to Q4 and Pchannel field effect transistors Q5 and Q6. The transistors Q3 and Q5 form a first inverter while the transistors Q4 and Q8 form a second inverter. An output of the first inverter and an input of the second inverter are commonly connected at a node Nt. An output of the second inverter and an input of the first inverter are commonly connected at a node N2. The transistors Q, and Q2 respectively connected between a true digit line D and the node N, and between a complement digit line D and the node N2 operate as transfer gate in response to a logic level of a word line WL.

In the following, the present invention will be explained by referring to accompanied drawings in comparison with the conventional technique, for example, in the situation where the V55 power wiring is formed of the polycrystalline doped with the N type impurity and the substrate is of N type as well as the well region is of P type.

Fig. 2 shows a conventional layout of a memory cell matrix with respect to two memory cells A and B neighbouring with each other. In this layout, one word line is formed of a laterally extended polycrystalline silicon 107. Portions 101 and 102 of the polycrystalline silicon 107 act as gates of the transfer gate transistors Q, and Q2 in Fig. 1 for the memory cell A. Similarly, portions 103 and 104 of another word line 108 act as gates of the transfer gate transistors in the memory cell B. Layouts of flip-flop circuits formed of the mentioned first and second inverters in the cells A and B are indicated by reference numerals 105 and 106 respectively. A true and complement digit lines D and D are formed of alminium wirings 109 and 110 respectively. Next, a V55 power wiring is formed of alminium wiring 111.A high impurity-concentration P type diffusion region 112 is employed for electrically connecting the P type well regions 120 with the V55 power wiring 111 through an opening provided on which region an ohmic contact is effected with the V55 power wiring 111.

In the above conventional layout, it is impossible to reduce the pattern size of the memory elements because of the limit of space in the aluminium wirings of the V55 power wiring 111 and the digit lines 109 and 110. For removing this difficulty, it may be thought that the bilayer polycrystalline silicon structure is incorporated to the memory matrix and the upper layer of polycrystalline silicon of which is used for the V55 power wiring.

However, it has been conventionally regarded as impossible to perform the connection for the P type well region with other than such a metal aluminium or a polycrystalline silicon containing the P type impurity, because of the required function of suppression of the latch up phenomenon.

In contrast thereto, according to the present invention, the above conventional concept is cleared away, and, under the notice that the latch-up phenomenon is comparatively hardly caused in the memory cell matrix, the poly crystalline silicon used for the V55 power wir ing doped with N type impurity is directly connected to the above mentioned P type well region in the junction state, whereby the latch-up phenomenon can be endured, and further the wiring limit caused by aluminium is removed, as well as the area occupied by the memory element can be reduced. As a result, the high density thereof can be attained.

With reference to Figs. 3 and 4, an embodiment of the present invention will be described.

A P type well region 220 for forming Nchannel transistors is formed within a N-type semiconductor substrate 221. As is similar in Fig. 2, transfer gate transistors Q, and Q2 of Fig. 1 are formed by the N-type polycrystalline silicon 207 as the word line, N type regions 216 and 217 as the nodes N, and N2 of Fig. 1, and N type regions 218 and 219.

To the regions 218 and 219 true and complement digit lines 209 and 210 formed of aluminium are connected through contact holes. The Vcc wirings 222 are formed by Ptype region extended to drains of the transistors Q5 and Q6 of Fig. 1.

In this figure, the V55 wirings 211 are formed of a polycrystalline silicon which is formed on the layer above the silicon layer forming the word lines 207 and 208 and doped with N-type impurity. The digit line 211 is connected to an N type regions 213 and 214 coupled to the sources of the transistors Q3 and Q4 through contact holes 215, this connnection is performed by a ohmic contact between the same conductivity (N) type silicon layer 211 and region 214. In other words, the conductivity type of the silicon 211 is determined so as to provide a current between the regions 213 and 214 and the V55 wiring 211. The polycrystalline silicon wiring 211 is also directly connected to a P + contact region 212 formed in the P type well region 220 through a contact hole.

The polycrystalline silicon wiring 211 is admitted to be superposed on a part of the digit line wirings 210 and 209 formed of aluminium.

Thus, continuous and simple wirings are provided from the starting point to the ending point of the memory cell matrix, and further an aluminum wiring for the ohmic contact with the P type diffusion layer can be avoided. The polycrystalline silicon wirings 211 so that the wiring limit caused by the aluminum V55 wiring can be removed, whereby the pattern area occupised by each memory cells can be reduced. Under this circumstance, it can be regarded equivalently that a diode 213 is inserted between the P type well 220 and the V55 power wiring 211 with a forward-direction from the P type well towards the V55 power wiring 211.

In other words, in view of supplying the V55 power to the well region 220, the diodes 213 operate in a reverse-direction to block the current to the well region 220 and hence biasing of the well region 220 is not performed due to the prima-facie concept. However, condition of PN junction of the diodes 213 is not in essentially ideal in view of PN function but is rather leaky like resistors. This seems to be caused by the junction between the highly doped N type polycrystalline silicon (211) and the highly doped P + region 212.

Therefore, the P-type well region 220 can be sufficiently biased by the diode 213.

Furthermore, in the case that these diode are employed only for the memory cell matrix where the latch-up phenomenon is comparatively hardly caused, even if these diodes have insufficient current performance, many of similar diodes are connected in parallel in the memory cell matrix, any difficulty is scarcely caused in a state of practical use.

As is apparent from the above, according to the present invention, the high density integration of the CMOS memory circuit arrangement, particularly, inside the memory cell matrix thereof can be attained.

Next, with reference to Figs. 5 and 6, the description will be made on detailed layout example and effect of the present invention in comparison with the conventional layout.

In the following explanation, the same layout rule is applied to the layouts of Figs. 5 and 6, where each contact hole is formed with a rectangular share of 2.4 um X 2.8 ym and aluminum wirings have their width of 3.7 clam A polycrystalline silicon wirings as the word lines and interconnection in the flipflop circuits are of 3.3 /lm width. In Figs. 5 and 6, the same reference numerals and codes are utilized to indicate portions as those of Figs. 1 to 4 for better understanding.

Throughout Figs. 5A and 5C which slow the conventional technique corresponding to Fig. 2, marks " +" are used to indicate reference points for layout aligning.

The P well region 120 and the respective P and N type impurity-doped regions are shown in Fig. 5A, with respect to neighbouring two memory cells. Areas denoted by Q, to Q6 are channel regions correesponding to the transistors Q, to Q6 of Fig. 1. Fig. 5B shows a layout pattern of the first level polycrystalline silicon with which the word lines 107 and 108 and interconnections 131 and 132 for forming the flip-flop circuit are formed. Fig. 5C shows a layout of aluminum wirings 109 and 110 as the digit lines D and D, and the V55 lines 111.

Wirings 141 and 142 are to connect the polycrystalline silicone wiring 131 and 132 to the P type and N type regions with ohmic contacts.

As shown in Fig. 5C, in the conventional layout of the memory cell matrix corresponding to Fig. 2, each of the memory cells is arranged in a rectangular region having a length of 37 um and a width of 41.4 ym. In this layout, wirings 151 and 152 forming circuit connections as well as gates of the transistors Q3 to Q6 are made of the same level of polycrystalline silicon of N-type as the word lines 107 and 108.

With reference to Figs. 6A to 6D, the detailed layout patterns of the respective layers according to the present invention will be described.

The layout of the P well region 220 and the respective impurity regions are shown in Fig.

6A.

The regions denoted by the reference codes Q, to Q6 are the channel regions conesponding the transistors Q, to Q6 of Fig. 1. The P type region 222 is used to feed the Vss power supply to the memory cells.

Fig. 6B shows a layout of the first level of the poycryst alline silicon forming the word lines 207 and 208, and the interconnection wirings 231 and 232 forming the flip-flop circuit of the memory cell.

Fig. 6C shows a layout of the aluminum wirings. The wirings 209 and 210 form the word lines D and D The wirings 241 and 242 are contact connection between the wirings 231, 232 and the impurity regions.

Fig. 6D shows the second level of porycrystalline silicon introduced by the present invention. In this example, for reducing a resistance, the polycrystalline silicon 211 is formed in a mesh-like manner along the peripheral edge of the respective memory cells.

Through the contact 215, the polycrystalline silicon 211 is connected to the N type region 214 while through the contact 216, the polycrystalline silicon 211 is also directly connected to the P + contact region in the D well region 220.

As shown throughout Figs. 6A to 6D, especially in Fig. 6D in the layout according to the embodiment of the present invention, each of the memory cells is formed on a relatively small region having a length of 37 #m and a width of 32.5 #m. In this layout, the wirings 251 and 252 for connecting the transistors Q3 to Q6 are formed of the same level of polycrystalline silicon as those for the word lines 207 and 208. As described above, according to the present invention, about 22% of reduction in size can be achieved in the memory cell matrix without loosing the latchup phenomena suppression function.

Although the above embodiment is described regarding the situation where the Vss power wiring formed of the polycrystalline silicon with the N type impurity, the N type substrate and the P type well regions are employed, the matter can be similarly effected by connecting the P-type polycrystalline silicon with the N type diffusion layer forming a part of the N type well even in the situation where the V55 power formed of the polycrystalline silicon doped with the P type impurity, the P type substrate and the N type well regions are employed on the contrary.

Claims (12)

1. An integrated circuit comprising a semiconductor substrate of a first conductivity type, at least one well region of a second conductivity type formed in said semiconductor substrate, said second conductivity type being opposite to said first conductivity type, a plurality of insulated gate field effect transistors formed on said well region and a region of said semiconductor substrate other than said well region, and at least three stacked wiring layers, the lowest layer being formed of polycrystalline silicon and including silicon gates of said transistors, one of the upper layers being formed of polycrystalline silicon and serving as power supply path to the selected ones of said transistors, said one of the upper layer being connected to said well region, and the other of the upper layers being formed of high-conductivity metal.
2. The circuit according to claim 1, in which said polycrystalline silicon forming said one of the upper layers is doped with impurity of said first conductivity type.
3. The circuit according to claim 1, in which said polycrystalline silicon forming the lower layer is doped with impurity of said first conductivity type.
4. A semiconductor memory device comprising a semiconductor substrate of a first conductivity type, a plurality of semiconductor regions of a second opposite conductivity type formed in said semiconductor substrate, a plurality of memory cells arranged in a matrix form on a matrix area of said semiconductor substrate, each of said memory cells including at least one of first insulated gate field effect transistor formed on one of said first regions and at least one of second insulated gate field effect transistor formed on an area of said semiconductor substrate other than said one of said first regions, a first level of polycrystalline silicon formed on said semiconductor substrate serving as gates of said first and second transistors, and a second level of polycrystalline silicon forming a plurality of first wirings extendend over said matrix area, each of said wirings having ohmic contact with an impurity region of said first conductivity type formed in the associated semiconductor region therewith, each of said first wirings being connected to the associated semiconductor region through a PN junction formed therebetween.
5. The device according to claim 4, further comprising a plurality of second wirings extended over said matrix area for transferring logic data, said second wirings being formed of high-conductivity metal.
6. The device according to claim 4, in which said second level of polycrystalline silicon is doped with impurity of said first conductivity type.
7. The device according to claim 6, in which said first level of polycrystalline silicon is doped with impurity of said first conductivity type.
8. The device according to claim 4, in which said first and second wirings are extended in parallel over said matrix area.
9. An intergrated circuit comprising a semiconductor substrate of a first conductivity type, at least one first semiconductor region of a second opposite conductivity type formed in said semiconductor substrate, at least one of first insulated gate field effect transistor formed on said first semiconductor region, at least one of second insulated gate field effect transistor formed on an area of said semiconductor substrate other than said first semiconductor region, a first level of polycrystalline silicon forming a silicon gate of said first transistor, a metal wiring for transferring data derived from at least one of said first and second transistors, and a second level of polycrystalline silicon doped with impurity of said first conductivity type and supplied with a power potential, said second level of polycrystalline silicon being connected to said first semiconductor region through a PN junction formed between said second level of polycrystalline silicon and said first semiconductor region and having an ohmic contact with one of said source and drain of said first transistor.
10. A memory integrated circuit comprising a semiconductor substrate of a first conductivity, a memory cell matrix formed on a matrix area of said semiconductor substrate, said memory cell matrix including a plurality of memory cells arranged in rows and columns a plurality of well regions of a second opposite conductivity formed on at least said matrix area, each of said memory cells including a flip-flop circuit having a pair of load transistors and a pair of switching transistors, and a pair of transfer gate transistors, said pair of switching transistors and said pair of transfer gate transistors being of the same channel conductivity and formed on one of said well regions, said pair of load transistors being formed on a part of said matrix area separate from and near said one of said well regions, and at least three stacked wiring layers, the lowest layer being formed of polycrystalline silicon and including silicon gates of said transistors, one of the upper wiring layers being formed of polycrystalline silicon serving as a power supply path to said flipflop circuits and connected to said well regions, and the other off the upper wiring layers being formed of high-conductivity of metal and including a plurality of data lines formed on said matrix area.
11. The circuit according to claim 10, in which said polycrystalline silicon as said one of the upper wiring layers is doped with impurity of said first conductivity type.
12. An integrated circuit constructed, arranged and adapted to operate substantially as hereinbefore described with reference to, and as illustrated in, the accompanying drawings.
GB8115463A 1981-05-20 1981-05-20 Multi-level interconnection system for integrated circuits Expired GB2098799B (en)

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GB8115463A GB2098799B (en) 1981-05-20 1981-05-20 Multi-level interconnection system for integrated circuits
GB8424243A GB2144580B (en) 1981-05-20 1984-09-25 }interconnection system for integrated circuits}

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GB2098799B GB2098799B (en) 1985-08-21

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0087979A2 (en) * 1982-03-03 1983-09-07 Fujitsu Limited A semiconductor memory device
GB2157886A (en) * 1984-04-18 1985-10-30 Gen Electric Co Plc Semiconductor devices
EP0192093A1 (en) * 1985-01-30 1986-08-27 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
FR2616966A1 (en) * 1987-06-22 1988-12-23 Thomson Semiconducteurs Structure mos transistors power

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0087979A2 (en) * 1982-03-03 1983-09-07 Fujitsu Limited A semiconductor memory device
EP0087979A3 (en) * 1982-03-03 1986-01-08 Fujitsu Limited A semiconductor memory device
US4809046A (en) * 1982-03-03 1989-02-28 Fujitsu Limited Semiconductor memory device
GB2157886A (en) * 1984-04-18 1985-10-30 Gen Electric Co Plc Semiconductor devices
EP0192093A1 (en) * 1985-01-30 1986-08-27 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US4907059A (en) * 1985-01-30 1990-03-06 Kabushiki Kaisha Toshiba Semiconductor bipolar-CMOS inverter
FR2616966A1 (en) * 1987-06-22 1988-12-23 Thomson Semiconducteurs Structure mos transistors power
EP0296997A1 (en) * 1987-06-22 1988-12-28 Sgs-Thomson Microelectronics S.A. Power mos transistors structure
US4890142A (en) * 1987-06-22 1989-12-26 Sgs-Thomson Microelectronics S.A. Power MOS transistor structure

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Effective date: 20010519