JPS6117166B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a FET differential width circuit, and more particularly, to a FET differential width circuit that can be manufactured by a normal semiconductor process, is easily monolithic, has a high operating speed, and has a wide operating voltage range. The purpose is to obtain a widening circuit.

In order to configure a digital circuit and an analog circuit on the same semiconductor substrate, such as an IC for a voice synthesis circuit, it is essential to realize an arithmetic amplification circuit with high input impedance and fast response speed. Although it is possible to meet such requirements by employing bi-Mos technology, the manufacturing process becomes extremely complicated and costs are inevitably high.

The present invention was made against this background.

First, an example of a conventional FET differential amplifier circuit will be given, and problems with such a conventional example will be explained.

The FET differential amplifier circuit shown in Fig. 1 consists of a pair of enhancement type first and second FETs Q ₁ , with depletion type FETs Q ₆ and Q ₇ serving as resistive drain loads.
Q ₂ is connected to a common source, and this common source is connected to ground via the source-drain channel path of the third FET Q ₃ , and further, the third FET Q ₃
A constant current power supply is connected to the gate of the depletion type 4th FET Q ₄ and an enhancement type 5th FET Q ₅ are vertically connected to give a constant bias, and the differential amplified output of inputs I ₁ and I ₂ is connected to the gate of The configuration is such that it can be extracted as a differential output between O ₁ and O ₂ .

However, in such a conventional configuration, (a) the input voltages I ₁ and I ₂ are
It does not operate below the threshold voltage of . FET Q ₁
If Q 2 and Q ₂ are made depletion type, this problem will be solved, but the gain will be considerably reduced.

(b) When the input voltages I ₁ and I ₂ approach the power supply voltage V _DD , the gain rapidly decreases and the device becomes unusable.

(c) Since FETs Q ₆ and Q ₇ are resistive loads, in order to increase the gain, it is necessary to considerably increase the gain constant β of FETs Q ₁ and Q ₂ , but in order to do so, parasitic This increases the capacity and causes a reduction in speed when multiple stages of differential amplifiers are connected. Therefore, when designing a high-speed operational amplifier, connect multiple stages of high-speed differential amplifiers with relatively small gains to obtain a reasonably large differential output, and use the level shift circuit and output DC Output is obtained through an amplification circuit, but
In this case as well, since the signal passes through several amplification stages, it is difficult to avoid speed reduction. The present invention has been made in view of the drawbacks of the conventional example.

The details of the present invention will be explained below with reference to an embodiment shown in FIGS. 2 and 3.

The FET differential amplifier circuit of the present invention basically has first and second voltage generation circuits 1 and 2 that function as a pair of level shift circuits with the same characteristics, and level shift outputs of the corresponding voltage generation circuits. High-gain first and second phase-inverting amplification circuits with uniform characteristics as inputs 1
1, 12, a negative feedback connection 21 from the first phase inversion amplification circuit 11 to the first voltage generation circuit 1, and a quasi-negative connection 21 from the first phase inversion amplification circuit 11 to the second voltage generation circuit 2. and a return connection 22.

The first and second voltage generating circuits 1 and 2 are each of a depletion type (or an enhancement type).
It consists of vertically connected FETs F ₁₁ and F ₁₂ or F ₂₁ and F ₂₂ . Each voltage generation circuit is connected to the lower stage FET F ₁₁ (or
The input applied to the gate of F ₂₁ ) is level-shifted, and its drain output is supplied as an input to the corresponding phase inversion amplification circuit 11 (or 12).

The first and second phase inversion amplifier circuits 11 and 12
is constituted by an inverter as shown in FIG. 3A or a push-pull inverter as shown in FIG.

By connecting the output of the first phase inverting amplification circuit 11 to the gate of the upper stage FET F ₁₂ of the first voltage generating circuit 1 through negative feedback, the output level of the first voltage generating circuit 1 can be changed to 1 phase inversion amplifier circuit 11
can be set near the threshold value.

As described above, the first and second phase inversion amplifier circuits 11,
Since 12 is composed of a push-pull inverter with high gain and uniformity characteristics, the output of the first phase inversion amplification circuit 11 is connected to the gate of the upper stage FET, _F12, of the second voltage generation circuit 2. By providing the quasi-negative feedback connection 22, the output level of the second voltage generation circuit 2 can be made close to the operating threshold level of the corresponding second phase inversion amplification circuit 12.

By making the FETs F ₁₁ , F ₁₂ , F ₂₁ and F ₂₂ depletion type and setting β to an appropriate value, the voltages V _I1 and V of the input I ₁ I ₂ can be
When _I2 changes from V _SS to V _DD , the feedback voltage Vo ₁ can be set so as not to exceed V _SS (or V _DD ).

As mentioned above, since the gain A of both phase inversion amplifier circuits 11 and 12 is set to be considerably large, FET F ₁₂ is controlled by the output of the first phase inversion amplifier circuit 11 in response to the input voltage V _I1 . NF controlled, FET F ₁₁
becomes stable when the drain output V _X1 becomes approximately equal to the threshold voltages of the first and second phase inversion amplification circuits 11 and 12. Next, the operation of the implementation circuit shown in FIG. 2 will be quantitatively explained.

In the circuit of Fig. 2, FETs F ₁₁ , F ₁₂ ,
There is no problem whether F ₂₁ and F ₂₂ operate in the saturated region or the non-saturated region, but in the following explanation they are all depletion type (the threshold voltage is assumed to be V _TD ).
Assume that the gain constants β are all equal and that F ₁₁ F ₂₁ operates in the non-saturated region and F ₂₁ operates in the saturated region.

_{If the current condition is that V _} ) The current flowing through FET _F12 is _ID = 1/2 x β x (V _O1 - V _TC - V _TD ) ² ... (2) Since both are equal, becomes.

Next, taking the case of V _TC = 1/5V _DD and V _TD = -1/3V _DD as an example, and looking at the relationship between V _I1 and V _O1 , (i) When V _I1 = V _SS , V _O1 = 0.172× _VD
D (ii) When V _I1 = 1/2V _DD , V _O1 = 0.409×V _D
D (iii) When V _I1 = V _DD, V _O1 = 0.569×V _D
It becomes _D.

Therefore, the input operating point changes from V _SS to V _DD in this way.
It can be seen that the output operating point can be well controlled even if the output varies up to . Now, next is voltage generation circuit 1.
Or consider a gain of 2.

Similar to equation (1), the current flowing through the FET _{and F21} is _ID = β × V _X2 × (V _I2 −V _{TD −1} / _{2V −V TD −V X2 ) × △ V} −V _X2 −V _TD ) ² ……………(6) ∴ △I _D =−β _× ( _{V O1 −V} From both equations, the gain A _{V of} voltage generation circuit 1 or 2 is A _V = △V _X2 / △V _I2 = _{V X2} / _{( 2V} Calculating the gain for the example case, we get
(However _, when V _X2 〓V _TC , V _I2 〓V _I1 ) (i) When _{V I2 〓V I1} = _{V SS} A _V = -0.170 (iii) V _I2 〓V _I1 = V _DD When A _V = -0.109 In order for the circuit in Figure 2 to function as a differential amplifier, A _V ×A must be significantly larger than 1. is necessary. If the operating point of inputs I ₁ and I ₂ is close to V _DD , the gain is small and disadvantageous, but since the output operating point approaches 1/2 V _DD , the differential amplifier of the present invention is used in the next stage. When connected, it is possible to obtain a larger gain than the previous stage.

Since the present invention has the above-mentioned configuration, it is possible to
The MOS transistor manufacturing process makes it possible to realize a low-cost differential amplifier circuit with high operating speed and wide operating voltage range. Additionally, it is resistant to parameter fluctuations and temperature changes, always operates near the operating point as an amplifier circuit, and has the effect of operating effectively even at low power supply voltages. .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional example of this type of FET differential amplifier circuit. 2 and 3 relate to the FET differential amplifier circuit of the present invention, FIG. 2 is an implementation circuit diagram, and FIG. 3 is a main part circuit diagram.

Claims (1)

[Claims] 1 First and second with a pair of vertically connected FETs
It is equipped with a level shift circuit, and first and second FET phase inversion amplification circuits each having the same electrical characteristics, and the output of the first phase inversion amplification circuit which receives the output of the first level shift circuit as an input is connected to the output of the first phase inversion amplification circuit. The second level shift circuit is directly connected to the gate of the FET that operates as a load among the FETs constituting the first level shift circuit to provide negative feedback, and also supplies input to the second phase inversion amplifier circuit. The output of the first phase inverting amplification circuit is supplied to the gate of the FET forming the load, and
A FET differential amplification circuit configured to derive a differential output for two inputs of a second level shift circuit from between the output terminals of the first and second phase inversion amplification circuits.