JPS61170198A - Data link bit switching circuit - Google Patents

Abstract

PURPOSE:To transfer a data link bit to an optional path by adding a data link bit inserting circuit and a data link bit separation circuit so as to replace a time slot not only for a main signal but also the data link bit. CONSTITUTION:The data link bit transmitted from transmission lines 1a-1d is separated from the main signal by incoming data link bit separation circuits 2a-2b. Then the input side data bit insertion circuit 3 inserts the separated data link bit into a data link time slot in the main signal. Then a write address circuit 5, a temporary storage device 6 and a read address circuit 7 replace the time slot. The data link bit in the data link time slot is separated by an output side data link bit separation circuit 8. Output side data link bit insertion circuits 10a-10d couple the main signal and the data link bit and output result to transmission lines 11a-11d. Thus, the data link bit is transmitted to an optional path by controlling the read counter of the read address circuit 7.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a time slot switching device for temporally switching the order of time slots, and particularly to a data link defined for communication between devices in a digital transmission system. The present invention relates to a data link bit switching circuit that effectively transmits bits.

[Prior Art] Conventionally, the main signal is sequentially loaded into a temporary storage device and read out randomly, or written randomly and read out sequentially, and the time slot of the main signal is changed. The slot switching device uses the primary group (1°544 Mb/II) or the secondary group (6,31 Mb/II) to transfer the data link bits defined for communication between devices.
The data and link bits on the 2 Mb/B) transmission line are separated and output to an external terminal, and then transferred by making a strap connection to the data link bit input terminal of the transmission line to be transferred.

[Problem that the invention seeks to solve].

However, in conventional circuits that transfer data link bits using strap connections, the strap connections are used for external terminals, so it is extremely difficult to change the initial connection settings, and the data link bits of a single transmission path are very difficult to change. It also had drawbacks such as the difficulty of inserting it into multiple other transmission lines.

[Failure to solve the problem]

The data link bit switching circuit according to the present invention is used in a time slot switching device that switches time slots of the main signal by sequentially writing and randomly reading a main signal into a temporary storage device, or randomly writing and reading out the main signal sequentially. A data link bit insertion circuit that inserts the data link bit defined in □ into a specific time slot in the main signal, and a data link bit insertion circuit that separates the data link bit inserted into a specific time slot in the main signal. The data link bit separation circuit is also provided with a data link bit separation circuit.

[Effect]

In this invention, as hardware, the main signal time is 71- for slot replacement
Since the hardware can be shared, data link bits can be transferred to any strategy with a simple configuration.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a data link bit switching circuit according to the present invention.

In the figure, 1a to 1d are transmission lines through which input signals are sent, and 2a to 2d are input side data that separate the main signal and data link bits from the input signals sent through these transmission lines 1a to 1d. Link bit separation circuit, 3 is an input side data link bit insertion circuit that inserts a data link bit into a specific time slot, 41 to 4d are input side insertion circuits, 5 is a write address circuit that outputs a data write address, 6 is a temporary 7 is a read address circuit that outputs a data read address; 8 is an output side data link bit separation circuit that separates a data link bit from a specific time slot; 91 to 9d are output side separation circuits;
Reference numerals 10a to 10d are output side data link bit insertion circuits that combine the main signal and data link bits and send them to transmission lines 11a to 11d.

Next, the operation of the data link bit switching circuit with the above configuration will be explained. First, the transmission line 1a1dK data "A-II, n B II, II C"
+1 D Q ;' ++ When EII is sent in order, these data "A".

B", "C"+'l p ++ +' W E l"
is input to the temporary storage device 6 via the input side data link bit separation circuits 2a to 2d and the input side insertion circuits 4a to 4d. At this time, the write address circuit 5 sequentially sends address signals Ao r AI r A2 + A3! A
4 is outputted and input into the temporary storage device 6. Therefore, this temporary storage circuit 16 stores data "An" at address 0, data "B" at address 1, and data 6C" at address 2.
Data "D" is written to address 3, and data "'E" is written to address 4 in order.Next, the read address circuit 7 writes J@
Next address signal A4 + AI + A3 +
When Ao + A2 is output to the temporary storage device 6, the data “E ++” at address 4 is sequentially output from this temporary storage device R6 as follows.
The data “B′” at address 1 is the data “D ++” at address 3.
is data n at address 0 A++ is data n at address 2
Since CI+ is read, the data “lpH, IIBI
I, DII, fi Al1. It is possible to read data ``AII'' to 1m of the data ``AII''.
II B ++ , W Cl”, D”, E′′ to data “EII, n B II, +1 D +
+, 'A'' * C1'' can be realized.

On the other hand, data link bits sent through transmission lines 1 to 1d are input to data link bit separation circuits 2a to 2.
It is separated from the main signal by d. Then, the input side data bit insertion circuit 3 inserts this separated data link bit into the data link time slot in the main signal. Then, as described above, the write address circuit 5
．． The temporary storage device 6 and the read address circuit T exchange the time slots. Then, the data link bits in this data link time slot are separated by the output side data link bit separation circuit 8. and,
The output side data link bit insertion circuits 10a to 10d combine the main signal and the data link bits to form a transmission line 11a.
~ Output to 11d. In this way, by controlling the read counter (not shown) of the read address circuit 7, data link bits can be sent to any route.

〔Effect of the invention〕

As explained in detail above, according to the data link bit switching circuit according to the present invention, by adding the data link bit insertion circuit and the data link bit separation circuit in the time slot switching circuit, not only the main signal but also the data link bit switching circuit can be used. The data link bits also have the advantage of being able to exchange time slots and transfer the data link bits to any route.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data link bit switching circuit according to the present invention. 1a to 1d...Transmission path, 2a to 2d...Input side data link bit separation circuit, 3...Input side data link bit insertion circuit, 4a to 4d...Input side insertion circuit, 5...Write address circuit, 6...Temporary storage circuit, 7...Read address circuit, 8...
Output side data link bit separation circuit, 9a-9d...
-Output side separation circuit, 10a to 10d-.e.Output side data link bit insertion circuit, 11a to 11d...Transmission line.

Claims (1)

[Claims] In a time slot switching device that switches the time slots of the main signal by sequentially writing and randomly reading the main signal into a temporary storage device, or by randomly writing and reading out the main signal sequentially, the data link bit defined in the frame is The present invention is characterized by comprising a data link bit insertion circuit that inserts into a specific time slot in the main signal, and a data link bit separation circuit that separates the data link bit inserted into the specific time slot in the main signal. data link bit switching circuit.