JPS61170197U - - Google Patents

Info

Publication number
JPS61170197U
JPS61170197U JP5305085U JP5305085U JPS61170197U JP S61170197 U JPS61170197 U JP S61170197U JP 5305085 U JP5305085 U JP 5305085U JP 5305085 U JP5305085 U JP 5305085U JP S61170197 U JPS61170197 U JP S61170197U
Authority
JP
Japan
Prior art keywords
dynamic ram
chip
flowchart showing
ram
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5305085U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5305085U priority Critical patent/JPS61170197U/ja
Publication of JPS61170197U publication Critical patent/JPS61170197U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Electromechanical Clocks (AREA)
  • Static Random-Access Memory (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面はこの考案の一実施例を示し、第1図はこ
の考案を適用した電子腕時計のブロツク回路図、
第2図は第1図で示したダイナミツクRAMの記
憶状態図、第3図はこの電子腕時計の動作の概要
を示すジエネラルフローチヤート、第4図は第3
図のキー処理(ステツプS)の具体的内容を示
したフローチヤート、第5図は第3図のアラーム
処理(ステツプSの)の具体的内容を示したフ
ローチヤートである。 1……ワンチツプLSI、10……スタテイツ
クRAM、11……ダイナミツクRAM。
The drawings show one embodiment of this invention, and Figure 1 is a block circuit diagram of an electronic wristwatch to which this invention is applied.
Fig. 2 is a memory state diagram of the dynamic RAM shown in Fig. 1, Fig. 3 is a general flowchart showing an overview of the operation of this electronic wristwatch, and Fig. 4 is a diagram of the memory state of the dynamic RAM shown in Fig. 1.
FIG. 5 is a flowchart showing specific details of the key processing (step S 2 ) in the figure. FIG. 5 is a flowchart showing specific details of the alarm processing (step S 5 ) in FIG. 1...One-chip LSI, 10...Static RAM, 11...Dynamic RAM.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] スタテイツクRAMとダイナミツクRAMとを
1チツプ内に設けたことを特徴とする半導体チツ
プ。
A semiconductor chip characterized in that a static RAM and a dynamic RAM are provided in one chip.
JP5305085U 1985-04-10 1985-04-10 Pending JPS61170197U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5305085U JPS61170197U (en) 1985-04-10 1985-04-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5305085U JPS61170197U (en) 1985-04-10 1985-04-10

Publications (1)

Publication Number Publication Date
JPS61170197U true JPS61170197U (en) 1986-10-22

Family

ID=30573548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5305085U Pending JPS61170197U (en) 1985-04-10 1985-04-10

Country Status (1)

Country Link
JP (1) JPS61170197U (en)

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