JPS61170122A - Analog multiplexer - Google Patents

Abstract

PURPOSE:To minimize an input/output error by passing each analog input through a quantity comparison circuit, a sequence decision circuit, a channel switching signal output circuit and a decode circuit so as to form a channel switching signal. CONSTITUTION:The quantity comparison circuit 20 compares the quantity of analog inputs 9, 10, 11. Then the sequence decision circuit sequences the analog inputs 9, 10, 11 in the small quantity order and decides to switch a channel in this order. Then a signal outputting the analog input 9 is lost at a prescribed time, e.g., at the converting time of an A/D converter and a signal outputting the analog input 11 is outputted from the sequence decision circuit 21. Thus, a channel switching signal output circuit 22 and a decode circuit 23 are operated to close the switch 12 and to conduct a switch 14. Finally, a signal outputting only the analog input 10 is outputted from the sequence decision circuit 21 and the channel switching signal output circuit 22 and the decode circuit 23 to conduct the switch 13 only.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a multiplexer that selects and outputs one from two analog inputs in a multi-channel A/1) conversion system, particularly the output order thereof. It's about decisions.

[Conventional technology]

FIG. 3 is a block diagram of a multi-channel A/D conversion system. In the figure, (1) is an analog multi-channel input signal, (2) is an analog multiplexer, (3) is a channel switching signal, (4) is an analog multiplexer output signal, (5) is a sample and hold device, (61 *
A held device output signal, (7) is an A/D converter, and (8) is a digital output signal.

The operation of the above system is as follows. Analog multi-channel input signals M (11 are always input simultaneously to the analog multiplexer (2). By switching the output channel of the analog multiplexer (2) with the channel switching signal (3), one of the input signals 11) One is selectively output as an analog multiplexer output signal (4). The sample and hold device (5) uses the analog multiplexer output signal (4) as the hold device output signal (6), and converts the analog multiplexer output signal (4) to the A/D converter (7).
Hold for the time required to convert.

The A/D converter digitally converts the hold device output signal (6) and outputs a digital output signal (8).

The onboard multi-channel A/D conversion system converts a large number of analog signals into digital signals by time-sharing and using only one A/D converter.

FIG. 4 is a schematic diagram showing the operating principle of a conventional analog multiplexer. An example of a three-channel analog multiplexer will be described below, but the same applies to analog multiplexers with other numbers of channels. (9+, (l(2), aIl is an analog input, and the above three parties generate an analog multi-channel input signal (
1) is configured. az, a row, (141 is a switch. Switch control signal QJ Switch control signal 0
61. The channel switching signal (3) is composed of the three switch control signals 071. (21, (41 are the same as those in the multi-channel A/D conversion system configuration diagram in FIG. 3.The operation of the conventional analog multiplexer is shown below.

Analog input (9) goes into switch 03, switch 1
When 2 is conductive, it is output as an analog multiplexer output (4). The switch 02 is conductive when the switch control signal 0 is ON, and is non-conductive when the switch control signal is 0FFO. Analog human power Ql, switch 031. Switch control signal +161
One set of 5 analog human power U, switch 041. The switch control signal +171 constitutes one set and operates in the same way. Analog input (9), analog human power 01. Analog human power O9
is always applied, and the switch control signal (I9
only (IN → switch control signal OG only ON → switch control signal αη only ON) Channel switching signal (3)
By switching the analog multiplexer output signal (4), the analog input (9) → analog input 0
An analog multi-channel input signal +11 is input in a time-division manner in the order of I→analog input (Ill).

[Problem that the invention seeks to solve]

In the above multi-channel A/D conversion system.

In the analog multiplexer (2), when switching the channel switching signal (3), the analog multi-channel input signal (
1), the analog multiplexer output signal (4) exhibits a tracking delay. Also, sample hold device (5)
Similarly, however, the hold device output signal (6) exhibits a follow-up delay with respect to changes in the analog multiplexer output signal (4). These are caused by the internal capacitance of the device and the combined resistance of input and load (and cannot be removed).

FIG. 5 is a schematic diagram showing the state of each signal before and after channel switching in the analog multiplexer. (41+6
1 (91Ql (Ill is the same as that in Figures 3 and 4. Ua is the input/output error when the analog human input OI is input and the hold device output signal (6) is regarded as the output. ■ is the analog This is the input/output error with respect to input ON.

Before time t1, analog multiplexer output signal (4)
Assume that the analog input (9) is output as follows.

The channel switching signal (3) is switched so that the analog input section is output at time t1. Then, as the analog multiplexer output signal (4), a signal delayed with respect to the analog input a1 is output as shown in FIG. Here, when the sample and hold device (5) holds the time at 1t2, a value with an input/output error of 0 seconds is held, and is further converted and outputted by the A/D converter (7). This input/output error Q81 increases as the potential difference between the analog input (9) and the analog input OI increases, and as the waiting time Δt from time t1 to time t2 decreases. ~
This is because the total processing time of a multi-channel A/D conversion system is generally limited.

It is often not possible to extend the waiting time. Furthermore, it is assumed that an analog input (ill) is output at time t3 and held at 2:1t4.The input/output error at this time is αl.

In the conventional analog multiplexer, the channel switching signal (3) is applied externally, regardless of the analog multi-channel input/output signal i11. For example, as shown in Figure 5,
Assume that the switching is done in the order of analog input (9) → analog manual OI → analog input +111. At this time, the input/output error α rise and the input/output error 0 depend on the potential difference between the analog input (9) and the analog human power OI, and the potential difference between the analog input (lI and the analog human power αD), respectively, and the improvement is The problem was that there was no room.

This invention was made in order to solve such problems, and is based on the analog multi-channel input/output signals (1
), change the order of the channel switching signal (3) according to
Analog input (9), analog input section.

By arranging and switching the analog inputs (111 in descending order), the purpose is to minimize the potential difference between each analog signal, and thus the input/output error θ& and the input/output error 09.

[Means for solving problems]

The multiplexer according to the present invention generates a channel switching signal by passing each analog input through a magnitude comparison circuit, an order determining circuit, a channel switching signal output circuit, and a decoding circuit.

[For production]

In this invention, the input potential difference before and after switching is minimized because the channels are switched in descending order of each analog input using the signals generated by the magnitude comparison circuit and the order determining circuit. Therefore.

Input/output errors can be minimized.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention, (4
) and (9) to αη are exactly the same as those of the conventional device. (A) is an analog input (9) and an analog human input θ analog input (a magnitude comparison circuit that compares the magnitude of the potential of Il+, C11l is an order determining circuit that determines the order of channel switching, @ is a channel switching signal output circuit, c !3 is a decoding circuit for converting the signal from the channel switching signal output circuit (c) into switch control signal 0, switch control signal -, and switch control signal planes.

The operation of the analog multiplexer configured as described above will be explained below. The magnitude comparison circuit (2) compares the magnitude of the analog input (9) and the analog human input (1) to (fill). Next, in the order determining circuit, the analog input (9), the analog manual input, and the analog input 1111 are ordered in descending order, and it is determined that the channels are to be switched in this order. For example, in the input state as shown in FIG. 5, the analog input (9) is the first, the analog input αB is the second, and the analog input On is the third.

First, 11fI order determination circuit (analog input from in (9)
A signal is issued to output the . In response to this, the channel switching signal output circuit (2) outputs a signal for outputting the analog input (9) as the analog multiplexer output signal (4). This signal is converted by the decoding circuit (c) so that only the channel control signal 09 is turned on, and the switch α2 is made conductive. Next, after a certain period of time 9, for example, the conversion time of the A/D converter, the signal for outputting the analog input (9) disappears, and a signal for outputting the analog human power 011 is output from the order determining circuit Qυ. As a result, switch 0 closes, and the decoding circuit (c) of the channel switching signal output circuit operates so that switch 0 becomes conductive. Finally, a signal to output only analog Q (1) is sent from the order determining circuit.

The decoding circuit of the channel switching signal output circuit operates so as to make only the switch αy conductive.

FIG. 2 shows a circuit diagram showing an embodiment of the present invention. (Foundation), I251. (c) is a comparator, and if the other input is thicker than the base input, it is TTL.
If the level is "H", a voltage of "L" is output if it is small. @, (c), the wire is a delay circuit, and the input is TTL
After a certain period of time has passed since the level becomes “H”, the output changes to “
I-1". The symbol R is the reset input, and when this reset input becomes "H", the output becomes "L" regardless of the input.

〔Effect of the invention〕

In addition to the above, this invention can switch the input channels of multiple analog inputs that change randomly by simply adding a magnitude comparison circuit, a sequence determination circuit, a channel output circuit, and a decoding circuit to a conventional analog multiplexer. This has the effect of optimizing the order and minimizing input/output errors during A/D conversion.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing an embodiment of the invention, Fig. 3 is a block diagram of a multi-channel A/D conversion system, and Fig. 4 is a conventional FIG. 5 is a schematic diagram showing the state of each signal before and after channel switching in the analog multiplexer. In the figure, (l) is an analog multi-channel input signal,
(2) is an analog multiplexer, (3) is a channel switching signal -q, +4) is an analog multiplexer output signal, (5) is a sample/hold device, (6) is a hold device output signal, (7) is an A/D Converter, (8) is digital output signal, (9) is analog input, Ql is analog input. 011 is an analog input, α2 is a switch, and Ql is a switch. ■ is a switch, 051 is a switch control signal, 0e is a switch control signal, on is a switch control signal, 0 & is an input/output error, a9 is an input/output error, ■ is a magnitude comparison circuit, C1υ
is an order determining circuit, (aZ is a channel switching signal output circuit, (c) is a decoding circuit, 241 is a comparator,
The bad thing is the comparator, c! +il is comparator, c17
IH delay circuit (281 is a delay circuit, @ is a delay circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A magnitude comparison circuit that compares the magnitude of multiple analog inputs, an order determination circuit that determines the order in which input channels are switched based on information from this magnitude comparison circuit, and a channel switching signal sent to a decoding circuit according to the order determined by this order determination circuit. An analog multiplexer comprising: a channel switching signal output circuit that outputs a signal for outputting a signal.