JPS61170112A - Fist order active phase equalizer - Google Patents

Abstract

PURPOSE:To make the titled device suitable for circuit integration by adding a signal fed back to an input terminal and a signal outputted via a buffer circuit and applying voltage-current conversion to the result so as to decrease number of components and simplify the circuit. CONSTITUTION:The signal fed back to the input terminal TA via a capacitor C and the signal outputted via the buffer circuit 20 are added by a resistance adder circuit 30. Then the added output is inputted to a negative phase voltage- current converter 10. Transistors (TRs) Q1-Q7 constitute the negative phase voltage-current converter 10, TRs Q8, Q9 applies a current Ix fed externally, a TRQ10 constitutes the buffer circuit 20 and resistors RA, RB are resistors being an adder circuit 30 to the input terminal TA. Further, current sources S1-S3 are formed at the inside of the IC substrate and current sources S01, S02 are formed externally. In a circuit shown in figure known as a Gilbert amplifier,the mutual conductance gm between the input terminal TA and an output terminal TB is expressed as 1/2R.(Ix/I). Thus, since the gm is adjusted by the current Ix of the current sources S01, S02 fed externally, the phase charactristic not affected by the absolute error of the internal resistors in circuit integration is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase equalizer, and particularly to a primary active phase equalizer suitable for IC implementation.

[Conventional technology]

A television signal processing circuit often requires a filter circuit that improves the frequency characteristics of a signal waveform and a phase equalizer that compensates for the phase.

Figure 4 shows such a phase equalizer (hereinafter referred to as an equalizer)
In this block diagram, 1 is a voltage-to-current conversion circuit configured by a differential amplifier circuit, etc., 2 is a buffer circuit with a gain of 1, and 3 is a phase inversion circuit with a gain of 1. .

In this figure, the input signal of input terminal T1 is Vin+output terminal T. ■ Output signal of. , when the mutual coductance g11 of the voltage-current conversion circuit 1 is 1/r, holds true. (where ω is the frequency of the signal) From equation (1), the following can be obtained.

This equation (2) is ω. = 1/cr, the phase characteristics of the input signal Vin and the output signal vo are shown by a curve with fC (cutoff frequency) being the frequency of 90' phase rotation, as shown in FIG.

[Problem that the invention seeks to solve]

By the way, such a primary active equalizer is
At least three amplifier circuits are required when converting to C, which increases the number of elements.

The present invention provides a primary active equalizer that simplifies the circuit configuration and reduces power consumption by reducing the number of elements when integrated into an IC.

[F-stage to solve problems]

In this invention, a first signal fed back to an input terminal via a capacitor and a signal output via a buffer circuit are added by a resistor adding circuit, and the added output is input to a voltage-to-current converter with an opposite phase. This constitutes a primary active equalizer.

[Effect]

In order to add a predetermined phase characteristic, the fed-back signals are added by a simple resistance adder circuit and then input to the reverse phase voltage-current converter, eliminating the need for a phase inverting circuit. is simplified.

Therefore, in particular, it becomes easy to implement IC.

〔Example〕

Fig. 1 shows a block diagram of the primary active phase equalizer of the present invention, in which 10 is a voltage-current converter to which a signal is input to the opposite phase terminal, and although not shown in the figure, it is mutually controlled by an external control signal. The conductance glI=1/r changes. 20 can be an emitter follower circuit, etc.
& is a buffer circuit with a gain of 1, 30 is an adder circuit composed of a resistor, and C is a capacitor.

In this circuit, assuming that there is attenuation in L/ in the adder circuit 10, the same holds true as in FIG. 4 above. (ω
−Receiving frequency Therefore, is obtained.

If this equation (4) and the above equation (2) are compared by 1, ω
. = 1/cr K, and the cutoff frequency f
c is low to 1/K.Then, its phase 4I property is the second
As shown in the figure, the phase of the output is reversed by 180°.

However, since the phase inversion circuit 1 can be omitted, there is an effect that the IC circuit is simplified as will be described later.

Note that K is 2 in normal addition, but can be set to any value greater than 2 depending on the configuration of the adder circuit.

FIG. 3 is a basic circuit diagram constructed based on the block diagram of FIG. A transistor, Q + o, which supplies a current Ix supplied from the outside to a point / is a transistor, RA, which constitutes the heffer circuit 20.

Re is the resistance that becomes the adder circuit 30 for the input terminal TA, and C
is a capacitor.

Note that sl, s2. s3 is a current source inside the IC board, S0
1. S02 is a current source formed externally.

The first differential amplifier circuit constituting the voltage-current converter 10 is formed by transistors Q+ and 'Q2, and transistors Q3. Q4 as a load, and transistors Q5. and Q4 forming a second differential amplifier circuit. An output voltage is supplied to Q6, and the output of this m2 differential amplifier circuit supplies an output current from the output terminal T11 to the transistor Q1o connected in an emitter-follower manner.

Since such a circuit is well known as a Gilbert amplifier, a detailed explanation will be omitted, but it is given by the mutual conductance between the input terminal T8 and the output terminal TB.

Therefore, the current source S01゜S02 supplied from the outside
Since the mutual conductance gm can be adjusted by the current value Ix, it is possible to provide a phase characteristic that is not affected by the absolute value error of the internal resistance in IC implementation. Note that if the resistance RA and the resistance R11 are made equal, the addition coefficient is 1/
= 1/2, and a symmetrical phase characteristic is realized around ωC.

By the way, the primary active equalizer of the present invention can of course be made into a secondary active equalizer by cascading two stages.

In this case, generally, the can I/off frequency of the first primary equalizer connected in two stages is ω1 (the capacitor is C+),
If the cutoff frequency of the second primary equalizer is ω2 (the capacitor is C2), then the can of the secondary equalizer (・
The off-frequency fc(ω,) is ωC=r 〒−v 石郎
......(5). Then, from the above equations (5) and (B), Q indicating the change around the phase becomes as follows.

Therefore, a low value of Q(
A second-order active filter with Q = 0.5) is ω
1-ω2 has the advantage that it can be easily configured.

Further, at this time, the input/output phases are again inverted by 180°, so it is particularly suitable as an equalizer for phase compensation for a second-order or J2 low-pass filter.

〔Effect of the invention〕

As described above, the primary active phase equalizer of the present invention has the advantage that when integrated into an IC, the number of elements is smaller than that of the conventional primary active phase equalizer, and the circuit is simplified. Furthermore, if the addition count K of the addition circuit can be set to a large value, the level at the input terminal (TA) becomes small, which has the advantage of being able to handle large input levels.

[Brief explanation of drawings]

- Figure 1 is a block diagram showing the principle of the primary active phase equalizer of the present invention, Figure 2 is a phase characteristic diagram of the input/output of the primary active phase equalizer of the present invention, and Figure 3 is the same as Figure 1. FIG. 4 is a block diagram of a conventional primary active phase equalizer, and FIG. 5 is an input/output phase characteristic diagram of FIG. 4. In the figure, 10 is a voltage-current converter, 20 is a bumper circuit,
30 is an adder circuit. Proceedings (Volunteer) April 1985) GoJ, rJ

Claims (1)

[Claims] a first signal fed back to the input terminal via the capacitor;
a resistor adder circuit that adds a second signal supplied to the output terminal via the buffer circuit; and an antiphase resistor adder circuit that receives the addition output signal of the resistor adder circuit and supplies current to the buffer circuit and the capacitor. A primary active phase equalizer comprising a voltage-current conversion circuit.