JPS61170025A - Formation of diffusion layer - Google Patents
Formation of diffusion layerInfo
- Publication number
- JPS61170025A JPS61170025A JP1012685A JP1012685A JPS61170025A JP S61170025 A JPS61170025 A JP S61170025A JP 1012685 A JP1012685 A JP 1012685A JP 1012685 A JP1012685 A JP 1012685A JP S61170025 A JPS61170025 A JP S61170025A
- Authority
- JP
- Japan
- Prior art keywords
- impurity
- temperature
- diffusion
- semiconductor substrate
- diffusion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 title claims abstract description 53
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 239000012535 impurity Substances 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000010894 electron beam technology Methods 0.000 claims description 4
- 230000004907 flux Effects 0.000 claims description 2
- 238000009826 distribution Methods 0.000 abstract description 13
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 3
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体素子の製造時等に利用される拡散層の形
成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for forming a diffusion layer used in the manufacture of semiconductor devices.
（従来技術とその問題点）
半導体素子の製造時等には、半導体基板に拡散層全形成
することが重要な工程として含まれることが多い。従来
、拡散層を形成する方法としては、（１） 不純物を
イオン注入して、基板表面に導入し、それら全押込み拡
散する方法や
（２）基板上に、不純物を含んだエピタキシャル層を堆
積させる方法。(Prior Art and its Problems) During the manufacture of semiconductor devices, forming a complete diffusion layer on a semiconductor substrate is often included as an important step. Conventionally, methods for forming a diffusion layer include (1) ion implantation of impurities, introducing them into the substrate surface, and then fully diffusing them; and (2) depositing an epitaxial layer containing impurities on the substrate. Method.
等が知られている口
これらの方法のうち、前記（１１の方法では、不純物を
導入した基板は、均一な一定温度の電気炉中で押込み拡
散される。基板中の不純物分布は、同相拡散によシ決定
される。例えば、ｐ形基板にｎ形不純物を拡散させる場
合には、イオン注入によシ導入した不純物の総址と、電
気炉の温度と拡散時間とで決ｔｂ、一般には第２図の不
純物分布図に示されるようにガウス分布、もしくはコン
プリメンタリ−エラー関数分布となることが知られてい
る。Among these methods, the impurity-introduced substrate is injected and diffused in an electric furnace at a uniform constant temperature.The impurity distribution in the substrate is determined by in-phase diffusion. For example, when diffusing n-type impurities into a p-type substrate, it is determined by the total amount of impurities introduced by ion implantation, the temperature of the electric furnace, and the diffusion time. As shown in the impurity distribution diagram of FIG. 2, it is known that a Gaussian distribution or a complementary error function distribution occurs.
しかしながら、半導体素子の製造時には、拡散層中の不
純物濃度が一定の拡散層が望ましい場合が多い。例えば
、Ｐ形基板ＫＮ形拡散ウェルを形成してＣＭＯＳを製造
する場合を考える。この場合、Ｎ形拡散つェル中にＰＭ
ＯＳトランジスタが形成される。第２図に示したような
不純物分布を有するＮ形拡散ウェルでは、ウェル表面の
Ｎ形不純物濃度が高く、基板内はどＮ形不純物濃度が低
くなっている。そのため、Ｎ形拡散つェル中のＰＭＯ８
）ランジスタについて考えた場合、Ｐ形基板とＮ形拡散
ウェルとの界面からの空乏層が拡が９やすいから、Ｐ形
基板とＰＭＯ８） 、’ンジスタがパンチスルーしやす
いという欠点や、弐面濃度が高くなるためＰＭＯ８）ラ
ンジスタの閾値電圧が制御しにくい等の欠点がある。However, when manufacturing semiconductor devices, it is often desirable to have a diffusion layer in which the impurity concentration in the diffusion layer is constant. For example, consider the case where a CMOS is manufactured by forming a KN type diffusion well on a P type substrate. In this case, PM in the N-type diffusion well
An OS transistor is formed. In an N-type diffusion well having an impurity distribution as shown in FIG. 2, the N-type impurity concentration on the well surface is high, and the N-type impurity concentration inside the substrate is low. Therefore, PMO8 in the N-type diffusion well
) When considering transistors, the depletion layer from the interface between the P-type substrate and the N-type diffusion well easily expands, so the P-type substrate and PMO8) have the disadvantage that the resistor easily punches through, and the concentration on the other side is Since the PMO8) transistor threshold voltage becomes high, there are drawbacks such as difficulty in controlling the threshold voltage of the transistor.
これらの欠点を克服する手段として、前記（２）の方法
が用いられる０この方法では前記（１１の方法に比較し
て、均一濃度の拡散層を形成することが可能である。し
かしながら、エピタキシャル成長工程は、半導体素子製
造工程において、製造コストが高い工程であることが知
られている。また１例えば、ＣＭＯＳ工程を考えると、
素子の分離のため、エピタキシャル層を貫通させて基板
と同じ極性の拡散層を形成することも必要となる。この
ように、前記（２）の方法においてもいくつかの欠点が
ある。As a means of overcoming these drawbacks, method (2) is used. This method makes it possible to form a diffusion layer with a uniform concentration compared to method (11). However, the epitaxial growth process It is known that manufacturing costs are high in the semiconductor device manufacturing process.For example, considering the CMOS process,
In order to separate the elements, it is also necessary to form a diffusion layer having the same polarity as the substrate by penetrating the epitaxial layer. As described above, the method (2) also has some drawbacks.
（発明の目的）
本発明は、前記の拡散層の形成方法の持つ欠点を克服し
、安価な製造コストで、簡単に均一な不純物分布を有す
る拡散層を形成する方法を提供することを目的とする〇
（発明の構成）
本発明による拡散層の形成方法では
１、半導体基板上に不純物を導入し、該不純物を導入し
た側の半導体基板面の温度を、該不純物の拡散が進行す
る温度に設定し、該不純物を導入しなかった側の半導体
基板面の温度を、該不純物の拡散が進行しない温度に設
定した状態で、該不純物を拡散させること、又は。(Objective of the Invention) An object of the present invention is to overcome the drawbacks of the above-described method for forming a diffusion layer, and to provide a method for easily forming a diffusion layer having a uniform impurity distribution at a low manufacturing cost. Yes (Structure of the Invention) In the method for forming a diffusion layer according to the present invention, 1. an impurity is introduced onto a semiconductor substrate, and the temperature of the surface of the semiconductor substrate on the side where the impurity is introduced is set to a temperature at which diffusion of the impurity progresses. and diffusing the impurity while the temperature of the surface of the semiconductor substrate on the side where the impurity is not introduced is set to a temperature at which diffusion of the impurity does not proceed.
２、半導体基板上に不純物を導入し、パルス状のレーザ
ー光、ランプ光、電子ビーム等のエネルギー束を用いて
、該不純物を導入した側の半導体基板面の温度を、該不
純物の拡散が進行する温度に等制約に設定し、該不純物
を導入しなかった側の半導体基板面の温度を該不純物の
拡散が進行しない温度に１等価的に設定した状態で該不
純物を拡散させることから構成される。2. An impurity is introduced onto a semiconductor substrate, and the temperature of the semiconductor substrate surface on the side where the impurity is introduced is controlled by using energy flux such as pulsed laser light, lamp light, or electron beam, and the diffusion of the impurity progresses. The impurity is diffused while the temperature of the semiconductor substrate surface on the side where the impurity is not introduced is equivalently set to a temperature at which diffusion of the impurity does not proceed. Ru.
（本発明の原理）
本発明は、従来性なわれてきた、均一温度電気炉中での
拡散を行なわず、半導体基板中に温度勾配をつけた状態
、又は１等価的に半導体基板が温度勾配を有するような
状態で不純物の拡散を行なうことを特徴とする。インタ
ーナショナル・エレクトロン・デバイス・ミーティング
（Ｉｎｔｅｒｎａ−１ｉｏｎａｌ Ｅｌｅｃｔｒｏｎ
Ｄｅｖｉｃｅ Ｍｅｅｔｉｎｇ）テクニカルダイジェ
ストｓ １９８１年、６６頁に、リー等（Ｊ、 Ｙ、
Ｍ、 Ｌｅｅ、 Ｒｅ Ｈ，Ｂｒｏｗｎ、 Ｒ，Ｄｏ
Ｂｔｃｈｅｌｌｓ。(Principle of the present invention) The present invention does not perform diffusion in a uniform-temperature electric furnace, as has conventionally been done, but instead creates a semiconductor substrate with a temperature gradient, or equivalently, a semiconductor substrate with a temperature gradient. It is characterized in that the impurity is diffused in such a state that . International Electron Device Meeting
Device Meeting) Technical Digests 1981, p. 66, Lee et al.
M, Lee, Re H, Brown, R, Do
Btchels.
Ｊ＊ Ｇｒｉｎｂｅｒｇ、 Ｇｏ Ｒｅ Ｎｕｄｄ、
ａｎｄ Ｐａ Ａｓ Ｎｙｇａａｒｄ）によるアルミニ
ウムの熱マイグレーシヨンを利用した配線技術について
の報告がある。これは１本発明の構成に類似して、半導
体基板に温度勾配をつけて処理するものである。しかし
、り一等の報告は、その物理現象が金属の熱マイグレー
シヨンに起因していること、半導体基板を貫通する配線
層を形成することｔ−特徴としている。一方、本発明は
固体甲の不純物の拡散現象を利用し、半導体素子の拡散
層を形成することを特徴としている。J* Grinberg, Go Re Nudd,
and Pa As Nygaard) have reported on wiring technology using thermal migration of aluminum. This is similar to the configuration of the present invention, in which a semiconductor substrate is processed with a temperature gradient applied thereto. However, Ri et al.'s report states that the physical phenomenon is caused by thermal migration of metal, and that it is characterized by the formation of a wiring layer that penetrates the semiconductor substrate. On the other hand, the present invention is characterized in that a diffusion layer of a semiconductor element is formed by utilizing the diffusion phenomenon of impurities in a solid shell.
これらの点で１本発明はり一等の報告とは原理が異なっ
ている。In these respects, the principle of the present invention differs from that reported by the author.
本発明は不純物を導入した側の半導体基板面を、不純物
の拡散が進行するような温度に設定し、不純物を導入し
なかった側の半導体基板面を、不純物の拡散が進行しな
いような温度に設定した状態。In the present invention, the semiconductor substrate surface on the side into which impurities are introduced is set at a temperature that allows impurity diffusion to proceed, and the semiconductor substrate surface on the side where impurities are not introduced is set at a temperature at which impurity diffusion does not proceed. The set state.
つまシ、半導体基板内で前記のような温度勾配が生じる
状態において、または１等価的に、半導体基板内で前記
のような温度勾配が生じる状態において不純物の拡散を
行なう。第１図にその例を示す。第１図（、）は、Ｐ形
基板にＮ形不純物をイオン注入により導入した図で、本
発明による拡散層を形成する前の状態である。第１図（
ｂｌは、本発明によシ拡散層を形成した後の状Ｂを示し
、第１図（ｄは、本発明を実施するだめの一例となる半
導体基板の厚さ方向の温度分布を示している。半導体素
子の製造に利用している。リン、ヒ素、ボロン等の不純
物は温度が８００℃程度ならば、買時間程度の拡散を行
なりてもほとんど不純物は移動しない。In other words, the impurity is diffused in a state where the above-described temperature gradient occurs within the semiconductor substrate, or equivalently, in a state where the above-described temperature gradient occurs within the semiconductor substrate. An example is shown in FIG. FIG. 1(,) is a diagram in which N-type impurities are introduced into a P-type substrate by ion implantation, before the diffusion layer according to the present invention is formed. Figure 1 (
bl shows the state B after forming the diffusion layer according to the present invention, and FIG. It is used in the manufacture of semiconductor devices.If the temperature of impurities such as phosphorus, arsenic, and boron is about 800°C, almost no impurities will be moved even if diffusion is performed for about an hour.
そこで、第１図（Ｃ）のように基板中に温度勾配をつけ
、形成したい拡散層の深さまで不純物が拡散するのに必
要な時間よシ十分長く拡散を行なえば、拡散が進行する
温度領域内の不純物は濃度勾配がなくなるまで拡散する
＠その結果拡散時間に依存せず、第１図（ｃｌの温度分
布で一義的に決まる第１図（ｂ）のような深さに、拡散
層を自己整合的に形成することが可能である。Therefore, as shown in Figure 1 (C), if a temperature gradient is created in the substrate and the impurity is diffused for a long enough time to diffuse to the depth of the desired diffusion layer, then the temperature range in which the diffusion will proceed can be improved. The impurities in the layer diffuse until the concentration gradient disappears.@As a result, the diffusion layer is not dependent on the diffusion time, and the diffusion layer is It is possible to form it in a self-aligned manner.
（実施例）
以下１本発明の実施例について述べる。第１図１ｃ）の
様な温度勾配を静的に実現するには、半導体基板の片面
全ランプやヒーター等で加熱し、半導体基板のもう一方
の片面を冷却すれば容易に実現できる。(Example) An example of the present invention will be described below. Static temperature gradients such as those shown in FIG. 1c) can be easily achieved by heating one side of the semiconductor substrate with a lamp or heater, etc., and cooling the other side of the semiconductor substrate.
また、等価的に第１図（ｃｌの様な温度勾配を実現する
方法としては、例えば、パルス状のレーザー光、ランプ
光、電子ビーム等のエネルギー束を使うこともできる。Furthermore, as a method for equivalently achieving a temperature gradient as shown in FIG.
パルス状のレーザー光、ランプ光、電子ビーム等のエネ
ルギー強度、照射のくり□返し周波数を調整して、半導
体基板の片面に照射すれば、等価的に第１図（ｃ）の温
度勾配を半導体基板につくることができる。By adjusting the energy intensity of pulsed laser light, lamp light, electron beam, etc. and the repetition frequency of irradiation and irradiating one side of the semiconductor substrate, the temperature gradient shown in Figure 1(c) can be equivalently achieved by adjusting the energy intensity of pulsed laser light, lamp light, electron beam, etc. It can be made on a substrate.
本発明によれば、安価な製造コストで、拡散時間に依存
せず、半導体基板内の温度分布で一義的に決まる深さを
有する拡散層を形成することが可能となる。その結果１
例えばＣＭＯＳプロセスにおける拡散ウェルの深さを浅
くできる、ラッチアップ耐圧を増加させられる等の効果
を得ることができる。According to the present invention, it is possible to form a diffusion layer having a depth that is uniquely determined by the temperature distribution within the semiconductor substrate, without depending on the diffusion time, at low manufacturing cost. Result 1
For example, the depth of a diffusion well in a CMOS process can be made shallow, the latch-up breakdown voltage can be increased, and other effects can be obtained.
第１図は、本発明の原理を示す図で、第１図（ａｌは、
本発明による拡散層の形成前の状態を示す不純物分布図
、第１図（ｂ）は本発明によゆ拡散層を形成した後の状
態を示す不純物分布図、第１図（ｅ）は、本発明を実施
するだめの一例となる半導体基板の厚さ方向の温度分布
を示す図である。
第２図は従来方法によシ形成した拡散層の不純物分布を
示す図である〇
寥 １ 図
（ｂｌ
不話セ↑刀１【２Ｊ口からの９９１７条さ 〔μｍ〕（
ｃ）FIG. 1 is a diagram showing the principle of the present invention.
FIG. 1(b) is an impurity distribution diagram showing the state before the formation of the diffusion layer according to the present invention, FIG. 1(e) is an impurity distribution diagram showing the state after forming the diffusion layer according to the present invention, FIG. 3 is a diagram showing a temperature distribution in the thickness direction of a semiconductor substrate, which is an example of a device for implementing the present invention. Figure 2 is a diagram showing the impurity distribution of the diffusion layer formed by the conventional method.
c)
Claims (1)
た側の半導体基板面の温度を、該不純物の拡散が進行す
る温度に設定し、該不純物を導入しなかった側の半導体
基板面の温度を、該不純物の拡散が進行しない温度に設
定した状態で、該不純物を拡散させることを特徴とする
拡散層の形成方法。 ２、半導体基板上に不純物を導入し、パルス状のレーザ
ー光、ランプ光、電子ビーム等のエネルギー束を用いて
、該不純物を導入した側の半導体基板面の温度を、該不
純物の拡散が進行する温度に等価的に設定し、該不純物
を導入しなかった側の半導体基板面の温度を、該不純物
の拡散が進行しない温度に、等価的に設定した状態で、
該不純物を拡散させることを特徴とする拡散層の形成方
法。[Claims] 1. An impurity is introduced onto a semiconductor substrate, the temperature of the surface of the semiconductor substrate on the side where the impurity is introduced is set to a temperature at which diffusion of the impurity progresses, and the impurity is not introduced. A method for forming a diffusion layer, comprising diffusing the impurity while the temperature of the surface of the semiconductor substrate on the side is set to a temperature at which diffusion of the impurity does not proceed. 2. An impurity is introduced onto a semiconductor substrate, and the temperature of the semiconductor substrate surface on the side where the impurity is introduced is controlled by using energy flux such as pulsed laser light, lamp light, or electron beam, and the diffusion of the impurity progresses. The temperature of the semiconductor substrate surface on the side where the impurity is not introduced is equivalently set to a temperature at which diffusion of the impurity does not proceed.
A method for forming a diffusion layer, which comprises diffusing the impurity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1012685A JPS61170025A (en) | 1985-01-23 | 1985-01-23 | Formation of diffusion layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1012685A JPS61170025A (en) | 1985-01-23 | 1985-01-23 | Formation of diffusion layer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61170025A true JPS61170025A (en) | 1986-07-31 |
Family
ID=11741592
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1012685A Pending JPS61170025A (en) | 1985-01-23 | 1985-01-23 | Formation of diffusion layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61170025A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003514377A (en) * | 1999-11-01 | 2003-04-15 | ジェテック インコーポレーテッド | Rapid heat treatment method for substrates |
| JP2019079894A (en) * | 2017-10-24 | 2019-05-23 | 住友重機械工業株式会社 | Heat treatment apparatus and heat treatment method |
-
1985
- 1985-01-23 JP JP1012685A patent/JPS61170025A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003514377A (en) * | 1999-11-01 | 2003-04-15 | ジェテック インコーポレーテッド | Rapid heat treatment method for substrates |
| JP2019079894A (en) * | 2017-10-24 | 2019-05-23 | 住友重機械工業株式会社 | Heat treatment apparatus and heat treatment method |
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