JPS61169937A - Expansion system of microprocessor instruction - Google Patents

Abstract

PURPOSE:To reduce the capacity of memory to be used sharply by using a specific instruction as an expanded instruction. CONSTITUTION:When the instruction is read from an objective program storing means 101 to a microprocessor 100, the instruction is decoded by a logic circuit in a physical instruction analyzing means 106. The decoded signal is decomposed to a signal corresponding to the instruction and the signal is executed by an instruction executing means 107 except restart. A signal 122 is obtained by decoding a restart instruction which is the 1st byte of expanded instructions and executed by a restart executing means 108 and then the address of an expanded instruction analyzing means 103 is set up in an address register 109. The means 103 analyzes the 2nd byte of the expanded instructions. A return address setting means 104 decides the instruction length of the expanded instructions and sets up the leading address of the instruction next to the expanded instructions on the objective program as a return address and an expanded instruction executing means 105 executes the expanded instructions analyzed by the means 103.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an instruction extension method for a microprocessor.

(Prior Art) Conventionally, programs for microprocessors are written using an assembly language in which instructions have a one-to-one correspondence with the machine language of the microprocessor, and a compiler language (such as C0DOL, FOTRAN, etc.) in which instructions are written using higher-level instructions. ) and those that use an interpreter method to process high-level instructions while translating them during execution (such as Ba5ic) are typical examples.

However, compiler and interpreter methods do not have a one-to-one correspondence with the microprocessor's machine language, so they can create instructions relatively freely, whereas assembler language has a higher degree of freedom in creating instructions than the microprocessor's physical instruction words ( Machine 1
11') Limited to IIC.

(Problems to be Solved by the Invention) As mentioned above, the present invention solves the problem that the instruction extension method of the assembly language is limited by the machine language of the microprocessor, and executes the extension instruction using a specific instruction. The present invention provides a microprocessor instruction extension method that can reduce the memory capacity required by a program by creating new extension instructions as a possible configuration.

(Means for Solving Problems) The system of the present invention includes an instruction analysis means for analyzing an instruction, and when the instruction analysis means detects that the instruction is a predetermined specific instruction, the specific instruction and its subordinate parts are analyzed. return address setting means for setting a memory address for storing an instruction to be executed next following execution of the special instruction consisting of;
a special instruction analysis means for receiving and analyzing the special instruction; and executing the special instruction based on the analysis result of the special instruction analysis means and transferring execution to the instruction stored at the return address after execution. and a special instruction execution means, and is configured to extend and execute the specific instruction into the special instruction.

(Example) Next, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of the present invention.

Usually, by incorporating a microprocessor system into various devices and writing the functions of the device as a program to be executed by the microprocessor, the functions can be changed relatively freely. Here, such a device function description program is referred to as a target program.

In FIG. 1, reference numeral 101 indicates a target program storage means for storing a target program. An address is given to the means 101. Reference numeral 102 is an extended instruction management storage means included in the target program for managing extended instructions, and includes extended instruction analysis means 103. Return address setting means 104. and extended instruction execution means 105, and successive addresses are set in an address register 109. Note that the target program storage means 101 and the extended instruction management storage means 1
An address different from 02 is set, and whether the target program storage means 101 or the extended instruction management storage means 102 is to be read is determined by the contents of the address register 109.

Next, when the instruction from the target program storage means 101 is read into the microprocessor 100, it is coded by the logic circuit of the physical instruction analysis means 106, decomposed into signals corresponding to the instruction, and the instruction execution means 107 other than restarting.
is executed. The signal 122 is a signal obtained by decoding the restart instruction corresponding to the first byte of the extended instruction of this embodiment (in this embodiment, a restart instruction is taken as an example of an extended instruction), and is executed by the restart execution means 108. As a result, the address of the extended instruction analysis means 103 is set in the address register 109.

The extended instruction analysis means 103 analyzes the second byte of the extended instruction. Next, the 1 return address setting means 104 determines the instruction length of the extended instruction and sets the starting address of the next instruction of the extended instruction on the target program as the return υ address. The extended instruction execution means 105 is a means for executing the extended instruction analyzed by the extended instruction analysis means 103.

FIG. 2 is a detailed block diagram of FIG. 1. The reference numeral 2 in FIG. 2 is an IFi microprocessor unit, and the reference numeral 2 is a memory section serving as storage means. Further, FIG. 5 shows details of this memory section 2, and FIG. 6 shows the stored contents of the memory section. In Fig. 6, Fig. 6(a) is a read-only memory section, where data uniquely corresponds to addresses due to circuit connections, and addresses and data are expressed using hexadecimal numbers. has been done. No. 6 (Contest) is a read/write memory section that can be freely written and written by the microprocessor, and the contents shown are at a certain point in time during processing, and may change as the processing progresses. . 7 and 9 represent the contents of the memory in association with instructions of the microprocessor.

Next, extended instructions will be explained. Extended instructions exist in the target program, and include restart instructions and extended instruction analysis unit 5.
0. Return address setting unit 51 and extended instruction execution unit 52
It is an instruction that can only obtain the function of an instruction by combining it with the function of . If extended instructions are written and executed on the target program without the above combination, the microprocessor will be unable to normally execute the target program at the time the extended instructions are read.

Next, the operation of the extended instruction will be explained.

Figure 7 shows a flag set program written in machine language and the corresponding assembly/pull language.From the top of Figure 7, the extended instruction analysis section, return address setting section, and extended instruction execution section are written. These are examples of a part, a part of an object program, and a variable part. In FIG. 7, the address part on the left side is an address part expressed in hexadecimal, and the object part is a program written in the machine language of the microprocessor, which corresponds to the contents of FIG.

The target program of this example starts execution at address 1537 (hexadecimal). At this point, the second
The memory successive procedure is executed according to the contents of the address register 9 shown in the figure. Address register 9 indicates 1537 (hexadecimal), and increment/decrement circuit 1
Address 1537 (16
send).

FIG. 5 is a detailed diagram of the memory section.
Enter 01. The output of the binary/decimal converter 201 is output in hexadecimal 1000 units of the input address. Since the address buffer 8 is now outputting 1537 (hexadecimal), the address bus 41 is in the state where A12=1°AI3~Al5=00. The binary/decimal converter 201 is
The states of these signals AI2 to A15 are decoded and
Outputs 1000. A100O is a signal for selecting the target log unit (1) 53-1 and is activated. Furthermore, the signals A8 to A of the address bus 41
ll is directly sent to the target program section (1) 53-1. Further, the address information on the data bus 40 is taken out by the address latch section 2074C and then output from the data bus 40, and the address information is read out from the data bus 40.

It is directly sent to the target program section (1) 53-IK together with signals 8 to All on the bus 41. At this time, signal A
O, A7. A8 to All are AO-A2=1°A3=0
．． A4-A5=1. A6-A7=O, A8=1. A9=
O, A10=1. A11=00 state, and when expressed in hexadecimal with AQ at the bottom and All at the top, it is 537
(hexadecimal).

Looking at FIG. 6, the contents of address 1537 (hexadecimal) are 2E (hexadecimal). In addition, address 153
The first 1 in 7 (hexadecimal) is the target program section (1) 5
3-1, and the following 537 (hexadecimal) indicates the internal address of the target program section (1) 53-1. Also, the extended instruction management storage unit 2o5゜purpose program unit 53-
1 to 3 are the maximum value of hexadecimal afr/FFF (16
It is a continuous memory as a whole, although it has internal addresses up to (digital). In FIG. 6, the addresses are described as consecutive addresses.

Now, from address 1537, the target program section (1) 53-
1 puts 2E (hexadecimal) on the data bus 40 and sends it to the microprocessor unit 1 in FIG.

The microprocessor unit 1 takes out the data from the data bus 40, takes it into the data buffer 3, and completes the memory reading.

Next, the microprocessor 1 reads data 2E (hexadecimal) from the data buffer 3 and sends it to the instruction decoder 6. The instruction decoder 6 analyzes (decodes) 2E (hexadecimal) and sends it to the control circuit 7. The control circuit 7 learns that the data 2E instruction has a length of 2 bytes, and begins execution to store the second byte of the i instruction in the register 13. first,
The increment/decrement circuit 12 increments the contents of the address register 9, 1537 (hexadecimal), by +1 to 1538 (hexadecimal).0 Next, the contents of address 1538 (hexadecimal) are transferred to the data buffer using the above-mentioned memory succession procedure. Read out in 3. Here, referring to FIG. 6, 153
Since the content of address 8 (hexadecimal) is 01 (hexadecimal), it can be seen that the content of data buffer 3 is 01 (hexadecimal). Next, the control circuit 7 sets the contents of the data buffer 3 to L
Send to register 13. Further, the contents of the address register 9 are incremented by +1 by the increment/decrement circuit 12 to 1539 (hexadecimal), and the execution of this instruction is completed.

Now, FIG. 8 will be explained. First, the ADD method is a trace of the contents of the address register 9, and the trace is a trace of the movement of an instruction, and the instruction part is expressed in an assembly language. The next ACC is the contents of the calculation register 4 in 4.9. H-REG
indicates the contents of the H register 14, L-REG indicates the contents of the L register 13, and SP indicates the contents of the stack register 10.

Now, in FIG. 8, when ADD==1537 (the content of address register 9 is 1537 hexadecimal), the MVIL instruction (corresponding to 2E (hexadecimal) K) shown in the trace is issued one after another, and as mentioned above, the address register is 1538 (1537 hexadecimal). (hexadecimal), and 01 (hexadecimal) is written from the memory.

Next, returning to FIG. 7, 1539 of address register 9
(Hexadecimal) Read address D7 (Hexadecimal).

Here, the 2E (hexadecimal) (MVIL) instruction at address 1537 (hexadecimal) is analyzed by the instruction decoder 6, and the control circuit 7 processes the instruction as a 2-byte length.
Hexadecimal) is originally defined in the control circuit 7 as a 1-byte long instruction, and as shown in ADDB item 1539 in Figure 7, 2
After B7 (hexadecimal) as a byte length instruction, IC04 (1
Even if B7 (hexadecimal) (address 153A) exists, it is not considered part of the instruction, so in this tt, after the instruction B7 (hexadecimal) is executed, 04 at address 153A may be executed as a new instruction. . That is, address 1539.

j; D704 (2 bytes in hexadecimal) stored in number 153A To make the instruction t-2 bytes long, K is the instruction decoder 6
, must be a command other than the physically defined command of the control circuit 7. Such instructions are expressed as extended instructions.

Return to the beginning and write B7 (hexadecimal) f to data buffer 3:
I will explain after reading it out. First, B7 (hexadecimal) enters the instruction decoder 6. FIG. 3 shows a part of the instruction decoder 6, in which B7 (hexadecimal) is set in the instruction latch circuit 202. Here, B7 (hexadecimal) is the instruction latch circuit 202
BQ, Bl.

B2. B4. B6 and B7 are 1. B3. BS corresponds to the O state. ANDGATE 203 is BQ.

Bl, B2. With the positive logic AND gate of B6 and B7, the output of the above D7 (hexadecimal) K and pyy gate 203 is 1.
Tonai. The output of the AND gate 203 is the start instruction decode output. Furthermore, 1 This output is B3 of the input command
．． Since the conditions for B4 and B5 are dangerous, B3. B4
By combining B5 and B5, 8 types of glue start commands can be created, and these 8 types of glue start commands are expressed in hexadecimal 07.
C.F.

B7. DF, B7. They become EF, F7 and FF.

Write these start commands in assembly language.
R8T1. R8T2. Rf9T3.几ST4゜R8T
5. They will be expressed as 几8T5 and R8T7.

Now, when the restart instruction is decoded by the instruction decoder 6, the control circuit 7 causes the increment/decrement circuit 12 to increment the contents of the address register 9 by +1.
53A (hexadecimal).

Next, the contents of address register 9 are saved.

The save is made to the stack section 55, and the address on the stack 1ls55 to be saved is created using the stack register IO. First, assuming that the current content of the stack register IO is 4400 (hexadecimal), the control circuit 7 increments the content of the stack register 10 by 1 using the increment/decrement circuit, and changes the content to 43FF (16
address 43 via address buffer 8 as
The FF is supplied to the memory unit 2. Next, the lower 8B port (currently 3A (multiple base)) of the address register 9 (16-bit configuration) is sent to the memory unit 2 through the t-data buffer 3.

The memory section 2 provides an address to the stack section 55 of the variable/stack section 206 in FIG. 5 in the same manner as the above-mentioned reading method. Then, data on the data bus 40 is written to the given address, contrary to the reading operation. Note that the variable/stack unit 206 is called a read/write memory and is used to temporarily store data.

Next, the contents of the stack register 10 are again decremented by 1 using the method described above to become 43FE, and the contents of the address register 9 are
The upper gBit (currently 15 (hexadecimal)) of is written to address 43Fg.

As the next step, the control circuit 7 generates a new address using logic as shown in FIG.

In FIG. 4, the contents of the instruction latch circuit 202 are 8 ports 3,
Contents of Bit 4 and Bit 5 A3. A4゜A5
is as it is, 8 bits 3゜Bit 4, 8 of address register 9
Enter bit 5 (counting from Bit □) and OK all other parts of address register 9. The actual relationship between the contents of the instruction latch circuit 202 and the contents of the address register 9 is described in FIG. As shown in Figure 4, instruction D7 (R8T2)
Then, the control circuit 7 controls the contents of the address register 9 to 0010, and ends the instruction D7.

As described above, the program enters the extended instruction analysis and return address setting means and starts setting the return address at address ADDB0010 in FIG.

Data is successively output from address 0010 using the method described above.

The content is E3 (hexadecimal), which is analyzed by the instruction decoder 6, and the control circuit 7 enters into instruction execution control. That is, the control circuit 7 transfers the contents of the stack register 10 to the address buffer 8, as shown after ADD 0O10 in FIG.
15, which is the content of the 43rd FB address of the stack section 55 of the memory section 2, is successively sent to the memory section 2 and placed in the upper 8" bits of the temporary register 19. Next, the contents of the stack register 10 are incremented by +1 by the increment/decrement circuit 12. The value 43FF is sent to the address buffer 8. At this time, the contents of the stack register 10 are i of 43FE.
tNo change. Furthermore, 43 via the address buffer 78
3A, which is the content of the FB address, is read out and placed in the lower gBits of the temporary register 19. Next, the content 00 of the H register 14 is transferred to the data buffer 3 and written to the corresponding position in the stack section 55 indicated by the address buffer 8 (currently 43FF). Next, move the contents of the KL register, 01, to the data buffer 3. Then, 43FB, which is the content of stack register 10, is transferred to address buffer 8, and 01t
- Move the contents of the 0th and 1st temporary registers 19 to the H and Lv registers to be written to the corresponding positions in the stack section 55. Finally, the increment/decrement circuit 12 increments the contents of the address register 9 by +1 to 0011.
shall be.

As described above, the instruction E3 moves the contents of the address indicated by the current stack register 10 and the contents of the address +1 (data saved in the stack) to the H1L register, and
This is an instruction to save the contents of the L register to the stack.
Let the lower BBit be the L register. With a 15-bit register bare, the control circuit 7 can be processed as a 16-bit register. ) is 153A (hexadecimal).

This 153A is the address of the second byte of the extended instruction.

Next, the contents of address 0011 are executed. address 0
The content of 011 is 7E (hexadecimal), and the contents of the H1L register bare are sent to the address buffer 8, and the address is used to send the second byte of the extended instruction to the memory section 20 and the target program section 53. This is an instruction to transfer the data to the arithmetic register 4 and cause the address register 9 to be incremented by 6+ by the increment/decrement circuit 12. The columns of ADDR items 0011 and 153A in FIG. 8 show the contents of each register at the time of reading.

Note that the contents of the calculation register 4 (currently 04 (1)
Hexadecimal)) is used as an extended instruction execution parameter in the extended instruction execution unit 52.

Next, the program moves to execution of address 0012. As shown in FIG. 6, the content of address 0012 is 23 (hexadecimal), and the microprocessor unit 1 in FIG. 23 is analyzed by the instruction decoder 6, and the 23 (hexadecimal) instruction is processed by the increment/decrement circuit 12 for the contents of the H and L register pair.
Execute the function to increase by 1. As a result, the contents of the H and L registers change from 15.3A to 15.3B.

This 15.3B is ADDR term 153 when referring to FIG.
The return address of the extended instruction is calculated corresponding to address 153B (hexadecimal) of the next instruction after 9 (extended instruction).
This means that you have entered the L register bear. Finally, increase the contents of address register 9 by +1 to 0013 and make it 23.
Execution of the (hexadecimal) instruction ends.

In FIG. 8, ADDROO13 is ADD 0010
With the same instruction as above, stack register IOK
The contents of the stack section 55 of the memory section 2 and H
H with the command to mutually exchange the contents of the 1Lv register pair and gold.
, L register pair busy next instruction address, ie return 9
The return address is set by saving the address in the stack section 55. Also, with ADDfLOolo, the saved H
, restores the contents of the L register, and finally increments the contents of address register 9 by +1 to 0014.

Next, when the instruction at address 0014 is read, the microprocessor unit IVi analyzes the contents. Instruction C3 at address 0014 is an instruction called a jump instruction.
Following the address <Contents of address 0015,0016 t-Continuing,
Execute the function to set the address register 9 and end the instruction. As a result, the next instruction execution is 0015,0016
It is executed from the address determined by the contents of the address. 8th
In the figure, the content of address 0015 is 52 (hexadecimal), which is the lower BBit of the address register 9, and the content of address 0016 is 00 (hexadecimal), which is the upper BBit of the address register 9. Therefore, the contents of the address register are
0052 (hexadecimal), as shown in Figure 8, 0052
Start reading the address instruction.

The instruction 26 at address 0052 is an instruction to set the next 1 byte to the H register 14. The upper BBit of the address of the variable section 54 is set to address 0053, and this is read and set to the H register 14. . As shown in Figure 7, the upper 8 bits of the address of the variable section 54 are 40 (hexadecimal)
This 40 (hexadecimal) is set in the H register 14.

The next instruction F3 at address 0054 is an instruction for preventing the execution of the currently executing program from being interrupted by an external interrupt.

The next instruction B6 at address 0055 successively reads the contents of the address indicated by the HL register bear and performs DDR0055.
In this case, the HL register bear indicates address 4001, and the contents of the operation register 4 at that time are 04 (hexadecimal), with the dependent part of the extended instruction set as is. In the example of FIG. 8, the contents of the variable section 54 at address 4001 are currently 80 (1
84 (hexadecimal) by executing this instruction B6.
becomes.

This is a dependent part of the extended instruction and changes the contents of the target variable part 54.

The next instruction FB at address 0056 is an instruction that allows interrupts from the outside.

The next instruction 77 at address 0057 writes the contents 84 (hexadecimal) of the calculation register 4 obtained at address 0055 to the address indicated by the HL register pair. According to this, υ is 400 in the variable part.
This means that the contents of address 1 have been changed from 80 (hexadecimal) to 84 (hexadecimal)K.

The next instruction is at address 0058, and this instruction C9 is the return address (153B (16M)) saved in the stack section 55.
This is an instruction to input the address register 9 into the address register 9. Execution of this instruction ends the execution of the extended instruction. As shown in Figure 7,
The next instruction after the extended instruction at address 1539 is address 153B, and the instructions are subsequently executed in the normal instruction order.

Next, another example will be briefly explained.

The example shown in Figure 9 is an example of a wa mouth extension command.
DDR1661 and 1668 (hexadecimal) instructions are extended instructions. FIGS. 10G) and 10(b) show these operations in the order of execution.

In the above explanation, the beam start instruction was used as an example, but the instructions that can be expanded are not limited to this. By executing the instruction, the address storing the next instruction to be executed is saved and branched to a specific address. The present invention can be applied to instructions that have the function of

FIG. 11 is for explaining a comparison with the conventional method. The left side of FIG. 11 shows an example of programming using the conventional method, and the right side shows a case using the extended instructions of the present invention.

In FIG. 11, reference numeral 301 indicates a program for the function of writing to the MCALM area.

In this case, if programming is done using the conventional method on the left, the instruction L that reads the contents of the address of the calculation register KMCALM
DA MCALMl and the contents of the calculation register and 16
It consists of an 0RI04H instruction that creates a logical sum of decimal 04, and a STA MCALM instruction that returns the result of the logical sum to the MCALM address, and uses 8 bytes of memory in this example.

On the other hand, in the method of the embodiment on the right, an instruction MVIL sets the target address MCALM in the L register, an extended instruction F8ETI 04H that updates the contents by creating a logical sum of MCALM and the set target address (MCALM) Ic.
It consists of 4 bytes of memory.

In this example, the number of bytes used for the 4-byte memory is reduced compared to when programming using the conventional method.

Next, an example of reference numeral 302 is a microprocessor O8
This is a program that instructs the (operating system) to make a meeting.

In this case, if programmed using the conventional method on the left, MVIA, READY-
It consists of a HAM instruction and a CALLWAITCL instruction that calls a subroutine for waiting, and uses 5 bytes of memory.

- If programmed according to the method of the embodiment, only the extended command WAIT 几EADY-HAM is used for queuing, and the part specifying what the queuing is for as shown in the conventional example is also included in the extended command. It is.

This extended instruction uses 2 bytes of memory, and compared to the conventional example, the number of memory usage bytes is reduced by 3 bytes. As described above, by using the extended instructions of this embodiment, the number of bytes of memory used can be reduced, and when such instructions occur frequently, the amount of memory used can be significantly reduced.

(Effects of the Invention) The present invention has the effect that the amount of memory used can be significantly reduced by configuring a specific instruction to be used as an extended instruction.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a detailed block diagram of Fig. 1, Fig. 3 is a partial circuit diagram of the instruction decoder shown in Fig. 2, and Fig. 4 is a beam start instruction. 5 is a detailed block diagram of the memory section of FIG. 2, FIG. 6 is a data storage diagram of the memory section of FIG. 2, and FIG. 7 is a diagram for explaining the operation of FIG. 2. FIG. 8 is a trace diagram of the program in FIG. 7, FIG. 9 is a diagram showing the second example program for explaining the operation in FIG. 2, and FIG. a) and (b) are trace diagrams of the program shown in FIG. 9, and FIG. 11 is a diagram showing a comparison between the conventional example and the present invention in the embodiment. 1...Micro processor unit, 2...
...Memory section, 3...Data buffer, 4.
... Arithmetic register, 5... Arithmetic circuit,
6...Instruction decoder, 7...Control circuit, 8...Address buffer, 9...Address register, 10...Stack register,
11...Register control unit, 12...Increment/decrement circuit, 13...L
Register, 14...H register, 15・Mountain...
E register, 16... D register, 17...
...C register, 18...B register, 50
...Extended instruction analysis section, 51...Return address setting section, 52...Extended instruction execution section, 53
, 53-1. 53-2. 53-3...Object program section, 54...Variable section, 55...
...Stack unit, 100...Microprocessor, 101...Object program storage means, 1
02... Storage means for managing extended commands, 103...
...Extended instruction analysis means, 104...Return address setting means, 105...Extended instruction execution means, 106...Physical instruction analysis means, 107...
... Instruction execution means other than restart, 108.
... Restart execution means, 109 ... Address register, 201 ... Binary-to-decimal converter, 202 ... Instruction latch circuit, 203 ...
...And gate, 205...Extended instruction management storage section, 206...Variable/stack section, 207.
...Address latch section. Mine 1m Mayuzumi 4-Kisei 6-kiri (long) Hachijo old

Claims (1)

[Scope of Claims] Command analysis means for analyzing a command; and when the command analysis means detects that the command is a predetermined specific command, the command analysis means continues executing a special command consisting of the specific command and its subordinate parts. return address setting means for setting a memory address for storing an instruction to be executed next; special instruction analysis means for receiving and analyzing the special instruction; and based on the analysis result of the special instruction analysis means. A microprocessor instruction extension method for extending execution of the specific instruction to the special instruction, the method including special instruction execution means for executing the special instruction and transferring execution to the instruction stored at the return address after execution.